Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22908459	1		T1	11635		T2	13		T3	336
full_word	7803472	1		T1	2775		T3	123		T4	35564

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30711631	1		T1	14410		T2	13		T3	459
auto[TlIntgErrCmd]	104	1		T74	7		T114	6		T225	8
auto[TlIntgErrData]	92	1		T74	1		T114	7		T225	7
auto[TlIntgErrBoth]	104	1		T74	2		T114	7		T225	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26340686	1		T1	12547		T2	12		T3	372
auto[1]	4371245	1		T1	1863		T2	1		T3	87

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22222372	1		T1	11356		T2	12		T3	319
auto[TlIntgErrNone]	partial	auto[1]	685821	1		T1	279		T2	1		T3	17
auto[TlIntgErrNone]	full_word	auto[0]	4118180	1		T1	1191		T3	53		T4	27616
auto[TlIntgErrNone]	full_word	auto[1]	3685258	1		T1	1584		T3	70		T4	7948
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T74	4		T114	2		T225	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T74	2		T114	3		T225	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T281	1		T388	1		T389	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T74	1		T114	1		T288	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T114	4		T225	4		T248	1
auto[TlIntgErrData]	partial	auto[1]	40	1		T74	1		T114	2		T225	3
auto[TlIntgErrData]	full_word	auto[0]	9	1		T114	1		T281	2		T288	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T390	1		T387	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T114	2		T225	1		T248	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T74	2		T114	4		T225	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T114	1		T281	1		T391	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T225	1		T281	1		T284	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18524	1		T74	10		T114	16		T115	816
full_word	3697430	1		T1	178		T3	7		T4	16215

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3715678	1		T1	178		T3	7		T4	16215
auto[TlIntgErrCmd]	91	1		T74	5		T114	6		T225	5
auto[TlIntgErrData]	103	1		T74	1		T114	8		T225	8
auto[TlIntgErrBoth]	82	1		T74	4		T114	5		T225	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3692474	1		T1	178		T3	7		T4	16215
auto[1]	23480	1		T74	7		T114	12		T115	898

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1210	1		T115	82		T116	4		T224	1
auto[TlIntgErrNone]	partial	auto[1]	17062	1		T115	734		T116	95		T224	121
auto[TlIntgErrNone]	full_word	auto[0]	3691159	1		T1	178		T3	7		T4	16215
auto[TlIntgErrNone]	full_word	auto[1]	6247	1		T115	164		T116	18		T224	40
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T74	1		T114	2		T225	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T74	4		T114	4		T225	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T390	1		T392	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T248	1		T284	1		T387	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T114	3		T225	4		T248	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T74	1		T114	3		T225	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T114	1		T225	1		T384	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T114	1		T225	2		T277	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T74	2		T114	1		T225	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T74	2		T114	3		T225	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T225	2		T277	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T114	1		T225	1		T284	1