Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_lfsr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lfsr 100.00 100.00



Module Instance : tb.dut.u_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_lfsr
TotalCoveredPercent
Totals 6 6 100.00
Total Bits 136 136 100.00
Total Bits 0->1 68 68 100.00
Total Bits 1->0 68 68 100.00

Ports 6 6 100.00
Port Bits 136 136 100.00
Port Bits 0->1 68 68 100.00
Port Bits 1->0 68 68 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T18 Yes T1,T2,T3 INPUT
seed_en_i Yes Yes T13,T39,T52 Yes T13,T39,T52 INPUT
seed_i[31:0] Yes Yes T13,T118,T85 Yes T13,T119,T118 INPUT
lfsr_en_i Yes Yes T13,T39,T52 Yes T13,T39,T52 INPUT
entropy_i[31:0] Unreachable Unreachable Unreachable INPUT
state_o[31:0] Yes Yes T13,T39,T52 Yes T13,T39,T52 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%