Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T14
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1600838576	1597647256	0	0
CheckNGreaterZero_A	4208	4208	0	0
GntImpliesReady_A	1600838576	385478612	0	0
GntImpliesValid_A	1600838576	385478612	0	0
GrantKnown_A	1600838576	1597647256	0	0
IdxKnown_A	1600838576	1597647256	0	0
IndexIsCorrect_A	1600838576	385478612	0	0
NoReadyValidNoGrant_A	1600838576	175785152	0	0
Priority_A	1600838576	408882010	0	0
ReadyAndValidImplyGrant_A	1600838576	385478612	0	0
ReqAndReadyImplyGrant_A	1600838576	385478612	0	0
ReqImpliesValid_A	1600838576	408882010	0	0
ValidKnown_A	1600838576	1597647256	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	1597647256	0	0
T1	124004	123608	0	0
T2	4644	4344	0	0
T3	7452	6832	0	0
T4	3567240	3566632	0	0
T5	12324	11424	0	0
T13	1543344	1543292	0	0
T17	6232	5852	0	0
T18	22436	20144	0	0
T19	980384	980028	0	0
T20	761732	760964	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4208	4208	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	385478612	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	63466	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	40454	0	0
T9	0	16942	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	385478612	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	63466	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	40454	0	0
T9	0	16942	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	1597647256	0	0
T1	124004	123608	0	0
T2	4644	4344	0	0
T3	7452	6832	0	0
T4	3567240	3566632	0	0
T5	12324	11424	0	0
T13	1543344	1543292	0	0
T17	6232	5852	0	0
T18	22436	20144	0	0
T19	980384	980028	0	0
T20	761732	760964	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	1597647256	0	0
T1	124004	123608	0	0
T2	4644	4344	0	0
T3	7452	6832	0	0
T4	3567240	3566632	0	0
T5	12324	11424	0	0
T13	1543344	1543292	0	0
T17	6232	5852	0	0
T18	22436	20144	0	0
T19	980384	980028	0	0
T20	761732	760964	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	385478612	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	63466	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	40454	0	0
T9	0	16942	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	175785152	0	0
T1	124004	4420	0	0
T2	4644	256	0	0
T3	7452	746	0	0
T4	3567240	2022784	0	0
T5	12324	828	0	0
T7	0	3696	0	0
T8	0	1242994	0	0
T9	0	563226	0	0
T13	1543344	2109952	0	0
T17	6232	256	0	0
T18	22436	3310	0	0
T19	980384	256	0	0
T20	761732	512	0	0
T26	0	12	0	0
T45	0	157314	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	408882010	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	566822	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	290042	0	0
T9	0	309242	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	385478612	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	63466	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	40454	0	0
T9	0	16942	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	385478612	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	63466	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	40454	0	0
T9	0	16942	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	408882010	0	0
T1	124004	42088	0	0
T2	4644	64	0	0
T3	7452	360	0	0
T4	3567240	566822	0	0
T5	12324	232	0	0
T7	0	62228	0	0
T8	0	290042	0	0
T9	0	309242	0	0
T13	1543344	514598	0	0
T17	6232	64	0	0
T18	22436	1384	0	0
T19	980384	427544	0	0
T20	761732	335924	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600838576	1597647256	0	0
T1	124004	123608	0	0
T2	4644	4344	0	0
T3	7452	6832	0	0
T4	3567240	3566632	0	0
T5	12324	11424	0	0
T13	1543344	1543292	0	0
T17	6232	5852	0	0
T18	22436	20144	0	0
T19	980384	980028	0	0
T20	761732	760964	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T14
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400209644	399411814	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	400209644	98586373	0	0
GntImpliesValid_A	400209644	98586373	0	0
GrantKnown_A	400209644	399411814	0	0
IdxKnown_A	400209644	399411814	0	0
IndexIsCorrect_A	400209644	98586373	0	0
NoReadyValidNoGrant_A	400209644	45398970	0	0
Priority_A	400209644	104284263	0	0
ReadyAndValidImplyGrant_A	400209644	98586373	0	0
ReqAndReadyImplyGrant_A	400209644	98586373	0	0
ReqImpliesValid_A	400209644	104284263	0	0
ValidKnown_A	400209644	399411814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586373	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586373	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586373	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	45398970	0	0
T1	31001	1610	0	0
T2	1161	128	0	0
T3	1863	365	0	0
T4	891810	546417	0	0
T5	3081	414	0	0
T13	385836	530688	0	0
T17	1558	128	0	0
T18	5609	1299	0	0
T19	245096	128	0	0
T20	190433	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	104284263	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	153004	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586373	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586373	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	104284263	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	153004	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T14
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400209644	399411814	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	400209644	98586283	0	0
GntImpliesValid_A	400209644	98586283	0	0
GrantKnown_A	400209644	399411814	0	0
IdxKnown_A	400209644	399411814	0	0
IndexIsCorrect_A	400209644	98586283	0	0
NoReadyValidNoGrant_A	400209644	45398970	0	0
Priority_A	400209644	104284173	0	0
ReadyAndValidImplyGrant_A	400209644	98586283	0	0
ReqAndReadyImplyGrant_A	400209644	98586283	0	0
ReqImpliesValid_A	400209644	104284173	0	0
ValidKnown_A	400209644	399411814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586283	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586283	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586283	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	45398970	0	0
T1	31001	1610	0	0
T2	1161	128	0	0
T3	1863	365	0	0
T4	891810	546417	0	0
T5	3081	414	0	0
T13	385836	530688	0	0
T17	1558	128	0	0
T18	5609	1299	0	0
T19	245096	128	0	0
T20	190433	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	104284173	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	153004	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586283	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	98586283	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	17304	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	104284173	0	0
T1	31001	14975	0	0
T2	1161	32	0	0
T3	1863	176	0	0
T4	891810	153004	0	0
T5	3081	116	0	0
T13	385836	129402	0	0
T17	1558	32	0	0
T18	5609	492	0	0
T19	245096	103246	0	0
T20	190433	78160	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T8
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T8
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400209644	399411814	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	400209644	94152953	0	0
GntImpliesValid_A	400209644	94152953	0	0
GrantKnown_A	400209644	399411814	0	0
IdxKnown_A	400209644	399411814	0	0
IndexIsCorrect_A	400209644	94152953	0	0
NoReadyValidNoGrant_A	400209644	42493612	0	0
Priority_A	400209644	100156756	0	0
ReadyAndValidImplyGrant_A	400209644	94152953	0	0
ReqAndReadyImplyGrant_A	400209644	94152953	0	0
ReqImpliesValid_A	400209644	100156756	0	0
ValidKnown_A	400209644	399411814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94152953	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94152953	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94152953	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	42493612	0	0
T1	31001	600	0	0
T2	1161	0	0	0
T3	1863	8	0	0
T4	891810	464975	0	0
T5	3081	0	0	0
T7	0	1848	0	0
T8	0	621497	0	0
T9	0	281613	0	0
T13	385836	524288	0	0
T17	1558	0	0	0
T18	5609	356	0	0
T19	245096	0	0	0
T20	190433	0	0	0
T26	0	6	0	0
T45	0	78657	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	100156756	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	130407	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	145021	0	0
T9	0	154621	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94152953	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94152953	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	100156756	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	130407	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	145021	0	0
T9	0	154621	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T8
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T18,T8
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400209644	399411814	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	400209644	94153003	0	0
GntImpliesValid_A	400209644	94153003	0	0
GrantKnown_A	400209644	399411814	0	0
IdxKnown_A	400209644	399411814	0	0
IndexIsCorrect_A	400209644	94153003	0	0
NoReadyValidNoGrant_A	400209644	42493600	0	0
Priority_A	400209644	100156818	0	0
ReadyAndValidImplyGrant_A	400209644	94153003	0	0
ReqAndReadyImplyGrant_A	400209644	94153003	0	0
ReqImpliesValid_A	400209644	100156818	0	0
ValidKnown_A	400209644	399411814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94153003	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94153003	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94153003	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	42493600	0	0
T1	31001	600	0	0
T2	1161	0	0	0
T3	1863	8	0	0
T4	891810	464975	0	0
T5	3081	0	0	0
T7	0	1848	0	0
T8	0	621497	0	0
T9	0	281613	0	0
T13	385836	524288	0	0
T17	1558	0	0	0
T18	5609	356	0	0
T19	245096	0	0	0
T20	190433	0	0	0
T26	0	6	0	0
T45	0	78657	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	100156818	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	130407	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	145021	0	0
T9	0	154621	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94153003	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	94153003	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	14429	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	20227	0	0
T9	0	8471	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	100156818	0	0
T1	31001	6069	0	0
T2	1161	0	0	0
T3	1863	4	0	0
T4	891810	130407	0	0
T5	3081	0	0	0
T7	0	31114	0	0
T8	0	145021	0	0
T9	0	154621	0	0
T13	385836	127897	0	0
T17	1558	0	0	0
T18	5609	200	0	0
T19	245096	110526	0	0
T20	190433	89802	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400209644	399411814	0	0
T1	31001	30902	0	0
T2	1161	1086	0	0
T3	1863	1708	0	0
T4	891810	891658	0	0
T5	3081	2856	0	0
T13	385836	385823	0	0
T17	1558	1463	0	0
T18	5609	5036	0	0
T19	245096	245007	0	0
T20	190433	190241	0	0