Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26449943	1		T1	131928		T2	21924		T3	7809
full_word	7694524	1		T1	878		T2	12348		T3	13397

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34144187	1		T1	132806		T2	34272		T3	21206
auto[TlIntgErrCmd]	89	1		T105	6		T106	2		T243	3
auto[TlIntgErrData]	93	1		T105	6		T106	5		T243	1
auto[TlIntgErrBoth]	98	1		T105	8		T106	3		T243	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29725405	1		T1	131965		T2	25100		T3	13849
auto[1]	4419062	1		T1	841		T2	9172		T3	7357

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25784405	1		T1	131880		T2	20730		T3	7499
auto[TlIntgErrNone]	partial	auto[1]	665275	1		T1	48		T2	1194		T3	310
auto[TlIntgErrNone]	full_word	auto[0]	3940885	1		T1	85		T2	4370		T3	6350
auto[TlIntgErrNone]	full_word	auto[1]	3753622	1		T1	793		T2	7978		T3	7047
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T105	2		T106	1		T243	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T105	3		T106	1		T243	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T392	1		T387	1		T393	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T105	1		T280	1		T388	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T105	2		T106	1		T243	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T105	4		T106	3		T280	5
auto[TlIntgErrData]	full_word	auto[0]	1	1		T386	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T106	1		T386	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T105	4		T106	1		T243	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T105	4		T106	1		T243	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T106	1		T243	1		T388	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T257	1		T261	1		T389	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17501	1		T108	446		T109	300		T105	17
full_word	3772112	1		T1	204		T18	9		T4	232

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3789357	1		T1	204		T18	9		T4	232
auto[TlIntgErrCmd]	79	1		T105	5		T106	3		T243	3
auto[TlIntgErrData]	89	1		T105	5		T106	2		T243	4
auto[TlIntgErrBoth]	88	1		T105	8		T106	5		T243	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3765418	1		T1	204		T18	9		T4	232
auto[1]	24195	1		T108	571		T109	534		T105	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	966	1		T108	7		T239	46		T107	12
auto[TlIntgErrNone]	partial	auto[1]	16304	1		T108	439		T109	300		T239	383
auto[TlIntgErrNone]	full_word	auto[0]	3764347	1		T1	204		T18	9		T4	232
auto[TlIntgErrNone]	full_word	auto[1]	7740	1		T108	132		T109	234		T239	219
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T105	1		T280	3		T257	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T105	4		T106	3		T243	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T261	1		T386	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T280	1		T257	2		T394	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T105	2		T243	2		T280	2
auto[TlIntgErrData]	partial	auto[1]	45	1		T105	3		T106	1		T243	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T106	1		T257	1		T388	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T313	1		T389	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T105	5		T106	3		T261	4
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T105	2		T106	2		T243	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T105	1		T280	1		T257	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T243	1		T261	1		T387	1