Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.58	100.00	73.66			96.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo	83.96	100.00	65.52			85.71	84.62
tb.dut.u_to_rd_fifo	92.89	100.00	75.00			96.55	100.00
tb.dut.u_tl_adapter_eflash	94.26	100.00	80.47			96.55	100.00

---

Module Instance : tb.dut.u_to_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.96	100.00	65.52			85.71	84.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.77	89.66	65.61			82.56	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	87.32	100.00	74.29			75.00	100.00
u_reqfifo	92.36	100.00	75.00			94.44	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	69.33	91.43	57.14			68.75	60.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	72.63	94.44	54.84			81.25	60.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.89	100.00	75.00			96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.03	87.86	75.35	80.00		86.96	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	66.91	76.92	65.71			25.00	100.00
u_reqfifo	86.36	100.00	71.79	70.00		90.00	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	98.30	100.00	91.49	100.00		100.00	100.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	85.85	100.00	69.23	70.00		90.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.26	100.00	80.47			96.55	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.13	92.89	80.86	97.66		94.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
gen_data_xor_addr_fifo.u_sramreqaddrfifo	96.53	100.00	86.11			100.00	100.00
u_err	79.64	100.00	68.57			50.00	100.00
u_reqfifo	94.41	100.00	82.05	90.00		100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	95.02	100.00	85.11	90.00		100.00	100.00
u_sram_byte	100.00	100.00					100.00
u_sramreqfifo	94.41	100.00	82.05	90.00		100.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
83.96	100.00

tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		68	68	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	279	8	8	100.00
ALWAYS	299	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	3	3	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	423	6	6	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	0	0
CONT_ASSIGN	477	0	0
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	486	0	0
ALWAYS	492	4	4	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	0	0
CONT_ASSIGN	620	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132		unreachable
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
162	1	1
176	1	1
188	1	1
272	1	1
273	1	1
274	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
289	1	1
292	1	1
299	1	1
301	1	1
302	1	1
303	1	1
305	1	1
308	1	1
313	1	1
317	1	1
336	1	1
341	1	1
347	1	1
359	1	1
362	1	1
363	1	1
365	1	1
369	1	1
390	1	1
391	1	1
392	1	1
393	1	1
423	1	1
424	1	1
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
438	1	1
439	1	1
440	1	1
			MISSING_ELSE
446	1	1
447	1	1
456	1	1
457	1	1
459	1	1
460	1	1
467	1	1
470	1	1
474	1	1
475		unreachable
477		unreachable
479	1	1
486		unreachable
492	1	1
496	1	1
498	1	1
504		unreachable
510	1	1
			MISSING_ELSE
526	1	1
531	1	1
536		unreachable
620	1	1

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
92.89	100.00

tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		72	72	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	279	8	8	100.00
ALWAYS	299	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	3	3	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	423	6	6	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
ALWAYS	492	4	4	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	0	0
CONT_ASSIGN	620	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
272	1	1
273	1	1
274	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
289	1	1
292	1	1
299	1	1
301	1	1
302	1	1
303	1	1
305	1	1
308	1	1
313	1	1
317	1	1
336	1	1
341	1	1
347	1	1
359	1	1
362	1	1
363	1	1
365	1	1
369	1	1
390	1	1
391	1	1
392	1	1
393	1	1
423	1	1
424	1	1
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
438	1	1
439	1	1
440	1	1
			MISSING_ELSE
446	1	1
447	1	1
456	1	1
457	1	1
459	1	1
460	1	1
467	1	1
470	1	1
474	1	1
475	1	1
477	1	1
479	1	1
486	1	1
492	1	1
496	1	1
498	1	1
504		unreachable
510	1	1
			MISSING_ELSE
526	1	1
531	1	1
536		unreachable
620	1	1

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
94.26	100.00

tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	279	8	8	100.00
ALWAYS	299	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	3	3	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	423	6	6	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
ALWAYS	492	4	4	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
272	1	1
273	1	1
274	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
289	1	1
292	1	1
299	1	1
301	1	1
302	1	1
303	1	1
305	1	1
308	1	1
313	1	1
317	1	1
336	1	1
341	1	1
347	1	1
359	1	1
362	1	1
363	1	1
365	1	1
369	1	1
390	1	1
391	1	1
392	1	1
393	1	1
423	1	1
424	1	1
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
438	1	1
439	1	1
440	1	1
			MISSING_ELSE
446	1	1
447	1	1
456	1	1
457	1	1
459	1	1
460	1	1
467	1	1
470	1	1
474	1	1
475	1	1
477	1	1
479	1	1
486	1	1
492	1	1
496	1	1
498	1	1
504	1	1
510		unreachable
			MISSING_ELSE
526	1	1
531	1	1
536		unreachable

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
83.96	65.52

tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	116	76	65.52
Logical	116	76	65.52
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T4
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T43
1	1	Covered	T1,T2,T3

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
92.89	75.00

tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	124	93	75.00
Logical	124	93	75.00
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T13,T14,T15
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T13,T14,T15
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Covered	T13,T14,T15
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T4
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T44,T45
1	1	Covered	T1,T2,T3

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T24,T46,T13

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T46,T13
1	1	Covered	T1,T2,T3

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T46,T13

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T3,T47,T48
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T47,T48
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
94.26	80.47

tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	128	103	80.47
Logical	128	103	80.47
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T6,T25,T26

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T6,T25,T26
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Covered	T6,T25,T26

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T2,T17,T20
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T20

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T49
0	1	Covered	T2,T50,T22
1	0	Covered	T2,T17,T20

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T50,T22
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T17,T20
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T18,T4
0	0	0	0	0	1	Covered	T6,T25,T26
0	0	0	0	1	0	Covered	T2,T51,T50
0	0	0	1	0	0	Covered	T23,T52,T53
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T54,T55,T56
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T18,T4

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T57,T58
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T18,T4

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T18,T4

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T23,T52,T53
1	0	Covered	T59,T60,T61

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T23,T52,T53
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T18,T4

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T60,T61
1	1	Covered	T1,T18,T4

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T52,T53
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T52,T53
1	1	1	Covered	T23,T52,T53

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T18,T4
1	1	Covered	T59,T60,T23

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T23,T55,T56
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T18,T4

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T52,T53
1	0	Covered	T1,T18,T4

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T23,T52,T53
1	1	1	Covered	T1,T18,T4

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T4

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Not Covered
1	1	Covered	T1,T18,T4

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T52,T53
1	1	Covered	T1,T18,T4

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		30	29	96.67
TERNARY	144	2	2	100.00
TERNARY	341	2	2	100.00
TERNARY	347	3	2	66.67
TERNARY	393	2	2	100.00
TERNARY	531	2	2	100.00
IF	129	3	3	100.00
IF	281	4	4	100.00
IF	301	3	3	100.00
IF	362	2	2	100.00
IF	426	2	2	100.00
IF	438	2	2	100.00
IF	496	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	347	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	531	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T13,T14,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if (reqfifo_rvalid)
-2-:	282	if (reqfifo_rdata.error)
-3-:	285	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T23,T52,T53
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if (reqfifo_rvalid)
-2-:	302	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	362	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	496	if ((|sramreqfifo_rdata.mask))
-2-:	498	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	1150979139	1148358435	0	0
DataIntgOptions_A	3171	3171	0	0
ReqOutKnown_A	1150979139	1148358435	0	0
SramDwHasByteGranularity_A	3171	3171	0	0
SramDwIsMultipleOfTlulWidth_A	3171	3171	0	0
TlOutKnownIfFifoKnown_A	1150979139	1148358435	0	0
TlOutValidKnown_A	1150979139	1148358435	0	0
WdataOutKnown_A	1150979139	1148358435	0	0
WeOutKnown_A	1150979139	1148358435	0	0
WmaskOutKnown_A	1150979139	1148358435	0	0
adapterNoReadOrWrite	3171	3171	0	0
rvalidHighReqFifoEmpty	1150979139	7325072	0	0
rvalidHighWhenRspFifoFull	1150362558	7318600	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3171	3171	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T9	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3171	3171	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T9	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3171	3171	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T9	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	1148358435	0	0
T1	804765	804600	0	0
T2	785934	749325	0	0
T3	593388	593154	0	0
T4	19023	18780	0	0
T9	1180227	1180185	0	0
T16	10707	10542	0	0
T17	3327	3171	0	0
T18	8136	7581	0	0
T19	4317	4110	0	0
T20	4836	4680	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	3171	3171	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T9	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150979139	7325072	0	0
T1	536510	279	0	0
T2	523956	3920	0	0
T3	395592	6144	0	0
T4	12682	348	0	0
T5	0	45155	0	0
T9	786818	0	0	0
T16	7138	0	0	0
T17	2218	0	0	0
T18	5424	73	0	0
T19	2878	0	0	0
T20	3224	0	0	0
T22	0	16251	0	0
T27	0	39080	0	0
T28	0	66	0	0
T29	0	75	0	0
T37	0	13	0	0
T44	0	33	0	0
T50	0	15	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150362558	7318600	0	0
T1	536510	279	0	0
T2	523956	3920	0	0
T3	395592	6144	0	0
T4	12682	348	0	0
T5	0	45155	0	0
T9	786818	0	0	0
T16	7138	0	0	0
T17	2218	0	0	0
T18	5424	73	0	0
T19	2878	0	0	0
T20	3224	0	0	0
T22	0	16251	0	0
T27	0	39080	0	0
T28	0	66	0	0
T29	0	75	0	0
T37	0	13	0	0
T44	0	33	0	0
T50	0	15	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		68	68	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	279	8	8	100.00
ALWAYS	299	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	3	3	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	423	6	6	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	0	0
CONT_ASSIGN	477	0	0
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	486	0	0
ALWAYS	492	4	4	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	0	0
CONT_ASSIGN	620	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132		unreachable
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
162	1	1
176	1	1
188	1	1
272	1	1
273	1	1
274	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
289	1	1
292	1	1
299	1	1
301	1	1
302	1	1
303	1	1
305	1	1
308	1	1
313	1	1
317	1	1
336	1	1
341	1	1
347	1	1
359	1	1
362	1	1
363	1	1
365	1	1
369	1	1
390	1	1
391	1	1
392	1	1
393	1	1
423	1	1
424	1	1
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
438	1	1
439	1	1
440	1	1
			MISSING_ELSE
446	1	1
447	1	1
456	1	1
457	1	1
459	1	1
460	1	1
467	1	1
470	1	1
474	1	1
475		unreachable
477		unreachable
479	1	1
486		unreachable
492	1	1
496	1	1
498	1	1
504		unreachable
510	1	1
			MISSING_ELSE
526	1	1
531	1	1
536		unreachable
620	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	116	76	65.52
Logical	116	76	65.52
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Unreachable
0	0	1	0	Unreachable
0	1	0	0	Unreachable
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Not Covered
0	0	0	1	0	Unreachable
0	0	1	0	0	Unreachable
0	1	0	0	0	Unreachable
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T4
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T43
1	1	Covered	T1,T2,T3

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T2,T3

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
Branches		28	24	85.71
TERNARY	144	2	2	100.00
TERNARY	341	2	1	50.00
TERNARY	347	3	1	33.33
TERNARY	393	2	2	100.00
TERNARY	531	2	1	50.00
IF	129	2	2	100.00
IF	281	4	4	100.00
IF	301	3	3	100.00
IF	362	2	2	100.00
IF	426	2	2	100.00
IF	438	2	2	100.00
IF	496	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	347	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	531	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if (reqfifo_rvalid)
-2-:	282	if (reqfifo_rdata.error)
-3-:	285	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T12
1	0	1	Covered	T12
1	0	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if (reqfifo_rvalid)
-2-:	302	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T12
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	362	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	496	if ((|sramreqfifo_rdata.mask))
-2-:	498	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Unreachable
1	0	Covered	T12
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	11	84.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	11	84.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	383659713	382786145	0	0
DataIntgOptions_A	1057	1057	0	0
ReqOutKnown_A	383659713	382786145	0	0
SramDwHasByteGranularity_A	1057	1057	0	0
SramDwIsMultipleOfTlulWidth_A	1057	1057	0	0
TlOutKnownIfFifoKnown_A	383659713	382786145	0	0
TlOutValidKnown_A	383659713	382786145	0	0
WdataOutKnown_A	383659713	382786145	0	0
WeOutKnown_A	383659713	382786145	0	0
WmaskOutKnown_A	383659713	382786145	0	0
adapterNoReadOrWrite	1057	1057	0	0
rvalidHighReqFifoEmpty	383659713	0	0	0
rvalidHighWhenRspFifoFull	383659713	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	0	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		72	72	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	279	8	8	100.00
ALWAYS	299	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	3	3	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	423	6	6	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
ALWAYS	492	4	4	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	0	0
CONT_ASSIGN	620	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
272	1	1
273	1	1
274	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
289	1	1
292	1	1
299	1	1
301	1	1
302	1	1
303	1	1
305	1	1
308	1	1
313	1	1
317	1	1
336	1	1
341	1	1
347	1	1
359	1	1
362	1	1
363	1	1
365	1	1
369	1	1
390	1	1
391	1	1
392	1	1
393	1	1
423	1	1
424	1	1
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
438	1	1
439	1	1
440	1	1
			MISSING_ELSE
446	1	1
447	1	1
456	1	1
457	1	1
459	1	1
460	1	1
467	1	1
470	1	1
474	1	1
475	1	1
477	1	1
479	1	1
486	1	1
492	1	1
496	1	1
498	1	1
504		unreachable
510	1	1
			MISSING_ELSE
526	1	1
531	1	1
536		unreachable
620	1	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	124	93	75.00
Logical	124	93	75.00
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Covered	T13,T14,T15
1	0	0	0	Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T13,T14,T15
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Covered	T13,T14,T15
1	0	0	0	0	Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T16,T4
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T44,T45
1	1	Covered	T1,T2,T3

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T2,T3

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T24,T46,T13

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T46,T13
1	1	Covered	T1,T2,T3

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T46,T13

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T3,T47,T48
1	1	0	1	Not Covered
1	1	1	0	Unreachable
1	1	1	1	Covered	T1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T47,T48
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
TERNARY	144	2	2	100.00
TERNARY	341	2	2	100.00
TERNARY	347	3	2	66.67
TERNARY	393	2	2	100.00
TERNARY	531	2	2	100.00
IF	129	3	3	100.00
IF	281	4	4	100.00
IF	301	3	3	100.00
IF	362	2	2	100.00
IF	426	2	2	100.00
IF	438	2	2	100.00
IF	496	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	347	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	531	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if (reqfifo_rvalid)
-2-:	282	if (reqfifo_rdata.error)
-3-:	285	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T12
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T12
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if (reqfifo_rvalid)
-2-:	302	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	362	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	496	if ((|sramreqfifo_rdata.mask))
-2-:	498	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Unreachable
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	383659713	382786145	0	0
DataIntgOptions_A	1057	1057	0	0
ReqOutKnown_A	383659713	382786145	0	0
SramDwHasByteGranularity_A	1057	1057	0	0
SramDwIsMultipleOfTlulWidth_A	1057	1057	0	0
TlOutKnownIfFifoKnown_A	383659713	382786145	0	0
TlOutValidKnown_A	383659713	382786145	0	0
WdataOutKnown_A	383659713	382786145	0	0
WeOutKnown_A	383659713	382786145	0	0
WmaskOutKnown_A	383659713	382786145	0	0
adapterNoReadOrWrite	1057	1057	0	0
rvalidHighReqFifoEmpty	383659713	3261938	0	0
rvalidHighWhenRspFifoFull	383043132	3255466	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	3261938	0	0
T1	268255	75	0	0
T2	261978	3920	0	0
T3	197796	6144	0	0
T4	6341	116	0	0
T5	0	28416	0	0
T9	393409	0	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	64	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	22656	0	0
T28	0	58	0	0
T29	0	72	0	0
T44	0	33	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	383043132	3255466	0	0
T1	268255	75	0	0
T2	261978	3920	0	0
T3	197796	6144	0	0
T4	6341	116	0	0
T5	0	28416	0	0
T9	393409	0	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	64	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	22656	0	0
T28	0	58	0	0
T29	0	72	0	0
T44	0	33	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		71	71	100.00
CONT_ASSIGN	107	0	0
CONT_ASSIGN	114	0	0
ALWAYS	129	4	4	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	279	8	8	100.00
ALWAYS	299	6	6	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	3	3	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	391	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	423	6	6	100.00
ALWAYS	435	5	5	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
ALWAYS	492	4	4	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	536	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
107		unreachable
114		unreachable
129	1	1
130	1	1
131	1	1
132	1	1
			MISSING_ELSE
138	1	1
144	1	1
151	1	1
156	1	1
176	1	1
188	1	1
272	1	1
273	1	1
274	1	1
279	1	1
281	1	1
282	1	1
284	1	1
285	1	1
286	1	1
289	1	1
292	1	1
299	1	1
301	1	1
302	1	1
303	1	1
305	1	1
308	1	1
313	1	1
317	1	1
336	1	1
341	1	1
347	1	1
359	1	1
362	1	1
363	1	1
365	1	1
369	1	1
390	1	1
391	1	1
392	1	1
393	1	1
423	1	1
424	1	1
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
438	1	1
439	1	1
440	1	1
			MISSING_ELSE
446	1	1
447	1	1
456	1	1
457	1	1
459	1	1
460	1	1
467	1	1
470	1	1
474	1	1
475	1	1
477	1	1
479	1	1
486	1	1
492	1	1
496	1	1
498	1	1
504	1	1
510		unreachable
			MISSING_ELSE
526	1	1
531	1	1
536		unreachable

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	128	103	80.47
Logical	128	103	80.47
Non-Logical	0	0
Event	0	0

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T6,T25,T26

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T6,T25,T26
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Covered	T6,T25,T26

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T18
0	1	Covered	T2,T17,T20
1	0	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T20

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T49
0	1	Covered	T2,T50,T22
1	0	Covered	T2,T17,T20

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T50,T22
1	Covered	T1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T17,T20
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T18,T4
0	0	0	0	0	1	Covered	T6,T25,T26
0	0	0	0	1	0	Covered	T2,T51,T50
0	0	0	1	0	0	Covered	T23,T52,T53
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T54,T55,T56
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T18,T4

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T57,T58
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T18,T4

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12
1	Covered	T1,T18,T4

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T23,T52,T53
1	0	Covered	T59,T60,T61

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T23,T52,T53
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T18,T4

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T60,T61
1	1	Covered	T1,T18,T4

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T52,T53
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T52,T53
1	1	1	Covered	T23,T52,T53

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T18,T4
1	1	Covered	T59,T60,T23

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T23,T55,T56
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T18,T4

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T52,T53
1	0	Covered	T1,T18,T4

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T27
1	1	0	Covered	T23,T52,T53
1	1	1	Covered	T1,T18,T4

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T18,T4
1	1	Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T4

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Not Covered
1	1	Covered	T1,T18,T4

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T52,T53
1	1	Covered	T1,T18,T4

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T4

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
Branches		29	28	96.55
TERNARY	144	2	2	100.00
TERNARY	341	2	2	100.00
TERNARY	347	3	2	66.67
TERNARY	393	2	2	100.00
TERNARY	531	2	2	100.00
IF	129	3	3	100.00
IF	281	4	4	100.00
IF	301	3	3	100.00
IF	362	2	2	100.00
IF	426	2	2	100.00
IF	438	2	2	100.00
IF	496	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T18

	LineNo.	Expression
-1-:	341	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	347	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T18,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	393	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	531	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	if ((!rst_ni))
-2-:	131	if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T25,T26
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if (reqfifo_rvalid)
-2-:	282	if (reqfifo_rdata.error)
-3-:	285	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T23,T52,T53
1	0	1	Covered	T1,T18,T4
1	0	0	Covered	T12
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	301	if (reqfifo_rvalid)
-2-:	302	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T18,T4
1	0	Covered	T12
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	362	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	496	if ((|sramreqfifo_rdata.mask))
-2-:	498	if (DataXorAddr)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T18,T4
1	0	Unreachable
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	383659713	382786145	0	0
DataIntgOptions_A	1057	1057	0	0
ReqOutKnown_A	383659713	382786145	0	0
SramDwHasByteGranularity_A	1057	1057	0	0
SramDwIsMultipleOfTlulWidth_A	1057	1057	0	0
TlOutKnownIfFifoKnown_A	383659713	382786145	0	0
TlOutValidKnown_A	383659713	382786145	0	0
WdataOutKnown_A	383659713	382786145	0	0
WeOutKnown_A	383659713	382786145	0	0
WmaskOutKnown_A	383659713	382786145	0	0
adapterNoReadOrWrite	1057	1057	0	0
rvalidHighReqFifoEmpty	383659713	4063134	0	0
rvalidHighWhenRspFifoFull	383659713	4063134	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	4063134	0	0
T1	268255	204	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	232	0	0
T5	0	16739	0	0
T9	393409	0	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	9	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T22	0	16251	0	0
T27	0	16424	0	0
T28	0	8	0	0
T29	0	3	0	0
T37	0	13	0	0
T50	0	15	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	4063134	0	0
T1	268255	204	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	232	0	0
T5	0	16739	0	0
T9	393409	0	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	9	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T22	0	16251	0	0
T27	0	16424	0	0
T28	0	8	0	0
T29	0	3	0	0
T37	0	13	0	0
T50	0	15	0	0