Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.65 100.00 92.86 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.40 98.24 91.16 93.75 98.85 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 80.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_info_types[0].u_info_mem 95.24 85.71 100.00 100.00
gen_info_types[1].u_info_mem 95.24 85.71 100.00 100.00
gen_info_types[2].u_info_mem 95.24 85.71 100.00 100.00
u_cmd_fifo 97.22 100.00 88.89 100.00 100.00
u_mem 95.24 85.71 100.00 100.00
u_phy_cov_if 93.52 100.00 88.89 91.67



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.65 100.00 92.86 93.75 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.26 98.24 90.48 93.75 98.85 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 80.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_info_types[0].u_info_mem 95.24 85.71 100.00 100.00
gen_info_types[1].u_info_mem 95.24 85.71 100.00 100.00
gen_info_types[2].u_info_mem 95.24 85.71 100.00 100.00
u_cmd_fifo 97.22 100.00 88.89 100.00 100.00
u_mem 95.24 85.71 100.00 100.00
u_phy_cov_if 92.28 100.00 85.19 91.67

Line Coverage for Module : prim_generic_flash_bank
Line No.TotalCoveredPercent
TOTAL142142100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18611100.00
ALWAYS18933100.00
ALWAYS19499100.00
ALWAYS21044100.00
ALWAYS22166100.00
CONT_ASSIGN23111100.00
ALWAYS2361313100.00
ALWAYS2518686100.00
CONT_ASSIGN40211100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
127 1 1
152 1 1
153 1 1
175 1 1
176 1 1
177 1 1
178 1 1
181 1 1
182 1 1
183 1 1
184 1 1
186 1 1
189 2 2
190 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
210 1 1
211 1 1
212 1 1
213 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
MISSING_ELSE
231 1 1
236 1 1
237 1 1
238 1 1
240 2 2
241 2 2
242 2 2
MISSING_ELSE
244 2 2
245 2 2
MISSING_ELSE
251 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
264 1 1
267 1 1
268 1 1
269 1 1
271 1 1
273 1 1
274 1 1
275 1 1
MISSING_ELSE
281 1 1
282 1 1
283 1 1
284 1 1
286 1 1
287 1 1
292 1 1
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
304 1 1
305 1 1
306 1 1
307 1 1
308 1 1
MISSING_ELSE
313 1 1
314 1 1
316 1 1
317 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
326 1 1
327 1 1
330 1 1
332 1 1
333 1 1
334 1 1
MISSING_ELSE
340 1 1
341 1 1
342 1 1
343 1 1
344 1 1
346 1 1
347 1 1
348 1 1
349 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
375 1 1
376 1 1
377 1 1
378 1 1
379 1 1
390 1 1
391 1 1
MISSING_ELSE
402 1 1
426 3 3
446 1 1
447 1 1
450 1 1
453 1 1


Cond Coverage for Module : prim_generic_flash_bank
TotalCoveredPercent
Conditions847892.86
Logical847892.86
Non-Logical00
Event00

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T92
11CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT1,T48,T77
0010CoveredT1,T2,T9
0100CoveredT1,T2,T3
1000CoveredT1,T2,T3

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T9

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T48,T77

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------
-1-StatusTests
0CoveredT5,T22,T169
1CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------
-1-StatusTests
0CoveredT5,T22,T169
1CoveredT1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------
-1--2--3-StatusTests
011Unreachable
101CoveredT91,T86,T92
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T9
01Not Covered
10CoveredT1,T2,T9

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT91,T86,T92

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T18,T4

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT77,T129,T130
10CoveredT1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT2,T3,T9
101CoveredT1,T18,T4
110CoveredT18,T29,T64
111CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT18,T29,T64
01Not Covered
10CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT151,T77,T129
101CoveredT1,T48,T61
110CoveredT1,T2,T3
111CoveredT45,T59,T145

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T48,T77
10CoveredT45,T59,T145

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT45,T59,T145

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT45,T145,T151
101CoveredT1,T18,T59
110CoveredT1,T2,T3
111CoveredT18,T29,T64

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T48,T77
10CoveredT18,T29,T64

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T29,T64

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : prim_generic_flash_bank
Summary for FSM :: st_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 16 15 93.75
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StErSuspend 356 Covered T78,T170,T91
StErase 302 Covered T1,T2,T9
StIdle 286 Covered T1,T2,T3
StInit 275 Covered T1,T2,T3
StProg 334 Covered T1,T2,T3
StRead 296 Covered T1,T2,T3
StReset 391 Covered T1,T2,T3


transitionsLine No.CoveredTests
StErSuspend->StIdle 379 Covered T78,T170,T171
StErSuspend->StReset 391 Covered T91,T86,T92
StErase->StErSuspend 356 Covered T78,T170,T91
StErase->StIdle 364 Covered T1,T2,T9
StErase->StReset 391 Covered T172,T173,T174
StIdle->StErase 302 Covered T1,T2,T9
StIdle->StRead 296 Covered T1,T2,T3
StIdle->StReset 391 Covered T2,T18,T9
StInit->StIdle 286 Covered T1,T2,T3
StInit->StReset 391 Not Covered
StProg->StIdle 346 Covered T1,T2,T3
StProg->StReset 391 Covered T91,T175,T86
StRead->StIdle 327 Covered T1,T2,T3
StRead->StProg 334 Covered T1,T2,T3
StRead->StReset 391 Covered T172,T176,T177
StReset->StInit 275 Covered T1,T2,T3



Branch Coverage for Module : prim_generic_flash_bank
Line No.TotalCoveredPercent
Branches 45 45 100.00
TERNARY 231 2 2 100.00
TERNARY 447 2 2 100.00
IF 189 2 2 100.00
IF 194 2 2 100.00
IF 210 3 3 100.00
IF 221 3 3 100.00
IF 236 8 8 100.00
CASE 271 21 21 100.00
IF 390 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 231 ((ReadLatency == 1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T22,T169


LineNo. Expression -1-: 447 ((rd_part_q == FlashPartData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 189 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 210 if ((!rst_ni)) -2-: 212 if (mem_rd_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 if ((!rst_ni)) -2-: 224 if (mem_rd_d)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 236 if ((!rst_ni)) -2-: 240 if (time_cnt_inc) -3-: 241 if (time_cnt_set1) -4-: 242 if (time_cnt_clr) -5-: 244 if (index_cnt_inc) -6-: 245 if (index_cnt_clr)

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T2,T3
0 0 1 - - - Covered T12
0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 - - Covered T1,T2,T3
0 - - - 1 - Covered T1,T2,T3
0 - - - 0 1 Covered T1,T2,T3
0 - - - 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 271 case (st_q) -2-: 274 if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i))) -3-: 282 if ((index_cnt < InitCycles)) -4-: 292 if (rd_req) -5-: 297 if (prog_req) -6-: 301 if (pg_erase_req) -7-: 305 if (bk_erase_req) -8-: 313 if ((time_cnt < ReadLatency)) -9-: 316 if ((!prog_pend_q)) -10-: 320 if (rd_req) -11-: 330 if (prog_pend_q) -12-: 341 if ((time_cnt < ProgLatency)) -13-: 355 if (erase_suspend_req_i) -14-: 357 if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StReset 1 - - - - - - - - - - - - Covered T1,T2,T3
StReset 0 - - - - - - - - - - - - Covered T1,T2,T3
StInit - 1 - - - - - - - - - - - Covered T1,T2,T3
StInit - 0 - - - - - - - - - - - Covered T1,T2,T3
StIdle - - 1 - - - - - - - - - - Covered T1,T2,T3
StIdle - - 0 1 - - - - - - - - - Covered T1,T2,T3
StIdle - - 0 0 1 - - - - - - - - Covered T1,T2,T9
StIdle - - 0 0 0 1 - - - - - - - Covered T1,T48,T77
StIdle - - 0 0 0 0 - - - - - - - Covered T1,T2,T3
StRead - - - - - - 1 - - - - - - Covered T1,T2,T3
StRead - - - - - - 0 1 1 - - - - Covered T12
StRead - - - - - - 0 1 0 - - - - Covered T1,T2,T3
StRead - - - - - - 0 0 - 1 - - - Covered T1,T2,T3
StRead - - - - - - 0 0 - 0 - - - Covered T12
StProg - - - - - - - - - - 1 - - Covered T1,T2,T3
StProg - - - - - - - - - - 0 - - Covered T1,T2,T3
StErase - - - - - - - - - - - 1 - Covered T78,T170,T91
StErase - - - - - - - - - - - 0 1 Covered T1,T2,T9
StErase - - - - - - - - - - - 0 0 Covered T1,T2,T9
StErSuspend - - - - - - - - - - - - - Covered T78,T170,T91
default - - - - - - - - - - - - - Covered T12


LineNo. Expression -1-: 390 if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank
Line No.TotalCoveredPercent
TOTAL142142100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18611100.00
ALWAYS18933100.00
ALWAYS19499100.00
ALWAYS21044100.00
ALWAYS22166100.00
CONT_ASSIGN23111100.00
ALWAYS2361313100.00
ALWAYS2518686100.00
CONT_ASSIGN40211100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
127 1 1
152 1 1
153 1 1
175 1 1
176 1 1
177 1 1
178 1 1
181 1 1
182 1 1
183 1 1
184 1 1
186 1 1
189 2 2
190 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
210 1 1
211 1 1
212 1 1
213 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
MISSING_ELSE
231 1 1
236 1 1
237 1 1
238 1 1
240 2 2
241 2 2
242 2 2
MISSING_ELSE
244 2 2
245 2 2
MISSING_ELSE
251 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
264 1 1
267 1 1
268 1 1
269 1 1
271 1 1
273 1 1
274 1 1
275 1 1
MISSING_ELSE
281 1 1
282 1 1
283 1 1
284 1 1
286 1 1
287 1 1
292 1 1
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
304 1 1
305 1 1
306 1 1
307 1 1
308 1 1
MISSING_ELSE
313 1 1
314 1 1
316 1 1
317 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
326 1 1
327 1 1
330 1 1
332 1 1
333 1 1
334 1 1
MISSING_ELSE
340 1 1
341 1 1
342 1 1
343 1 1
344 1 1
346 1 1
347 1 1
348 1 1
349 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
375 1 1
376 1 1
377 1 1
378 1 1
379 1 1
390 1 1
391 1 1
MISSING_ELSE
402 1 1
426 3 3
446 1 1
447 1 1
450 1 1
453 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank
TotalCoveredPercent
Conditions847892.86
Logical847892.86
Non-Logical00
Event00

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T92
11CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT1,T77,T78
0010CoveredT2,T9,T50
0100CoveredT1,T2,T3
1000CoveredT1,T2,T3

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T9,T50

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T77,T78

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------
-1-StatusTests
0CoveredT5,T22,T169
1CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------
-1-StatusTests
0CoveredT5,T22,T169
1CoveredT1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------
-1--2--3-StatusTests
011Unreachable
101CoveredT91,T86,T92
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T9
01Not Covered
10CoveredT1,T2,T9

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT91,T86,T92

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T18,T4

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT77,T129,T130
10CoveredT1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT2,T3,T9
101CoveredT1,T18,T4
110CoveredT18,T29,T64
111CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT18,T29,T64
01Not Covered
10CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT77,T129,T130
101CoveredT1,T61,T78
110CoveredT1,T2,T3
111CoveredT59,T145,T146

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T77,T78
10CoveredT59,T145,T146

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT59,T145,T146

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT128,T77,T139
101CoveredT1,T18,T59
110CoveredT1,T2,T3
111CoveredT18,T29,T64

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T77,T78
10CoveredT18,T29,T64

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T29,T64

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank
Summary for FSM :: st_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 16 15 93.75
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StErSuspend 356 Covered T78,T170,T91
StErase 302 Covered T1,T2,T9
StIdle 286 Covered T1,T2,T3
StInit 275 Covered T1,T2,T3
StProg 334 Covered T1,T2,T3
StRead 296 Covered T1,T2,T3
StReset 391 Covered T1,T2,T3


transitionsLine No.CoveredTests
StErSuspend->StIdle 379 Covered T78,T170,T171
StErSuspend->StReset 391 Covered T91,T92
StErase->StErSuspend 356 Covered T78,T170,T91
StErase->StIdle 364 Covered T1,T2,T9
StErase->StReset 391 Covered T172,T173,T174
StIdle->StErase 302 Covered T1,T2,T9
StIdle->StRead 296 Covered T1,T2,T3
StIdle->StReset 391 Covered T2,T18,T9
StInit->StIdle 286 Covered T1,T2,T3
StInit->StReset 391 Not Covered
StProg->StIdle 346 Covered T1,T2,T3
StProg->StReset 391 Covered T91,T86,T92
StRead->StIdle 327 Covered T1,T2,T3
StRead->StProg 334 Covered T1,T2,T3
StRead->StReset 391 Covered T172,T178,T179
StReset->StInit 275 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank
Line No.TotalCoveredPercent
Branches 45 45 100.00
TERNARY 231 2 2 100.00
TERNARY 447 2 2 100.00
IF 189 2 2 100.00
IF 194 2 2 100.00
IF 210 3 3 100.00
IF 221 3 3 100.00
IF 236 8 8 100.00
CASE 271 21 21 100.00
IF 390 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 231 ((ReadLatency == 1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T22,T169


LineNo. Expression -1-: 447 ((rd_part_q == FlashPartData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 189 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 210 if ((!rst_ni)) -2-: 212 if (mem_rd_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 if ((!rst_ni)) -2-: 224 if (mem_rd_d)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 236 if ((!rst_ni)) -2-: 240 if (time_cnt_inc) -3-: 241 if (time_cnt_set1) -4-: 242 if (time_cnt_clr) -5-: 244 if (index_cnt_inc) -6-: 245 if (index_cnt_clr)

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T2,T3
0 0 1 - - - Covered T12
0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 - - Covered T1,T2,T3
0 - - - 1 - Covered T1,T2,T3
0 - - - 0 1 Covered T1,T2,T3
0 - - - 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 271 case (st_q) -2-: 274 if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i))) -3-: 282 if ((index_cnt < InitCycles)) -4-: 292 if (rd_req) -5-: 297 if (prog_req) -6-: 301 if (pg_erase_req) -7-: 305 if (bk_erase_req) -8-: 313 if ((time_cnt < ReadLatency)) -9-: 316 if ((!prog_pend_q)) -10-: 320 if (rd_req) -11-: 330 if (prog_pend_q) -12-: 341 if ((time_cnt < ProgLatency)) -13-: 355 if (erase_suspend_req_i) -14-: 357 if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StReset 1 - - - - - - - - - - - - Covered T1,T2,T3
StReset 0 - - - - - - - - - - - - Covered T1,T2,T3
StInit - 1 - - - - - - - - - - - Covered T1,T2,T3
StInit - 0 - - - - - - - - - - - Covered T1,T2,T3
StIdle - - 1 - - - - - - - - - - Covered T1,T2,T3
StIdle - - 0 1 - - - - - - - - - Covered T1,T2,T3
StIdle - - 0 0 1 - - - - - - - - Covered T2,T9,T50
StIdle - - 0 0 0 1 - - - - - - - Covered T1,T77,T78
StIdle - - 0 0 0 0 - - - - - - - Covered T1,T2,T3
StRead - - - - - - 1 - - - - - - Covered T1,T2,T3
StRead - - - - - - 0 1 1 - - - - Covered T12
StRead - - - - - - 0 1 0 - - - - Covered T1,T2,T3
StRead - - - - - - 0 0 - 1 - - - Covered T1,T2,T3
StRead - - - - - - 0 0 - 0 - - - Covered T12
StProg - - - - - - - - - - 1 - - Covered T1,T2,T3
StProg - - - - - - - - - - 0 - - Covered T1,T2,T3
StErase - - - - - - - - - - - 1 - Covered T78,T170,T91
StErase - - - - - - - - - - - 0 1 Covered T1,T2,T9
StErase - - - - - - - - - - - 0 0 Covered T1,T2,T9
StErSuspend - - - - - - - - - - - - - Covered T78,T170,T91
default - - - - - - - - - - - - - Covered T12


LineNo. Expression -1-: 390 if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank
Line No.TotalCoveredPercent
TOTAL142142100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18611100.00
ALWAYS18933100.00
ALWAYS19499100.00
ALWAYS21044100.00
ALWAYS22166100.00
CONT_ASSIGN23111100.00
ALWAYS2361313100.00
ALWAYS2518686100.00
CONT_ASSIGN40211100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN42611100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
127 1 1
152 1 1
153 1 1
175 1 1
176 1 1
177 1 1
178 1 1
181 1 1
182 1 1
183 1 1
184 1 1
186 1 1
189 2 2
190 1 1
194 1 1
195 1 1
196 1 1
197 1 1
198 1 1
200 1 1
201 1 1
202 1 1
203 1 1
210 1 1
211 1 1
212 1 1
213 1 1
MISSING_ELSE
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
MISSING_ELSE
231 1 1
236 1 1
237 1 1
238 1 1
240 2 2
241 2 2
242 2 2
MISSING_ELSE
244 2 2
245 2 2
MISSING_ELSE
251 1 1
254 1 1
255 1 1
256 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
262 1 1
263 1 1
264 1 1
267 1 1
268 1 1
269 1 1
271 1 1
273 1 1
274 1 1
275 1 1
MISSING_ELSE
281 1 1
282 1 1
283 1 1
284 1 1
286 1 1
287 1 1
292 1 1
293 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1
299 1 1
300 1 1
301 1 1
302 1 1
303 1 1
304 1 1
305 1 1
306 1 1
307 1 1
308 1 1
MISSING_ELSE
313 1 1
314 1 1
316 1 1
317 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
326 1 1
327 1 1
330 1 1
332 1 1
333 1 1
334 1 1
MISSING_ELSE
340 1 1
341 1 1
342 1 1
343 1 1
344 1 1
346 1 1
347 1 1
348 1 1
349 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
375 1 1
376 1 1
377 1 1
378 1 1
379 1 1
390 1 1
391 1 1
MISSING_ELSE
402 1 1
426 3 3
446 1 1
447 1 1
450 1 1
453 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank
TotalCoveredPercent
Conditions847892.86
Logical847892.86
Non-Logical00
Event00

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86
11CoveredT1,T18,T4

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT48,T78,T79
0010CoveredT1,T9,T50
0100CoveredT1,T4,T9
1000CoveredT1,T18,T4

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------
-1--2-StatusTests
01CoveredT1,T4,T44
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T9
11CoveredT1,T18,T4

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T18,T4
11CoveredT1,T4,T9

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T18,T4
11CoveredT1,T9,T50

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T18,T4
11CoveredT48,T78,T79

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T9
11CoveredT1,T18,T4

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------
-1-StatusTests
0CoveredT5,T22,T169
1CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------
-1-StatusTests
0CoveredT5,T22,T169
1CoveredT1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------
-1--2--3-StatusTests
011Unreachable
101CoveredT91,T86,T92
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------
-1--2-StatusTests
00CoveredT1,T9,T50
01Not Covered
10CoveredT1,T9,T50

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT91,T86,T92

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT43,T37,T45
11CoveredT1,T18,T4

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----
-1--2-StatusTests
00CoveredT43,T37,T45
01CoveredT129,T133,T153
10CoveredT1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT43,T37,T145
101CoveredT1,T18,T4
110CoveredT45,T145,T151
111CoveredT43,T37,T45

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T37,T45

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT45,T59,T145
01Not Covered
10CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT151,T129,T133
101CoveredT48,T61,T78
110CoveredT43,T37,T45
111CoveredT45,T145,T151

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T37,T45

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T78,T79
10CoveredT45,T145,T151

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT45,T145,T151

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT45,T145,T151
101CoveredT59,T151,T48
110CoveredT43,T37,T45
111CoveredT45,T145,T151

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T37,T45

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T78,T79
10CoveredT45,T59,T145

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT45,T59,T145

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------
-1-StatusTests
0CoveredT43,T37,T45
1CoveredT1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank
Summary for FSM :: st_q
TotalCoveredPercent
States 7 7 100.00 (Not included in score)
Transitions 16 15 93.75
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StErSuspend 356 Covered T78,T170,T171
StErase 302 Covered T1,T9,T50
StIdle 286 Covered T1,T2,T3
StInit 275 Covered T1,T2,T3
StProg 334 Covered T1,T4,T44
StRead 296 Covered T1,T18,T4
StReset 391 Covered T1,T2,T3


transitionsLine No.CoveredTests
StErSuspend->StIdle 379 Covered T78,T170,T171
StErSuspend->StReset 391 Covered T86,T180
StErase->StErSuspend 356 Covered T78,T170,T171
StErase->StIdle 364 Covered T1,T9,T50
StErase->StReset 391 Covered T181,T91,T86
StIdle->StErase 302 Covered T1,T9,T50
StIdle->StRead 296 Covered T1,T18,T4
StIdle->StReset 391 Covered T2,T18,T9
StInit->StIdle 286 Covered T1,T2,T3
StInit->StReset 391 Not Covered
StProg->StIdle 346 Covered T1,T4,T44
StProg->StReset 391 Covered T91,T175,T86
StRead->StIdle 327 Covered T1,T18,T4
StRead->StProg 334 Covered T1,T4,T44
StRead->StReset 391 Covered T176,T177,T182
StReset->StInit 275 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank
Line No.TotalCoveredPercent
Branches 45 45 100.00
TERNARY 231 2 2 100.00
TERNARY 447 2 2 100.00
IF 189 2 2 100.00
IF 194 2 2 100.00
IF 210 3 3 100.00
IF 221 3 3 100.00
IF 236 8 8 100.00
CASE 271 21 21 100.00
IF 390 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 231 ((ReadLatency == 1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T22,T169


LineNo. Expression -1-: 447 ((rd_part_q == FlashPartData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T43,T37,T45


LineNo. Expression -1-: 189 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 210 if ((!rst_ni)) -2-: 212 if (mem_rd_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T18,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 if ((!rst_ni)) -2-: 224 if (mem_rd_d)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T18,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 236 if ((!rst_ni)) -2-: 240 if (time_cnt_inc) -3-: 241 if (time_cnt_set1) -4-: 242 if (time_cnt_clr) -5-: 244 if (index_cnt_inc) -6-: 245 if (index_cnt_clr)

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T1,T18,T4
0 0 1 - - - Covered T12
0 0 0 1 - - Covered T1,T18,T4
0 0 0 0 - - Covered T1,T2,T3
0 - - - 1 - Covered T1,T2,T3
0 - - - 0 1 Covered T1,T2,T3
0 - - - 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 271 case (st_q) -2-: 274 if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i))) -3-: 282 if ((index_cnt < InitCycles)) -4-: 292 if (rd_req) -5-: 297 if (prog_req) -6-: 301 if (pg_erase_req) -7-: 305 if (bk_erase_req) -8-: 313 if ((time_cnt < ReadLatency)) -9-: 316 if ((!prog_pend_q)) -10-: 320 if (rd_req) -11-: 330 if (prog_pend_q) -12-: 341 if ((time_cnt < ProgLatency)) -13-: 355 if (erase_suspend_req_i) -14-: 357 if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StReset 1 - - - - - - - - - - - - Covered T1,T2,T3
StReset 0 - - - - - - - - - - - - Covered T1,T2,T3
StInit - 1 - - - - - - - - - - - Covered T1,T2,T3
StInit - 0 - - - - - - - - - - - Covered T1,T2,T3
StIdle - - 1 - - - - - - - - - - Covered T1,T18,T4
StIdle - - 0 1 - - - - - - - - - Covered T1,T4,T9
StIdle - - 0 0 1 - - - - - - - - Covered T1,T9,T50
StIdle - - 0 0 0 1 - - - - - - - Covered T48,T78,T79
StIdle - - 0 0 0 0 - - - - - - - Covered T1,T2,T3
StRead - - - - - - 1 - - - - - - Covered T1,T4,T9
StRead - - - - - - 0 1 1 - - - - Covered T12
StRead - - - - - - 0 1 0 - - - - Covered T1,T18,T4
StRead - - - - - - 0 0 - 1 - - - Covered T1,T4,T9
StRead - - - - - - 0 0 - 0 - - - Covered T12
StProg - - - - - - - - - - 1 - - Covered T1,T4,T9
StProg - - - - - - - - - - 0 - - Covered T1,T4,T9
StErase - - - - - - - - - - - 1 - Covered T78,T170,T171
StErase - - - - - - - - - - - 0 1 Covered T1,T9,T50
StErase - - - - - - - - - - - 0 0 Covered T1,T9,T50
StErSuspend - - - - - - - - - - - - - Covered T78,T170,T171
default - - - - - - - - - - - - - Covered T12


LineNo. Expression -1-: 390 if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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