Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1534638852	1531144580	0	0
CheckNGreaterZero_A	4228	4228	0	0
GntImpliesReady_A	1534638852	412878032	0	0
GntImpliesValid_A	1534638852	412878032	0	0
GrantKnown_A	1534638852	1531144580	0	0
IdxKnown_A	1534638852	1531144580	0	0
IndexIsCorrect_A	1534638852	412878032	0	0
NoReadyValidNoGrant_A	1534638852	175178959	0	0
Priority_A	1534638852	437100697	0	0
ReadyAndValidImplyGrant_A	1534638852	412878032	0	0
ReqAndReadyImplyGrant_A	1534638852	412878032	0	0
ReqImpliesValid_A	1534638852	437100697	0	0
ValidKnown_A	1534638852	1531144580	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	1531144580	0	0
T1	1073020	1072800	0	0
T2	1047912	999100	0	0
T3	791184	790872	0	0
T4	25364	25040	0	0
T9	1573636	1573580	0	0
T16	14276	14056	0	0
T17	4436	4228	0	0
T18	10848	10108	0	0
T19	5756	5480	0	0
T20	6448	6240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4228	4228	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T9	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	412878032	0	0
T1	1073020	527424	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7674	0	0
T5	0	42106	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	41666	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	412878032	0	0
T1	1073020	527424	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7674	0	0
T5	0	42106	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	41666	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	1531144580	0	0
T1	1073020	1072800	0	0
T2	1047912	999100	0	0
T3	791184	790872	0	0
T4	25364	25040	0	0
T9	1573636	1573580	0	0
T16	14276	14056	0	0
T17	4436	4228	0	0
T18	10848	10108	0	0
T19	5756	5480	0	0
T20	6448	6240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	1531144580	0	0
T1	1073020	1072800	0	0
T2	1047912	999100	0	0
T3	791184	790872	0	0
T4	25364	25040	0	0
T9	1573636	1573580	0	0
T16	14276	14056	0	0
T17	4436	4228	0	0
T18	10848	10108	0	0
T19	5756	5480	0	0
T20	6448	6240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	412878032	0	0
T1	1073020	527424	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7674	0	0
T5	0	42106	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	41666	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	175178959	0	0
T1	1073020	2122	0	0
T2	1047912	60704	0	0
T3	791184	4736	0	0
T4	25364	872	0	0
T5	0	1282138	0	0
T9	1573636	2109952	0	0
T16	14276	256	0	0
T17	4436	256	0	0
T18	10848	842	0	0
T19	5756	256	0	0
T20	6448	256	0	0
T27	0	112196	0	0
T28	0	96	0	0
T29	0	56	0	0
T44	0	66	0	0
T64	0	14	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	437100697	0	0
T1	1073020	528006	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7690	0	0
T5	0	272644	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	43048	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	412878032	0	0
T1	1073020	527424	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7674	0	0
T5	0	42106	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	41666	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	412878032	0	0
T1	1073020	527424	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7674	0	0
T5	0	42106	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	41666	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	437100697	0	0
T1	1073020	528006	0	0
T2	1047912	218932	0	0
T3	791184	30622	0	0
T4	25364	7690	0	0
T5	0	272644	0	0
T9	1573636	514650	0	0
T16	14276	64	0	0
T17	4436	64	0	0
T18	10848	380	0	0
T19	5756	64	0	0
T20	6448	64	0	0
T27	0	43048	0	0
T28	0	34	0	0
T29	0	20	0	0
T44	0	488	0	0
T67	0	297528	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1534638852	1531144580	0	0
T1	1073020	1072800	0	0
T2	1047912	999100	0	0
T3	791184	790872	0	0
T4	25364	25040	0	0
T9	1573636	1573580	0	0
T16	14276	14056	0	0
T17	4436	4228	0	0
T18	10848	10108	0	0
T19	5756	5480	0	0
T20	6448	6240	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383659713	382786145	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	383659713	105534551	0	0
GntImpliesValid_A	383659713	105534551	0	0
GrantKnown_A	383659713	382786145	0	0
IdxKnown_A	383659713	382786145	0	0
IndexIsCorrect_A	383659713	105534551	0	0
NoReadyValidNoGrant_A	383659713	45371117	0	0
Priority_A	383659713	111624061	0	0
ReadyAndValidImplyGrant_A	383659713	105534551	0	0
ReqAndReadyImplyGrant_A	383659713	105534551	0	0
ReqImpliesValid_A	383659713	111624061	0	0
ValidKnown_A	383659713	382786145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534551	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534551	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534551	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	45371117	0	0
T1	268255	744	0	0
T2	261978	30352	0	0
T3	197796	2368	0	0
T4	6341	261	0	0
T9	393409	530688	0	0
T16	3569	128	0	0
T17	1109	128	0	0
T18	2712	395	0	0
T19	1439	128	0	0
T20	1612	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	111624061	0	0
T1	268255	263401	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1666	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534551	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534551	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	111624061	0	0
T1	268255	263401	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1666	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383659713	382786145	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	383659713	105534702	0	0
GntImpliesValid_A	383659713	105534702	0	0
GrantKnown_A	383659713	382786145	0	0
IdxKnown_A	383659713	382786145	0	0
IndexIsCorrect_A	383659713	105534702	0	0
NoReadyValidNoGrant_A	383659713	45371106	0	0
Priority_A	383659713	111624223	0	0
ReadyAndValidImplyGrant_A	383659713	105534702	0	0
ReqAndReadyImplyGrant_A	383659713	105534702	0	0
ReqImpliesValid_A	383659713	111624223	0	0
ValidKnown_A	383659713	382786145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534702	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534702	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534702	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	45371106	0	0
T1	268255	744	0	0
T2	261978	30352	0	0
T3	197796	2368	0	0
T4	6341	261	0	0
T9	393409	530688	0	0
T16	3569	128	0	0
T17	1109	128	0	0
T18	2712	395	0	0
T19	1439	128	0	0
T20	1612	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	111624223	0	0
T1	268255	263401	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1666	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534702	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	105534702	0	0
T1	268255	263152	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1662	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	111624223	0	0
T1	268255	263401	0	0
T2	261978	109466	0	0
T3	197796	15311	0	0
T4	6341	1666	0	0
T9	393409	129428	0	0
T16	3569	32	0	0
T17	1109	32	0	0
T18	2712	182	0	0
T19	1439	32	0	0
T20	1612	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T18,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383659713	382786145	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	383659713	100904433	0	0
GntImpliesValid_A	383659713	100904433	0	0
GrantKnown_A	383659713	382786145	0	0
IdxKnown_A	383659713	382786145	0	0
IndexIsCorrect_A	383659713	100904433	0	0
NoReadyValidNoGrant_A	383659713	42218367	0	0
Priority_A	383659713	106926251	0	0
ReadyAndValidImplyGrant_A	383659713	100904433	0	0
ReqAndReadyImplyGrant_A	383659713	100904433	0	0
ReqImpliesValid_A	383659713	106926251	0	0
ValidKnown_A	383659713	382786145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904433	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904433	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904433	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	42218367	0	0
T1	268255	317	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	175	0	0
T5	0	641069	0	0
T9	393409	524288	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	26	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	56098	0	0
T28	0	48	0	0
T29	0	28	0	0
T44	0	33	0	0
T64	0	7	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	106926251	0	0
T1	268255	602	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2179	0	0
T5	0	136322	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	21524	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904433	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904433	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	106926251	0	0
T1	268255	602	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2179	0	0
T5	0	136322	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	21524	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T18,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T18,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T18,T4
1	1	Covered	T1,T18,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T18,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383659713	382786145	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	383659713	100904346	0	0
GntImpliesValid_A	383659713	100904346	0	0
GrantKnown_A	383659713	382786145	0	0
IdxKnown_A	383659713	382786145	0	0
IndexIsCorrect_A	383659713	100904346	0	0
NoReadyValidNoGrant_A	383659713	42218369	0	0
Priority_A	383659713	106926162	0	0
ReadyAndValidImplyGrant_A	383659713	100904346	0	0
ReqAndReadyImplyGrant_A	383659713	100904346	0	0
ReqImpliesValid_A	383659713	106926162	0	0
ValidKnown_A	383659713	382786145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904346	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904346	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904346	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	42218369	0	0
T1	268255	317	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	175	0	0
T5	0	641069	0	0
T9	393409	524288	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	26	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	56098	0	0
T28	0	48	0	0
T29	0	28	0	0
T44	0	33	0	0
T64	0	7	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	106926162	0	0
T1	268255	602	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2179	0	0
T5	0	136322	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	21524	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904346	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	100904346	0	0
T1	268255	560	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2175	0	0
T5	0	21053	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	20833	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	106926162	0	0
T1	268255	602	0	0
T2	261978	0	0	0
T3	197796	0	0	0
T4	6341	2179	0	0
T5	0	136322	0	0
T9	393409	127897	0	0
T16	3569	0	0	0
T17	1109	0	0	0
T18	2712	8	0	0
T19	1439	0	0	0
T20	1612	0	0	0
T27	0	21524	0	0
T28	0	17	0	0
T29	0	10	0	0
T44	0	244	0	0
T67	0	148764	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383659713	382786145	0	0
T1	268255	268200	0	0
T2	261978	249775	0	0
T3	197796	197718	0	0
T4	6341	6260	0	0
T9	393409	393395	0	0
T16	3569	3514	0	0
T17	1109	1057	0	0
T18	2712	2527	0	0
T19	1439	1370	0	0
T20	1612	1560	0	0