Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21685499	1		T1	187433		T2	96		T3	57
full_word	7643846	1		T1	29190		T2	51		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29329095	1		T1	216623		T2	147		T3	58
auto[TlIntgErrCmd]	92	1		T72	2		T73	6		T126	3
auto[TlIntgErrData]	78	1		T72	3		T73	7		T126	2
auto[TlIntgErrBoth]	80	1		T72	5		T73	7		T126	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24973536	1		T1	195362		T2	94		T3	57
auto[1]	4355809	1		T1	21261		T2	53		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21035971	1		T1	184843		T2	91		T3	56
auto[TlIntgErrNone]	partial	auto[1]	649300	1		T1	2590		T2	5		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	3937448	1		T1	10519		T2	3		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3706376	1		T1	18671		T2	48		T4	962
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T72	1		T73	3		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T72	1		T73	3		T126	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T276	1		T375	1		T275	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T374	1		T376	1		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1		T72	1		T73	4		T213	3
auto[TlIntgErrData]	partial	auto[1]	33	1		T72	1		T73	3		T126	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T377	1		T378	3		T376	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T72	1		T126	1		T213	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T72	1		T73	2		T126	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T72	4		T73	4		T126	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T73	1		T379	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T234	1		T375	2		T380	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18270	1		T72	10		T73	18		T126	10
full_word	3760391	1		T1	41002		T4	258		T8	160

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3778425	1		T1	41002		T4	258		T8	160
auto[TlIntgErrCmd]	66	1		T72	2		T73	4		T126	3
auto[TlIntgErrData]	84	1		T72	6		T73	6		T126	4
auto[TlIntgErrBoth]	86	1		T72	2		T73	8		T126	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3755001	1		T1	41002		T4	258		T8	160
auto[1]	23660	1		T72	5		T73	14		T126	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1111	1		T210	6		T212	79		T235	84
auto[TlIntgErrNone]	partial	auto[1]	16933	1		T210	81		T211	31		T212	1492
auto[TlIntgErrNone]	full_word	auto[0]	3753806	1		T1	41002		T4	258		T8	160
auto[TlIntgErrNone]	full_word	auto[1]	6575	1		T210	41		T211	16		T212	473
auto[TlIntgErrCmd]	partial	auto[0]	22	1		T72	2		T214	1		T233	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T73	4		T126	3		T213	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T274	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T374	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	32	1		T72	3		T73	2		T126	3
auto[TlIntgErrData]	partial	auto[1]	47	1		T72	3		T73	4		T126	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T233	1		T378	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T380	1		T376	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T73	2		T213	2		T214	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T72	2		T73	6		T126	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T373	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T380	1		-	-		-	-