Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.76 96.63 85.85 100.00 91.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.73 96.73 92.84 96.90 100.00 96.82 97.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 97.56 100.00 93.85 95.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.02 97.64 93.24 100.00 99.37 94.83
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.40 98.88 95.28 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.62 96.96 93.81 100.00 100.00 97.88 97.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.39 100.00 93.85 100.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.08 97.64 93.56 100.00 99.37 94.83
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS2296583.33
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 0 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions10610296.23
Logical10610296.23
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11CoveredT85,T86,T220

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT85,T86,T220

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T4,T8
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T8
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T8
110Not Covered
111CoveredT1,T4,T8

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T8
101CoveredT1,T4,T8
110CoveredT66,T67
111CoveredT1,T4,T8

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT103
10CoveredT1,T4,T8
11CoveredT1,T4,T8

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11CoveredT1,T4,T8

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT104,T105
10CoveredT1,T2,T3
11CoveredT1,T4,T8

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T4,T8

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT4,T5,T8
11CoveredT1,T2,T4

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT66,T67
10CoveredT60,T221

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT60,T221

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11CoveredT66,T67

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT4,T5,T8
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T24,T28
10CoveredT4,T5,T8

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT204

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT204
11CoveredT204

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T8
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT204

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT14,T15,T16

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T17

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T17

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 341 Covered T4,T5,T8
StCtrlProg 339 Covered T1,T2,T4
StCtrlRead 337 Covered T1,T2,T3
StDisable 335 Covered T2,T12,T13
StIdle 349 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 369 Covered T4,T5,T8
StCtrlProg->StIdle 359 Covered T1,T2,T4
StCtrlRead->StIdle 349 Covered T1,T2,T3
StIdle->StCtrl 341 Covered T4,T5,T8
StIdle->StCtrlProg 339 Covered T1,T2,T4
StIdle->StCtrlRead 337 Covered T1,T2,T3
StIdle->StDisable 335 Covered T2,T12,T13



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 2 100.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 3 75.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T204
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T85,T86,T220
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T204
0 0 0 Covered T1,T4,T8


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T2,T12,T13
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T4
StIdle 0 0 0 1 - - - Covered T4,T5,T8
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T4
StCtrlProg - - - - - 0 - Covered T1,T2,T4
StCtrl - - - - - - 1 Covered T4,T5,T8
StCtrl - - - - - - 0 Covered T4,T5,T8
StDisable - - - - - - - Covered T2,T12,T13
default - - - - - - - Covered T14,T15,T16


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 760338386 2933130 0 0
CtrlPrio_A 760338386 2933130 0 0
HostTransIdleChk_A 760338386 43954243 0 0
NoRemainder_A 2114 2114 0 0
OneHotReqs_A 760338386 758647960 0 0
Pow2Multiple_A 2114 2114 0 0
RdTxnCheck_A 759624966 757934540 0 0
u_state_regs_A 760338386 758647960 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 760338386 2933130 0 0
T1 888592 14594 0 0
T2 2116 0 0 0
T3 2702 0 0 0
T4 278216 84 0 0
T5 84800 0 0 0
T6 0 6823 0 0
T7 0 7940 0 0
T17 453276 0 0 0
T18 2234 0 0 0
T19 548106 0 0 0
T20 2976 0 0 0
T21 134356 0 0 0
T24 0 84 0 0
T25 0 3906 0 0
T28 0 84 0 0
T31 0 4907 0 0
T45 0 40479 0 0
T58 0 6072 0 0
T77 0 36874 0 0
T152 0 636 0 0
T192 0 2966 0 0
T200 0 648 0 0
T222 0 2363 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 760338386 2933130 0 0
T1 888592 14594 0 0
T2 2116 0 0 0
T3 2702 0 0 0
T4 278216 84 0 0
T5 84800 0 0 0
T6 0 6823 0 0
T7 0 7940 0 0
T17 453276 0 0 0
T18 2234 0 0 0
T19 548106 0 0 0
T20 2976 0 0 0
T21 134356 0 0 0
T24 0 84 0 0
T25 0 3906 0 0
T28 0 84 0 0
T31 0 4907 0 0
T45 0 40479 0 0
T58 0 6072 0 0
T77 0 36874 0 0
T152 0 636 0 0
T192 0 2966 0 0
T200 0 648 0 0
T222 0 2363 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 760338386 43954243 0 0
T1 888592 137890 0 0
T2 2116 0 0 0
T3 2702 0 0 0
T4 278216 816 0 0
T5 84800 0 0 0
T6 0 91078 0 0
T7 0 78323 0 0
T8 0 248 0 0
T17 453276 0 0 0
T18 2234 0 0 0
T19 548106 0 0 0
T20 2976 0 0 0
T21 134356 0 0 0
T24 0 670 0 0
T31 0 57798 0 0
T34 0 45 0 0
T58 0 55852 0 0
T60 0 20 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2114 2114 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 760338386 758647960 0 0
T1 888592 888420 0 0
T2 2116 1956 0 0
T3 2702 2572 0 0
T4 278216 278028 0 0
T5 84800 79778 0 0
T17 453276 453162 0 0
T18 2234 1848 0 0
T19 548106 547948 0 0
T20 2976 2542 0 0
T21 134356 134180 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2114 2114 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 759624966 757934540 0 0
T1 888592 888420 0 0
T2 2116 1956 0 0
T3 2702 2572 0 0
T4 278216 278028 0 0
T5 84800 79778 0 0
T17 453276 453162 0 0
T18 2234 1848 0 0
T19 548106 547948 0 0
T20 2976 2542 0 0
T21 134356 134180 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 760338386 758647960 0 0
T1 888592 888420 0 0
T2 2116 1956 0 0
T3 2702 2572 0 0
T4 278216 278028 0 0
T5 84800 79778 0 0
T17 453276 453162 0 0
T18 2234 1848 0 0
T19 548106 547948 0 0
T20 2976 2542 0 0
T21 134356 134180 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL898696.63
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS2034375.00
ALWAYS2156583.33
ALWAYS2296583.33
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 0 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 0 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 0 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1069185.85
Logical1069185.85
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T4,T17
10CoveredT1,T4,T8
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T4,T8
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T4,T17
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T8
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T8
110Not Covered
111CoveredT1,T4,T8

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T8
101CoveredT1,T4,T8
110Not Covered
111CoveredT1,T4,T8

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT103
10CoveredT1,T4,T8
11CoveredT1,T4,T8

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T4,T21
10CoveredT1,T4,T8
11CoveredT1,T4,T8

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT105
10CoveredT1,T4,T17
11CoveredT1,T4,T8

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T4,T17
11CoveredT1,T4,T8

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T17
11CoveredT1,T4,T21

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT4,T8,T22
11CoveredT1,T4,T17

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T4,T17
10CoveredT1,T2,T3
11Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T17
11CoveredT1,T4,T21

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T4,T21
11CoveredT1,T4,T17

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT4,T5,T8
10CoveredT1,T4,T17
11CoveredT4,T8,T22

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T24,T28
10CoveredT4,T5,T8

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T4,T8
10Not Covered
11Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T17
11CoveredT1,T4,T21

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T8
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT14,T15,T16

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T21,T60
10CoveredT1,T19,T21

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T21,T6
10CoveredT1,T19,T21

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T19,T21

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T19,T21

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 341 Covered T4,T8,T22
StCtrlProg 339 Covered T1,T4,T17
StCtrlRead 337 Covered T1,T4,T21
StDisable 335 Covered T2,T12,T13
StIdle 349 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 369 Covered T4,T8,T22
StCtrlProg->StIdle 359 Covered T1,T4,T17
StCtrlRead->StIdle 349 Covered T1,T4,T21
StIdle->StCtrl 341 Covered T4,T8,T22
StIdle->StCtrlProg 339 Covered T1,T4,T17
StIdle->StCtrlRead 337 Covered T1,T4,T21
StIdle->StDisable 335 Covered T2,T12,T13



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 42 91.30
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 1 50.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 2 66.67
IF 215 4 3 75.00
IF 229 4 3 75.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T19,T21
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T19,T21
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T17
0 0 1 Covered T1,T4,T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T4,T8


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T4,T17


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T2,T12,T13
StIdle 0 1 - - - - - Covered T1,T4,T21
StIdle 0 0 1 - - - - Covered T1,T4,T17
StIdle 0 0 0 1 - - - Covered T4,T8,T22
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T4,T21
StCtrlRead - - - - 0 - - Covered T1,T4,T21
StCtrlProg - - - - - 1 - Covered T1,T4,T17
StCtrlProg - - - - - 0 - Covered T1,T4,T17
StCtrl - - - - - - 1 Covered T4,T8,T22
StCtrl - - - - - - 0 Covered T4,T8,T22
StDisable - - - - - - - Covered T2,T12,T13
default - - - - - - - Covered T14,T15,T16


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 380169193 1423511 0 0
CtrlPrio_A 380169193 1423511 0 0
HostTransIdleChk_A 380169193 22249763 0 0
NoRemainder_A 1057 1057 0 0
OneHotReqs_A 380169193 379323980 0 0
Pow2Multiple_A 1057 1057 0 0
RdTxnCheck_A 379812483 378967270 0 0
u_state_regs_A 380169193 379323980 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 1423511 0 0
T1 444296 6022 0 0
T2 1058 0 0 0
T3 1351 0 0 0
T4 139108 0 0 0
T5 42400 0 0 0
T6 0 3367 0 0
T7 0 1613 0 0
T17 226638 0 0 0
T18 1117 0 0 0
T19 274053 0 0 0
T20 1488 0 0 0
T21 67178 0 0 0
T45 0 40479 0 0
T58 0 1695 0 0
T77 0 36874 0 0
T152 0 636 0 0
T192 0 1582 0 0
T200 0 648 0 0
T222 0 2363 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 1423511 0 0
T1 444296 6022 0 0
T2 1058 0 0 0
T3 1351 0 0 0
T4 139108 0 0 0
T5 42400 0 0 0
T6 0 3367 0 0
T7 0 1613 0 0
T17 226638 0 0 0
T18 1117 0 0 0
T19 274053 0 0 0
T20 1488 0 0 0
T21 67178 0 0 0
T45 0 40479 0 0
T58 0 1695 0 0
T77 0 36874 0 0
T152 0 636 0 0
T192 0 1582 0 0
T200 0 648 0 0
T222 0 2363 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 22249763 0 0
T1 444296 67081 0 0
T2 1058 0 0 0
T3 1351 0 0 0
T4 139108 327 0 0
T5 42400 0 0 0
T6 0 45511 0 0
T7 0 34747 0 0
T8 0 102 0 0
T17 226638 0 0 0
T18 1117 0 0 0
T19 274053 0 0 0
T20 1488 0 0 0
T21 67178 0 0 0
T24 0 314 0 0
T31 0 31688 0 0
T34 0 23 0 0
T58 0 27556 0 0
T60 0 10 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1057 1057 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 379323980 0 0
T1 444296 444210 0 0
T2 1058 978 0 0
T3 1351 1286 0 0
T4 139108 139014 0 0
T5 42400 39889 0 0
T17 226638 226581 0 0
T18 1117 924 0 0
T19 274053 273974 0 0
T20 1488 1271 0 0
T21 67178 67090 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1057 1057 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 379812483 378967270 0 0
T1 444296 444210 0 0
T2 1058 978 0 0
T3 1351 1286 0 0
T4 139108 139014 0 0
T5 42400 39889 0 0
T17 226638 226581 0 0
T18 1117 924 0 0
T19 274053 273974 0 0
T20 1488 1271 0 0
T21 67178 67090 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 379323980 0 0
T1 444296 444210 0 0
T2 1058 978 0 0
T3 1351 1286 0 0
T4 139108 139014 0 0
T5 42400 39889 0 0
T17 226638 226581 0 0
T18 1117 924 0 0
T19 274053 273974 0 0
T20 1488 1271 0 0
T21 67178 67090 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS2296583.33
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 0 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions10610195.28
Logical10610195.28
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11CoveredT85,T86,T220

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT85,T86,T220

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T4,T8
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T4,T8
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T8
110Not Covered
111CoveredT1,T4,T8

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T8
101CoveredT1,T4,T8
110CoveredT66,T67
111CoveredT1,T4,T8

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T8
11CoveredT1,T4,T8

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T8
11CoveredT1,T4,T8

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT104
10CoveredT1,T2,T3
11CoveredT1,T4,T8

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11CoveredT1,T4,T8

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T4,T21
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T4,T17
10CoveredT4,T5,T8
11CoveredT1,T2,T4

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT66,T67
10CoveredT60,T221

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT60,T221

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT1,T2,T3
11CoveredT66,T67

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT4,T5,T8
10CoveredT1,T2,T3
11CoveredT4,T5,T8

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T24,T28
10CoveredT4,T5,T8

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT204

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T4,T8
10CoveredT204
11CoveredT204

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T8

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T8
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT204

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT14,T15,T16

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T17

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T17

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 341 Covered T4,T5,T8
StCtrlProg 339 Covered T1,T2,T4
StCtrlRead 337 Covered T1,T2,T3
StDisable 335 Covered T2,T12,T13
StIdle 349 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 369 Covered T4,T5,T8
StCtrlProg->StIdle 359 Covered T1,T2,T4
StCtrlRead->StIdle 349 Covered T1,T2,T3
StIdle->StCtrl 341 Covered T4,T5,T8
StIdle->StCtrlProg 339 Covered T1,T2,T4
StIdle->StCtrlRead 337 Covered T1,T2,T3
StIdle->StDisable 335 Covered T2,T12,T13



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 2 100.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 3 75.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T204
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T4,T8
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T85,T86,T220
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T204
0 0 0 Covered T1,T4,T8


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T2,T12,T13
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T4
StIdle 0 0 0 1 - - - Covered T4,T5,T8
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T4
StCtrlProg - - - - - 0 - Covered T1,T2,T4
StCtrl - - - - - - 1 Covered T4,T5,T8
StCtrl - - - - - - 0 Covered T4,T5,T8
StDisable - - - - - - - Covered T2,T12,T13
default - - - - - - - Covered T14,T15,T16


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 380169193 1509619 0 0
CtrlPrio_A 380169193 1509619 0 0
HostTransIdleChk_A 380169193 21704480 0 0
NoRemainder_A 1057 1057 0 0
OneHotReqs_A 380169193 379323980 0 0
Pow2Multiple_A 1057 1057 0 0
RdTxnCheck_A 379812483 378967270 0 0
u_state_regs_A 380169193 379323980 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 1509619 0 0
T1 444296 8572 0 0
T2 1058 0 0 0
T3 1351 0 0 0
T4 139108 84 0 0
T5 42400 0 0 0
T6 0 3456 0 0
T7 0 6327 0 0
T17 226638 0 0 0
T18 1117 0 0 0
T19 274053 0 0 0
T20 1488 0 0 0
T21 67178 0 0 0
T24 0 84 0 0
T25 0 3906 0 0
T28 0 84 0 0
T31 0 4907 0 0
T58 0 4377 0 0
T192 0 1384 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 1509619 0 0
T1 444296 8572 0 0
T2 1058 0 0 0
T3 1351 0 0 0
T4 139108 84 0 0
T5 42400 0 0 0
T6 0 3456 0 0
T7 0 6327 0 0
T17 226638 0 0 0
T18 1117 0 0 0
T19 274053 0 0 0
T20 1488 0 0 0
T21 67178 0 0 0
T24 0 84 0 0
T25 0 3906 0 0
T28 0 84 0 0
T31 0 4907 0 0
T58 0 4377 0 0
T192 0 1384 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 21704480 0 0
T1 444296 70809 0 0
T2 1058 0 0 0
T3 1351 0 0 0
T4 139108 489 0 0
T5 42400 0 0 0
T6 0 45567 0 0
T7 0 43576 0 0
T8 0 146 0 0
T17 226638 0 0 0
T18 1117 0 0 0
T19 274053 0 0 0
T20 1488 0 0 0
T21 67178 0 0 0
T24 0 356 0 0
T31 0 26110 0 0
T34 0 22 0 0
T58 0 28296 0 0
T60 0 10 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1057 1057 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 379323980 0 0
T1 444296 444210 0 0
T2 1058 978 0 0
T3 1351 1286 0 0
T4 139108 139014 0 0
T5 42400 39889 0 0
T17 226638 226581 0 0
T18 1117 924 0 0
T19 274053 273974 0 0
T20 1488 1271 0 0
T21 67178 67090 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1057 1057 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 379812483 378967270 0 0
T1 444296 444210 0 0
T2 1058 978 0 0
T3 1351 1286 0 0
T4 139108 139014 0 0
T5 42400 39889 0 0
T17 226638 226581 0 0
T18 1117 924 0 0
T19 274053 273974 0 0
T20 1488 1271 0 0
T21 67178 67090 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 380169193 379323980 0 0
T1 444296 444210 0 0
T2 1058 978 0 0
T3 1351 1286 0 0
T4 139108 139014 0 0
T5 42400 39889 0 0
T17 226638 226581 0 0
T18 1117 924 0 0
T19 274053 273974 0 0
T20 1488 1271 0 0
T21 67178 67090 0 0