Module Definition
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Module Instance : tb.dut.u_reg_core.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T1,*T4,*T17 Yes T1,T4,T17 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T1,T2,T3 Yes T1,T2,T4 INPUT
data_o[56:0] Yes Yes T1,T4,T17 Yes T1,T4,T17 OUTPUT
syndrome_o[6:0] Yes Yes T18,T20,T5 Yes T18,T20,T5 OUTPUT
err_o[1:0] Yes Yes T1,T4,T18 Yes T18,T20,T5 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_core.u_chk.u_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T1,*T4,*T17 Yes T1,T4,T17 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T1,T2,T3 Yes T1,T2,T4 INPUT
data_o[56:0] Yes Yes T1,T4,T17 Yes T1,T4,T17 OUTPUT
syndrome_o[6:0] Yes Yes T18,T5,T50 Yes T18,T5,T50 OUTPUT
err_o[1:0] Yes Yes T18,T5,T50 Yes T18,T5,T50 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T18,*T60,*T6 Yes T1,T4,T18 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T1,T4,T18 Yes T1,T4,T18 INPUT
data_o[56:0] Yes Yes T18,T60,T6 Yes T1,T4,T18 OUTPUT
syndrome_o[6:0] Yes Yes T18,T6,T12 Yes T18,T120,T6 OUTPUT
err_o[1:0] Yes Yes T1,T4,T18 Yes T18,T60,T6 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 232 232 100.00
Total Bits 0->1 116 116 100.00
Total Bits 1->0 116 116 100.00

Ports 4 4 100.00
Port Bits 232 232 100.00
Port Bits 0->1 116 116 100.00
Port Bits 1->0 116 116 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[42:0] Yes Yes *T18,*T20,*T6 Yes T1,T18,T35 INPUT
data_i[56:43] Unreachable Unreachable Unreachable INPUT
data_i[63:57] Yes Yes T3,T20,T81 Yes T120,T125,T58 INPUT
data_o[56:0] Yes Yes T18,T20,T6 Yes T1,T18,T35 OUTPUT
syndrome_o[6:0] Yes Yes T18,T20,T25 Yes T18,T20,T120 OUTPUT
err_o[1:0] Yes Yes T1,T4,T18 Yes T20,T125,T58 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%