Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1520676772	1517295920	0	0
CheckNGreaterZero_A	4228	4228	0	0
GntImpliesReady_A	1520676772	397331533	0	0
GntImpliesValid_A	1520676772	397331533	0	0
GrantKnown_A	1520676772	1517295920	0	0
IdxKnown_A	1520676772	1517295920	0	0
IndexIsCorrect_A	1520676772	397331533	0	0
NoReadyValidNoGrant_A	1520676772	176943659	0	0
Priority_A	1520676772	421690440	0	0
ReadyAndValidImplyGrant_A	1520676772	397331533	0	0
ReqAndReadyImplyGrant_A	1520676772	397331533	0	0
ReqImpliesValid_A	1520676772	421690440	0	0
ValidKnown_A	1520676772	1517295920	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	1517295920	0	0
T1	1777184	1776840	0	0
T2	4232	3912	0	0
T3	5404	5144	0	0
T4	556432	556056	0	0
T5	169600	159556	0	0
T17	906552	906324	0	0
T18	4468	3696	0	0
T19	1096212	1095896	0	0
T20	5952	5084	0	0
T21	268712	268360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4228	4228	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	397331533	0	0
T1	1777184	643510	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	269682	0	0
T5	169600	50800	0	0
T6	0	109766	0	0
T7	0	52548	0	0
T8	0	1934	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	17186	0	0
T60	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	397331533	0	0
T1	1777184	643510	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	269682	0	0
T5	169600	50800	0	0
T6	0	109766	0	0
T7	0	52548	0	0
T8	0	1934	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	17186	0	0
T60	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	1517295920	0	0
T1	1777184	1776840	0	0
T2	4232	3912	0	0
T3	5404	5144	0	0
T4	556432	556056	0	0
T5	169600	159556	0	0
T17	906552	906324	0	0
T18	4468	3696	0	0
T19	1096212	1095896	0	0
T20	5952	5084	0	0
T21	268712	268360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	1517295920	0	0
T1	1777184	1776840	0	0
T2	4232	3912	0	0
T3	5404	5144	0	0
T4	556432	556056	0	0
T5	169600	159556	0	0
T17	906552	906324	0	0
T18	4468	3696	0	0
T19	1096212	1095896	0	0
T20	5952	5084	0	0
T21	268712	268360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	397331533	0	0
T1	1777184	643510	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	269682	0	0
T5	169600	50800	0	0
T6	0	109766	0	0
T7	0	52548	0	0
T8	0	1934	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	17186	0	0
T60	0	10	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	176943659	0	0
T1	1777184	188354	0	0
T2	4232	256	0	0
T3	5404	256	0	0
T4	556432	2016	0	0
T5	169600	13096	0	0
T6	0	76422	0	0
T7	0	58074	0	0
T8	0	236	0	0
T17	906552	256	0	0
T18	4468	522	0	0
T19	1096212	256	0	0
T20	5952	520	0	0
T21	268712	3998	0	0
T22	0	3372	0	0
T31	0	51136	0	0
T34	0	246	0	0
T60	0	12	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	421690440	0	0
T1	1777184	747600	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	270074	0	0
T5	169600	50800	0	0
T6	0	125602	0	0
T7	0	60260	0	0
T8	0	1988	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	20180	0	0
T60	0	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	397331533	0	0
T1	1777184	643510	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	269682	0	0
T5	169600	50800	0	0
T6	0	109766	0	0
T7	0	52548	0	0
T8	0	1934	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	17186	0	0
T60	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	397331533	0	0
T1	1777184	643510	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	269682	0	0
T5	169600	50800	0	0
T6	0	109766	0	0
T7	0	52548	0	0
T8	0	1934	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	17186	0	0
T60	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	421690440	0	0
T1	1777184	747600	0	0
T2	4232	196	0	0
T3	5404	64	0	0
T4	556432	270074	0	0
T5	169600	50800	0	0
T6	0	125602	0	0
T7	0	60260	0	0
T8	0	1988	0	0
T17	906552	395488	0	0
T18	4468	132	0	0
T19	1096212	499624	0	0
T20	5952	130	0	0
T21	268712	97130	0	0
T31	0	20180	0	0
T60	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1520676772	1517295920	0	0
T1	1777184	1776840	0	0
T2	4232	3912	0	0
T3	5404	5144	0	0
T4	556432	556056	0	0
T5	169600	159556	0	0
T17	906552	906324	0	0
T18	4468	3696	0	0
T19	1096212	1095896	0	0
T20	5952	5084	0	0
T21	268712	268360	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380169193	379323980	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	380169193	104101593	0	0
GntImpliesValid_A	380169193	104101593	0	0
GrantKnown_A	380169193	379323980	0	0
IdxKnown_A	380169193	379323980	0	0
IndexIsCorrect_A	380169193	104101593	0	0
NoReadyValidNoGrant_A	380169193	45619599	0	0
Priority_A	380169193	110041466	0	0
ReadyAndValidImplyGrant_A	380169193	104101593	0	0
ReqAndReadyImplyGrant_A	380169193	104101593	0	0
ReqImpliesValid_A	380169193	110041466	0	0
ValidKnown_A	380169193	379323980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101593	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101593	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101593	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	45619599	0	0
T1	444296	48831	0	0
T2	1058	128	0	0
T3	1351	128	0	0
T4	139108	628	0	0
T5	42400	6548	0	0
T17	226638	128	0	0
T18	1117	261	0	0
T19	274053	128	0	0
T20	1488	260	0	0
T21	67178	231	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	110041466	0	0
T1	444296	200509	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1477	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101593	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101593	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	110041466	0	0
T1	444296	200509	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1477	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380169193	379323980	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	380169193	104101506	0	0
GntImpliesValid_A	380169193	104101506	0	0
GrantKnown_A	380169193	379323980	0	0
IdxKnown_A	380169193	379323980	0	0
IndexIsCorrect_A	380169193	104101506	0	0
NoReadyValidNoGrant_A	380169193	45619599	0	0
Priority_A	380169193	110041379	0	0
ReadyAndValidImplyGrant_A	380169193	104101506	0	0
ReqAndReadyImplyGrant_A	380169193	104101506	0	0
ReqImpliesValid_A	380169193	110041379	0	0
ValidKnown_A	380169193	379323980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101506	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101506	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101506	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	45619599	0	0
T1	444296	48831	0	0
T2	1058	128	0	0
T3	1351	128	0	0
T4	139108	628	0	0
T5	42400	6548	0	0
T17	226638	128	0	0
T18	1117	261	0	0
T19	274053	128	0	0
T20	1488	260	0	0
T21	67178	231	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	110041379	0	0
T1	444296	200509	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1477	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101506	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	104101506	0	0
T1	444296	173801	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1371	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	110041379	0	0
T1	444296	200509	0	0
T2	1058	98	0	0
T3	1351	32	0	0
T4	139108	1477	0	0
T5	42400	25400	0	0
T17	226638	90428	0	0
T18	1117	66	0	0
T19	274053	128306	0	0
T20	1488	65	0	0
T21	67178	32913	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380169193	379323980	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	380169193	94564212	0	0
GntImpliesValid_A	380169193	94564212	0	0
GrantKnown_A	380169193	379323980	0	0
IdxKnown_A	380169193	379323980	0	0
IndexIsCorrect_A	380169193	94564212	0	0
NoReadyValidNoGrant_A	380169193	42852226	0	0
Priority_A	380169193	100803797	0	0
ReadyAndValidImplyGrant_A	380169193	94564212	0	0
ReqAndReadyImplyGrant_A	380169193	94564212	0	0
ReqImpliesValid_A	380169193	100803797	0	0
ValidKnown_A	380169193	379323980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564212	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564212	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564212	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	42852226	0	0
T1	444296	45346	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	380	0	0
T5	42400	0	0	0
T6	0	38211	0	0
T7	0	29037	0	0
T8	0	118	0	0
T17	226638	0	0	0
T18	1117	0	0	0
T19	274053	0	0	0
T20	1488	0	0	0
T21	67178	1768	0	0
T22	0	1686	0	0
T31	0	25568	0	0
T34	0	123	0	0
T60	0	6	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	100803797	0	0
T1	444296	173291	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133560	0	0
T5	42400	0	0	0
T6	0	62801	0	0
T7	0	30130	0	0
T8	0	994	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	10090	0	0
T60	0	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564212	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564212	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	100803797	0	0
T1	444296	173291	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133560	0	0
T5	42400	0	0	0
T6	0	62801	0	0
T7	0	30130	0	0
T8	0	994	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	10090	0	0
T60	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T4,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380169193	379323980	0	0
CheckNGreaterZero_A	1057	1057	0	0
GntImpliesReady_A	380169193	94564222	0	0
GntImpliesValid_A	380169193	94564222	0	0
GrantKnown_A	380169193	379323980	0	0
IdxKnown_A	380169193	379323980	0	0
IndexIsCorrect_A	380169193	94564222	0	0
NoReadyValidNoGrant_A	380169193	42852235	0	0
Priority_A	380169193	100803798	0	0
ReadyAndValidImplyGrant_A	380169193	94564222	0	0
ReqAndReadyImplyGrant_A	380169193	94564222	0	0
ReqImpliesValid_A	380169193	100803798	0	0
ValidKnown_A	380169193	379323980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564222	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564222	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564222	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	42852235	0	0
T1	444296	45346	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	380	0	0
T5	42400	0	0	0
T6	0	38211	0	0
T7	0	29037	0	0
T8	0	118	0	0
T17	226638	0	0	0
T18	1117	0	0	0
T19	274053	0	0	0
T20	1488	0	0	0
T21	67178	1768	0	0
T22	0	1686	0	0
T31	0	25568	0	0
T34	0	123	0	0
T60	0	6	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	100803798	0	0
T1	444296	173291	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133560	0	0
T5	42400	0	0	0
T6	0	62801	0	0
T7	0	30130	0	0
T8	0	994	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	10090	0	0
T60	0	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564222	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	94564222	0	0
T1	444296	147954	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133470	0	0
T5	42400	0	0	0
T6	0	54883	0	0
T7	0	26274	0	0
T8	0	967	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	8593	0	0
T60	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	100803798	0	0
T1	444296	173291	0	0
T2	1058	0	0	0
T3	1351	0	0	0
T4	139108	133560	0	0
T5	42400	0	0	0
T6	0	62801	0	0
T7	0	30130	0	0
T8	0	994	0	0
T17	226638	107316	0	0
T18	1117	0	0	0
T19	274053	121506	0	0
T20	1488	0	0	0
T21	67178	15652	0	0
T31	0	10090	0	0
T60	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380169193	379323980	0	0
T1	444296	444210	0	0
T2	1058	978	0	0
T3	1351	1286	0	0
T4	139108	139014	0	0
T5	42400	39889	0	0
T17	226638	226581	0	0
T18	1117	924	0	0
T19	274053	273974	0	0
T20	1488	1271	0	0
T21	67178	67090	0	0