Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27050053	1		T1	9449		T2	195		T3	500
full_word	7887015	1		T1	9563		T2	48		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34936768	1		T1	19012		T2	243		T3	505
auto[TlIntgErrCmd]	93	1		T104	3		T206	6		T207	5
auto[TlIntgErrData]	106	1		T104	3		T206	7		T207	2
auto[TlIntgErrBoth]	101	1		T104	4		T206	7		T207	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30374272	1		T1	11192		T2	191		T3	497
auto[1]	4562796	1		T1	7820		T2	52		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26318083	1		T1	8492		T2	188		T3	497
auto[TlIntgErrNone]	partial	auto[1]	731692	1		T1	957		T2	7		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	4056052	1		T1	2700		T2	3		T18	2
auto[TlIntgErrNone]	full_word	auto[1]	3830941	1		T1	6863		T2	45		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T104	1		T206	2		T208	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T104	2		T206	4		T207	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T207	1		T208	2		T359	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T208	1		T274	1		T361	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T104	2		T206	2		T207	2
auto[TlIntgErrData]	partial	auto[1]	46	1		T206	5		T208	5		T357	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T104	1		T208	1		T274	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T208	1		T357	1		T277	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T104	2		T206	3		T207	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T104	2		T206	3		T207	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T304	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T206	1		T208	1		T274	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20633	1		T67	271		T102	548		T103	84
full_word	3776606	1		T4	16396		T23	24		T21	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3796958	1		T4	16396		T23	24		T21	10
auto[TlIntgErrCmd]	111	1		T104	7		T206	8		T207	4
auto[TlIntgErrData]	91	1		T104	2		T206	6		T207	3
auto[TlIntgErrBoth]	79	1		T206	5		T207	3		T208	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3771389	1		T4	16396		T23	24		T21	10
auto[1]	25850	1		T67	422		T102	804		T103	118

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1370	1		T67	3		T102	60		T103	7
auto[TlIntgErrNone]	partial	auto[1]	19011	1		T67	268		T102	488		T103	77
auto[TlIntgErrNone]	full_word	auto[0]	3769906	1		T4	16396		T23	24		T21	10
auto[TlIntgErrNone]	full_word	auto[1]	6671	1		T67	154		T102	316		T103	41
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T104	1		T206	3		T207	3
auto[TlIntgErrCmd]	partial	auto[1]	68	1		T104	4		T206	5		T207	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T208	1		T274	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T104	2		T246	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T104	2		T206	2		T207	2
auto[TlIntgErrData]	partial	auto[1]	39	1		T206	2		T207	1		T208	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T357	1		T277	1		T362	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T206	2		T208	1		T304	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T206	2		T207	1		T208	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1		T206	2		T207	2		T208	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T274	1		T363	1		T277	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T206	1		T276	2		T277	1