Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T23,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T21
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T21

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1560082336	1556676560	0	0
CheckNGreaterZero_A	4240	4240	0	0
GntImpliesReady_A	1560082336	405117747	0	0
GntImpliesValid_A	1560082336	405117747	0	0
GrantKnown_A	1560082336	1556676560	0	0
IdxKnown_A	1560082336	1556676560	0	0
IndexIsCorrect_A	1560082336	405117747	0	0
NoReadyValidNoGrant_A	1560082336	172631972	0	0
Priority_A	1560082336	429463343	0	0
ReadyAndValidImplyGrant_A	1560082336	405117747	0	0
ReqAndReadyImplyGrant_A	1560082336	405117747	0	0
ReqImpliesValid_A	1560082336	429463343	0	0
ValidKnown_A	1560082336	1556676560	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	1556676560	0	0
T1	841360	841116	0	0
T2	4904	4604	0	0
T3	13388	10612	0	0
T4	2321064	2320384	0	0
T5	806784	771484	0	0
T11	5076	4768	0	0
T14	14032	11376	0	0
T18	3850920	3850260	0	0
T19	4716	4368	0	0
T20	6164	5112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4240	4240	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T11	4	4	0	0
T14	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	405117747	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	35516	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	430	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	21808	0	0
T60	0	255794	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	405117747	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	35516	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	430	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	21808	0	0
T60	0	255794	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	1556676560	0	0
T1	841360	841116	0	0
T2	4904	4604	0	0
T3	13388	10612	0	0
T4	2321064	2320384	0	0
T5	806784	771484	0	0
T11	5076	4768	0	0
T14	14032	11376	0	0
T18	3850920	3850260	0	0
T19	4716	4368	0	0
T20	6164	5112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	1556676560	0	0
T1	841360	841116	0	0
T2	4904	4604	0	0
T3	13388	10612	0	0
T4	2321064	2320384	0	0
T5	806784	771484	0	0
T11	5076	4768	0	0
T14	14032	11376	0	0
T18	3850920	3850260	0	0
T19	4716	4368	0	0
T20	6164	5112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	405117747	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	35516	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	430	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	21808	0	0
T60	0	255794	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	172631972	0	0
T1	841360	7564	0	0
T2	4904	256	0	0
T3	13388	1144	0	0
T4	2321064	1209690	0	0
T5	806784	45776	0	0
T6	0	586	0	0
T7	0	10	0	0
T11	5076	256	0	0
T14	14032	1372	0	0
T18	3850920	384	0	0
T19	4716	256	0	0
T20	6164	536	0	0
T21	0	56	0	0
T22	0	120	0	0
T23	0	244	0	0
T26	0	58	0	0
T41	0	27818	0	0
T60	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	429463343	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	575270	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	436	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	35600	0	0
T60	0	255794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	405117747	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	35516	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	430	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	21808	0	0
T60	0	255794	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	405117747	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	35516	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	430	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	21808	0	0
T60	0	255794	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	429463343	0	0
T1	841360	90208	0	0
T2	4904	584	0	0
T3	13388	300	0	0
T4	2321064	575270	0	0
T5	806784	172408	0	0
T6	0	134648	0	0
T7	0	436	0	0
T11	5076	584	0	0
T14	14032	366	0	0
T18	3850920	1410	0	0
T19	4716	64	0	0
T20	6164	134	0	0
T21	0	20	0	0
T23	0	630	0	0
T26	0	154	0	0
T41	0	35600	0	0
T60	0	255794	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1560082336	1556676560	0	0
T1	841360	841116	0	0
T2	4904	4604	0	0
T3	13388	10612	0	0
T4	2321064	2320384	0	0
T5	806784	771484	0	0
T11	5076	4768	0	0
T14	14032	11376	0	0
T18	3850920	3850260	0	0
T19	4716	4368	0	0
T20	6164	5112	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T23,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390020584	389169140	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	390020584	100862033	0	0
GntImpliesValid_A	390020584	100862033	0	0
GrantKnown_A	390020584	389169140	0	0
IdxKnown_A	390020584	389169140	0	0
IndexIsCorrect_A	390020584	100862033	0	0
NoReadyValidNoGrant_A	390020584	44302199	0	0
Priority_A	390020584	107030107	0	0
ReadyAndValidImplyGrant_A	390020584	100862033	0	0
ReqAndReadyImplyGrant_A	390020584	100862033	0	0
ReqImpliesValid_A	390020584	107030107	0	0
ValidKnown_A	390020584	389169140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	44302199	0	0
T1	210340	1730	0	0
T2	1226	128	0	0
T3	3347	572	0	0
T4	580266	323879	0	0
T5	201696	22888	0	0
T11	1269	128	0	0
T14	3508	686	0	0
T18	962730	192	0	0
T19	1179	128	0	0
T20	1541	268	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107030107	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	165279	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107030107	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	165279	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T23,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390020584	389169140	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	390020584	100862033	0	0
GntImpliesValid_A	390020584	100862033	0	0
GrantKnown_A	390020584	389169140	0	0
IdxKnown_A	390020584	389169140	0	0
IndexIsCorrect_A	390020584	100862033	0	0
NoReadyValidNoGrant_A	390020584	44302199	0	0
Priority_A	390020584	107030107	0	0
ReadyAndValidImplyGrant_A	390020584	100862033	0	0
ReqAndReadyImplyGrant_A	390020584	100862033	0	0
ReqImpliesValid_A	390020584	107030107	0	0
ValidKnown_A	390020584	389169140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	44302199	0	0
T1	210340	1730	0	0
T2	1226	128	0	0
T3	3347	572	0	0
T4	580266	323879	0	0
T5	201696	22888	0	0
T11	1269	128	0	0
T14	3508	686	0	0
T18	962730	192	0	0
T19	1179	128	0	0
T20	1541	268	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107030107	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	165279	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	100862033	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	9927	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107030107	0	0
T1	210340	19613	0	0
T2	1226	32	0	0
T3	3347	150	0	0
T4	580266	165279	0	0
T5	201696	86204	0	0
T11	1269	292	0	0
T14	3508	183	0	0
T18	962730	705	0	0
T19	1179	32	0	0
T20	1541	67	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T23
1	0	Covered	T4,T23,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T21,T7
1	0	Covered	T1,T2,T23
1	1	Covered	T4,T23,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T21
1	1	Covered	T1,T2,T23

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T21,T7
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390020584	389169140	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	390020584	101696884	0	0
GntImpliesValid_A	390020584	101696884	0	0
GrantKnown_A	390020584	389169140	0	0
IdxKnown_A	390020584	389169140	0	0
IndexIsCorrect_A	390020584	101696884	0	0
NoReadyValidNoGrant_A	390020584	42013787	0	0
Priority_A	390020584	107701608	0	0
ReadyAndValidImplyGrant_A	390020584	101696884	0	0
ReqAndReadyImplyGrant_A	390020584	101696884	0	0
ReqImpliesValid_A	390020584	107701608	0	0
ValidKnown_A	390020584	389169140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696884	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696884	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696884	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	42013787	0	0
T1	210340	2052	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	280966	0	0
T5	201696	0	0	0
T6	0	293	0	0
T7	0	5	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	28	0	0
T22	0	60	0	0
T23	0	122	0	0
T26	0	29	0	0
T41	0	13909	0	0
T60	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107701608	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	122356	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	218	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	17800	0	0
T60	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696884	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696884	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107701608	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	122356	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	218	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	17800	0	0
T60	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T23
1	0	Covered	T4,T23,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T23,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T21,T7
1	0	Covered	T1,T2,T23
1	1	Covered	T4,T23,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T21
1	1	Covered	T1,T2,T23

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T21,T7
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T23,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	390020584	389169140	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	390020584	101696797	0	0
GntImpliesValid_A	390020584	101696797	0	0
GrantKnown_A	390020584	389169140	0	0
IdxKnown_A	390020584	389169140	0	0
IndexIsCorrect_A	390020584	101696797	0	0
NoReadyValidNoGrant_A	390020584	42013787	0	0
Priority_A	390020584	107701521	0	0
ReadyAndValidImplyGrant_A	390020584	101696797	0	0
ReqAndReadyImplyGrant_A	390020584	101696797	0	0
ReqImpliesValid_A	390020584	107701521	0	0
ValidKnown_A	390020584	389169140	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696797	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696797	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696797	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	42013787	0	0
T1	210340	2052	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	280966	0	0
T5	201696	0	0	0
T6	0	293	0	0
T7	0	5	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	28	0	0
T22	0	60	0	0
T23	0	122	0	0
T26	0	29	0	0
T41	0	13909	0	0
T60	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107701521	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	122356	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	218	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	17800	0	0
T60	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696797	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	101696797	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	7831	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	215	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	10904	0	0
T60	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	107701521	0	0
T1	210340	25491	0	0
T2	1226	260	0	0
T3	3347	0	0	0
T4	580266	122356	0	0
T5	201696	0	0	0
T6	0	67324	0	0
T7	0	218	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	10	0	0
T23	0	315	0	0
T26	0	77	0	0
T41	0	17800	0	0
T60	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0