Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22758178	1		T1	4816		T2	20		T3	11418
full_word	7665299	1		T1	12809		T3	10841		T12	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30423167	1		T1	17625		T2	20		T3	22259
auto[TlIntgErrCmd]	97	1		T71	2		T109	7		T226	5
auto[TlIntgErrData]	101	1		T71	5		T109	5		T226	8
auto[TlIntgErrBoth]	112	1		T71	3		T109	8		T226	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25962057	1		T1	4237		T2	19		T3	18532
auto[1]	4461420	1		T1	13388		T2	1		T3	3727

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22070472	1		T1	2156		T2	19		T3	11250
auto[TlIntgErrNone]	partial	auto[1]	687423	1		T1	2660		T2	1		T3	168
auto[TlIntgErrNone]	full_word	auto[0]	3891456	1		T1	2081		T3	7282		T12	1
auto[TlIntgErrNone]	full_word	auto[1]	3773816	1		T1	10728		T3	3559		T12	5
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T71	1		T109	2		T226	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T71	1		T109	5		T226	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T232	1		T267	1		T272	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T267	1		T350	2		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1		T71	3		T109	2		T226	5
auto[TlIntgErrData]	partial	auto[1]	44	1		T71	2		T109	2		T226	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T109	1		T229	2		T348	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T226	1		T232	1		T265	3
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T71	1		T109	3		T226	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T71	2		T109	5		T226	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T229	1		T351	1		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T349	1		T265	1		T348	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18324	1		T107	638		T71	9		T108	15
full_word	3811770	1		T4	50		T6	52		T7	193

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3829807	1		T4	50		T6	52		T7	193
auto[TlIntgErrCmd]	98	1		T71	3		T109	6		T226	6
auto[TlIntgErrData]	97	1		T71	4		T109	8		T226	5
auto[TlIntgErrBoth]	92	1		T71	3		T109	5		T226	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3806608	1		T4	50		T6	52		T7	193
auto[1]	23486	1		T107	735		T71	4		T108	23

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1167	1		T107	38		T215	26		T216	25
auto[TlIntgErrNone]	partial	auto[1]	16895	1		T107	600		T108	15		T215	601
auto[TlIntgErrNone]	full_word	auto[0]	3805319	1		T4	50		T6	52		T7	193
auto[TlIntgErrNone]	full_word	auto[1]	6426	1		T107	135		T108	8		T215	124
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T71	1		T226	3		T227	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T71	2		T109	6		T226	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T229	1		T349	1		T353	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T232	1		T354	1		T267	2
auto[TlIntgErrData]	partial	auto[0]	46	1		T71	3		T109	3		T226	3
auto[TlIntgErrData]	partial	auto[1]	42	1		T71	1		T109	3		T226	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T109	2		T265	1		T266	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T229	1		T354	1		T355	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T71	1		T109	5		T226	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T71	1		T226	7		T227	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T71	1		T351	1		T350	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T226	1		T227	1		T232	1