Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1426063784	1422494356	0	0
CheckNGreaterZero_A	4240	4240	0	0
GntImpliesReady_A	1426063784	385640958	0	0
GntImpliesValid_A	1426063784	385640958	0	0
GrantKnown_A	1426063784	1422494356	0	0
IdxKnown_A	1426063784	1422494356	0	0
IndexIsCorrect_A	1426063784	385640958	0	0
NoReadyValidNoGrant_A	1426063784	176151104	0	0
Priority_A	1426063784	409526720	0	0
ReadyAndValidImplyGrant_A	1426063784	385640958	0	0
ReqAndReadyImplyGrant_A	1426063784	385640958	0	0
ReqImpliesValid_A	1426063784	409526720	0	0
ValidKnown_A	1426063784	1422494356	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	1422494356	0	0
T1	754184	753928	0	0
T2	5284	4884	0	0
T3	211884	211568	0	0
T4	383876	379288	0	0
T5	819876	789216	0	0
T12	12072	9396	0	0
T18	13596	13384	0	0
T19	426768	426536	0	0
T20	5700	5324	0	0
T21	7644	7296	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4240	4240	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T12	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	385640958	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	614	0	0
T8	0	16028	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	385640958	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	614	0	0
T8	0	16028	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	1422494356	0	0
T1	754184	753928	0	0
T2	5284	4884	0	0
T3	211884	211568	0	0
T4	383876	379288	0	0
T5	819876	789216	0	0
T12	12072	9396	0	0
T18	13596	13384	0	0
T19	426768	426536	0	0
T20	5700	5324	0	0
T21	7644	7296	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	1422494356	0	0
T1	754184	753928	0	0
T2	5284	4884	0	0
T3	211884	211568	0	0
T4	383876	379288	0	0
T5	819876	789216	0	0
T12	12072	9396	0	0
T18	13596	13384	0	0
T19	426768	426536	0	0
T20	5700	5324	0	0
T21	7644	7296	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	385640958	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	614	0	0
T8	0	16028	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	176151104	0	0
T1	377092	256	0	0
T2	2642	256	0	0
T3	105942	5248	0	0
T4	383876	4434	0	0
T5	819876	37704	0	0
T6	0	76	0	0
T7	0	550	0	0
T8	0	605180	0	0
T12	6036	704	0	0
T13	7520	0	0	0
T18	13596	256	0	0
T19	426768	2638	0	0
T20	5700	256	0	0
T21	7644	992	0	0
T24	420846	0	0	0
T25	0	52	0	0
T31	0	105098	0	0
T33	0	1230924	0	0
T42	0	34	0	0
T49	522270	0	0	0
T50	0	180	0	0
T53	2588	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	409526720	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	658	0	0
T8	0	221706	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	385640958	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	614	0	0
T8	0	16028	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	385640958	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	614	0	0
T8	0	16028	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	409526720	0	0
T1	754184	324548	0	0
T2	5284	64	0	0
T3	211884	31248	0	0
T4	383876	140310	0	0
T5	819876	131216	0	0
T6	0	570	0	0
T7	0	658	0	0
T8	0	221706	0	0
T12	12072	188	0	0
T18	13596	64	0	0
T19	426768	181306	0	0
T20	5700	64	0	0
T21	7644	356	0	0
T24	0	1796984	0	0
T42	0	22	0	0
T59	0	256356	0	0
T60	0	29592	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1426063784	1422494356	0	0
T1	754184	753928	0	0
T2	5284	4884	0	0
T3	211884	211568	0	0
T4	383876	379288	0	0
T5	819876	789216	0	0
T12	12072	9396	0	0
T18	13596	13384	0	0
T19	426768	426536	0	0
T20	5700	5324	0	0
T21	7644	7296	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356515946	355623589	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	356515946	100362354	0	0
GntImpliesValid_A	356515946	100362354	0	0
GrantKnown_A	356515946	355623589	0	0
IdxKnown_A	356515946	355623589	0	0
IndexIsCorrect_A	356515946	100362354	0	0
NoReadyValidNoGrant_A	356515946	45707929	0	0
Priority_A	356515946	106299931	0	0
ReadyAndValidImplyGrant_A	356515946	100362354	0	0
ReqAndReadyImplyGrant_A	356515946	100362354	0	0
ReqImpliesValid_A	356515946	106299931	0	0
ValidKnown_A	356515946	355623589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	45707929	0	0
T1	188546	128	0	0
T2	1321	128	0	0
T3	52971	2624	0	0
T4	95969	2105	0	0
T5	204969	18852	0	0
T12	3018	352	0	0
T18	3399	128	0	0
T19	106692	862	0	0
T20	1425	128	0	0
T21	1911	496	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	106299931	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	106299931	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356515946	355623589	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	356515946	100362354	0	0
GntImpliesValid_A	356515946	100362354	0	0
GrantKnown_A	356515946	355623589	0	0
IdxKnown_A	356515946	355623589	0	0
IndexIsCorrect_A	356515946	100362354	0	0
NoReadyValidNoGrant_A	356515946	45707929	0	0
Priority_A	356515946	106299931	0	0
ReadyAndValidImplyGrant_A	356515946	100362354	0	0
ReqAndReadyImplyGrant_A	356515946	100362354	0	0
ReqImpliesValid_A	356515946	106299931	0	0
ValidKnown_A	356515946	355623589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	45707929	0	0
T1	188546	128	0	0
T2	1321	128	0	0
T3	52971	2624	0	0
T4	95969	2105	0	0
T5	204969	18852	0	0
T12	3018	352	0	0
T18	3399	128	0	0
T19	106692	862	0	0
T20	1425	128	0	0
T21	1911	496	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	106299931	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	100362354	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	106299931	0	0
T1	188546	121598	0	0
T2	1321	32	0	0
T3	52971	15624	0	0
T4	95969	67828	0	0
T5	204969	65608	0	0
T12	3018	94	0	0
T18	3399	32	0	0
T19	106692	54093	0	0
T20	1425	32	0	0
T21	1911	178	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T6,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T33
1	0	Covered	T1,T4,T19
1	1	Covered	T6,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T33
1	1	Covered	T1,T4,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356515946	355623589	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	356515946	92458125	0	0
GntImpliesValid_A	356515946	92458125	0	0
GrantKnown_A	356515946	355623589	0	0
IdxKnown_A	356515946	355623589	0	0
IndexIsCorrect_A	356515946	92458125	0	0
NoReadyValidNoGrant_A	356515946	42367623	0	0
Priority_A	356515946	98463429	0	0
ReadyAndValidImplyGrant_A	356515946	92458125	0	0
ReqAndReadyImplyGrant_A	356515946	92458125	0	0
ReqImpliesValid_A	356515946	98463429	0	0
ValidKnown_A	356515946	355623589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	42367623	0	0
T4	95969	112	0	0
T5	204969	0	0	0
T6	0	38	0	0
T7	0	275	0	0
T8	0	302590	0	0
T13	3760	0	0	0
T18	3399	0	0	0
T19	106692	457	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	210423	0	0	0
T25	0	26	0	0
T31	0	52549	0	0
T33	0	615462	0	0
T42	0	17	0	0
T49	261135	0	0	0
T50	0	90	0	0
T53	1294	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	98463429	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	329	0	0
T8	0	110853	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	98463429	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	329	0	0
T8	0	110853	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T6,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T33
1	0	Covered	T1,T4,T19
1	1	Covered	T6,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T33
1	1	Covered	T1,T4,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	356515946	355623589	0	0
CheckNGreaterZero_A	1060	1060	0	0
GntImpliesReady_A	356515946	92458125	0	0
GntImpliesValid_A	356515946	92458125	0	0
GrantKnown_A	356515946	355623589	0	0
IdxKnown_A	356515946	355623589	0	0
IndexIsCorrect_A	356515946	92458125	0	0
NoReadyValidNoGrant_A	356515946	42367623	0	0
Priority_A	356515946	98463429	0	0
ReadyAndValidImplyGrant_A	356515946	92458125	0	0
ReqAndReadyImplyGrant_A	356515946	92458125	0	0
ReqImpliesValid_A	356515946	98463429	0	0
ValidKnown_A	356515946	355623589	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	42367623	0	0
T4	95969	112	0	0
T5	204969	0	0	0
T6	0	38	0	0
T7	0	275	0	0
T8	0	302590	0	0
T13	3760	0	0	0
T18	3399	0	0	0
T19	106692	457	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	210423	0	0	0
T25	0	26	0	0
T31	0	52549	0	0
T33	0	615462	0	0
T42	0	17	0	0
T49	261135	0	0	0
T50	0	90	0	0
T53	1294	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	98463429	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	329	0	0
T8	0	110853	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	92458125	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	307	0	0
T8	0	8014	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	98463429	0	0
T1	188546	40676	0	0
T2	1321	0	0	0
T3	52971	0	0	0
T4	95969	2327	0	0
T5	204969	0	0	0
T6	0	285	0	0
T7	0	329	0	0
T8	0	110853	0	0
T12	3018	0	0	0
T18	3399	0	0	0
T19	106692	36560	0	0
T20	1425	0	0	0
T21	1911	0	0	0
T24	0	898492	0	0
T42	0	11	0	0
T59	0	128178	0	0
T60	0	14796	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	356515946	355623589	0	0
T1	188546	188482	0	0
T2	1321	1221	0	0
T3	52971	52892	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	1425	1331	0	0
T21	1911	1824	0	0