Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync	100.00	100.00					100.00
tb.dut.u_lc_seed_hw_rd_en_sync	100.00	100.00					100.00
tb.dut.u_flash_hw_if.u_sync_rma_req	100.00	100.00					100.00
tb.dut.u_prog_tl_gate.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_lc_escalation_en_sync	100.00	100.00					100.00
tb.dut.u_tl_gate.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.17	100.00	94.79		92.11	98.94	100.00	u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.37	100.00	88.89		57.14	95.83	50.00	u_prog_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.60	100.00	100.00		57.14	95.83	50.00	u_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_lc_seed_hw_rd_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prog_tl_gate.u_err_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	5	5

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10600	10600	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.OutputDelay_A	2147483647	2147483647	0	22050
gen_no_flops.OutputDelay_A	699858262	698073548	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10600	10600	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T12	10	10	0	0
T18	10	10	0	0
T19	10	10	0	0
T20	10	10	0	0
T21	10	10	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1885460	1884820	0	0
T2	4100	3100	0	0
T3	3260	2470	0	0
T4	959690	948220	0	0
T5	2049690	1973040	0	0
T12	30180	23490	0	0
T18	33990	33460	0	0
T19	1066920	1066340	0	0
T20	3980	3040	0	0
T21	19110	18240	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	22050
T1	1508368	1507832	0	24
T2	3280	2480	0	0
T3	2608	1976	0	0
T4	767752	758216	0	24
T5	1639752	1576008	0	24
T12	24144	18576	0	24
T13	0	0	0	24
T18	27192	26744	0	24
T19	853536	853048	0	24
T20	3184	2432	0	0
T21	15288	14568	0	24
T24	0	0	0	24
T49	0	0	0	24

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699858262	698073548	0	0
T1	377092	376964	0	0
T2	820	620	0	0
T3	652	494	0	0
T4	191938	189644	0	0
T5	409938	394608	0	0
T12	6036	4698	0	0
T18	6798	6692	0	0
T19	213384	213268	0	0
T20	796	608	0	0
T21	3822	3648	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929165	349036808	0	0
gen_flops.OutputDelay_A	349929165	349001819	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349036808	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349001819	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929165	349036808	0	0
gen_flops.OutputDelay_A	349929165	349001819	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349036808	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349001819	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929165	349036808	0	0
gen_flops.OutputDelay_A	349929165	349001819	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349036808	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349001819	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929165	349036808	0	0
gen_flops.OutputDelay_A	349929165	349001819	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349036808	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349001819	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929165	349036808	0	0
gen_flops.OutputDelay_A	349929165	349001819	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349036808	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349001819	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929165	349036808	0	0
gen_flops.OutputDelay_A	349929165	349001819	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349036808	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929165	349001819	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929131	349036774	0	0
gen_no_flops.OutputDelay_A	349929131	349036774	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929131	349036774	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929131	349036774	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349909126	349016769	0	0
gen_flops.OutputDelay_A	349909126	348981930	0	2625

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349909126	349016769	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349909126	348981930	0	2625
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3

Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929131	349036774	0	0
gen_no_flops.OutputDelay_A	349929131	349036774	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929131	349036774	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929131	349036774	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	5	5

---

Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1060	1060	0	0
OutputsKnown_A	349929131	349036774	0	0
gen_flops.OutputDelay_A	349929131	349001800	0	2775

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929131	349036774	0	0
T1	188546	188482	0	0
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94822	0	0
T5	204969	197304	0	0
T12	3018	2349	0	0
T18	3399	3346	0	0
T19	106692	106634	0	0
T20	398	304	0	0
T21	1911	1824	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	349929131	349001800	0	2775
T1	188546	188479	0	3
T2	410	310	0	0
T3	326	247	0	0
T4	95969	94777	0	3
T5	204969	197001	0	3
T12	3018	2322	0	3
T13	0	0	0	3
T18	3399	3343	0	3
T19	106692	106631	0	3
T20	398	304	0	0
T21	1911	1821	0	3
T24	0	0	0	3
T49	0	0	0	3