Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23597676	1		T1	3233		T2	8459		T3	39959
full_word	7674792	1		T1	4123		T2	32897		T3	7320

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31272198	1		T1	7356		T2	41356		T3	47279
auto[TlIntgErrCmd]	89	1		T66	1		T209	8		T223	3
auto[TlIntgErrData]	83	1		T66	7		T209	5		T223	3
auto[TlIntgErrBoth]	98	1		T66	2		T209	7		T223	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26798937	1		T1	2930		T2	34581		T3	41768
auto[1]	4473531	1		T1	4426		T2	6775		T3	5511

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22896642	1		T1	2929		T2	6010		T3	39222
auto[TlIntgErrNone]	partial	auto[1]	700781	1		T1	304		T2	2449		T3	737
auto[TlIntgErrNone]	full_word	auto[0]	3902169	1		T1	1		T2	28571		T3	2546
auto[TlIntgErrNone]	full_word	auto[1]	3772606	1		T1	4122		T2	4326		T3	4774
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T66	1		T209	5		T223	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T209	3		T223	2		T274	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T277	1		T361	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T271	1		T362	2		T276	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T66	3		T209	1		T274	4
auto[TlIntgErrData]	partial	auto[1]	36	1		T66	4		T209	2		T223	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T209	1		T225	1		T269	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T209	1		T363	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T66	2		T209	2		T223	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T209	5		T223	3		T274	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T276	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T225	1		T362	1		T277	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18455	1		T65	97		T66	8		T117	730
full_word	3782485	1		T2	16857		T3	15807		T6	16331

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3800683	1		T2	16857		T3	15807		T6	16331
auto[TlIntgErrCmd]	88	1		T66	7		T209	9		T223	3
auto[TlIntgErrData]	74	1		T66	2		T209	5		T223	1
auto[TlIntgErrBoth]	95	1		T209	6		T223	5		T274	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3777153	1		T2	16857		T3	15807		T6	16331
auto[1]	23787	1		T65	136		T66	7		T117	1346

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1105	1		T65	5		T117	24		T118	7
auto[TlIntgErrNone]	partial	auto[1]	17114	1		T65	92		T117	706		T118	91
auto[TlIntgErrNone]	full_word	auto[0]	3775953	1		T2	16857		T3	15807		T6	16331
auto[TlIntgErrNone]	full_word	auto[1]	6511	1		T65	44		T117	640		T118	38
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T66	2		T209	5		T223	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T66	5		T209	4		T223	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T361	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T223	1		T225	1		T271	1
auto[TlIntgErrData]	partial	auto[0]	35	1		T209	3		T223	1		T274	4
auto[TlIntgErrData]	partial	auto[1]	32	1		T66	1		T209	2		T274	4
auto[TlIntgErrData]	full_word	auto[0]	2	1		T364	1		T276	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T66	1		T270	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T209	2		T274	1		T273	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T209	4		T223	5		T274	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T273	1		T271	1		T269	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T274	1		T273	1		T271	1