Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1538670336	1535234800	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1538670336	399712500	0	0
GntImpliesValid_A	1538670336	399712500	0	0
GrantKnown_A	1538670336	1535234800	0	0
IdxKnown_A	1538670336	1535234800	0	0
IndexIsCorrect_A	1538670336	399712500	0	0
NoReadyValidNoGrant_A	1538670336	168501958	0	0
Priority_A	1538670336	423200996	0	0
ReadyAndValidImplyGrant_A	1538670336	399712500	0	0
ReqAndReadyImplyGrant_A	1538670336	399712500	0	0
ReqImpliesValid_A	1538670336	423200996	0	0
ValidKnown_A	1538670336	1535234800	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	1535234800	0	0
T1	211048	210816	0	0
T2	490188	490124	0	0
T3	409480	409128	0	0
T4	824968	824720	0	0
T5	273132	272760	0	0
T6	696676	696056	0	0
T16	211936	211612	0	0
T17	388220	387996	0	0
T18	4344	4092	0	0
T19	4868	4660	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	399712500	0	0
T1	211048	30556	0	0
T2	490188	87606	0	0
T3	409480	115900	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	82198	0	0
T16	211936	40738	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	151918	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	399712500	0	0
T1	211048	30556	0	0
T2	490188	87606	0	0
T3	409480	115900	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	82198	0	0
T16	211936	40738	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	151918	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	1535234800	0	0
T1	211048	210816	0	0
T2	490188	490124	0	0
T3	409480	409128	0	0
T4	824968	824720	0	0
T5	273132	272760	0	0
T6	696676	696056	0	0
T16	211936	211612	0	0
T17	388220	387996	0	0
T18	4344	4092	0	0
T19	4868	4660	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	1535234800	0	0
T1	211048	210816	0	0
T2	490188	490124	0	0
T3	409480	409128	0	0
T4	824968	824720	0	0
T5	273132	272760	0	0
T6	696676	696056	0	0
T16	211936	211612	0	0
T17	388220	387996	0	0
T18	4344	4092	0	0
T19	4868	4660	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	399712500	0	0
T1	211048	30556	0	0
T2	490188	87606	0	0
T3	409480	115900	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	82198	0	0
T16	211936	40738	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	151918	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	168501958	0	0
T1	105524	256	0	0
T2	490188	2679218	0	0
T3	409480	121250	0	0
T4	824968	4224	0	0
T5	273132	328	0	0
T6	696676	226858	0	0
T16	211936	116714	0	0
T17	388220	7464	0	0
T18	4344	286	0	0
T19	4868	256	0	0
T31	0	24	0	0
T32	0	16	0	0
T33	0	24	0	0
T43	390842	42984	0	0
T47	0	36024	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	423200996	0	0
T1	211048	30556	0	0
T2	490188	575498	0	0
T3	409480	133230	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	85606	0	0
T16	211936	43742	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	167922	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	399712500	0	0
T1	211048	30556	0	0
T2	490188	87606	0	0
T3	409480	115900	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	82198	0	0
T16	211936	40738	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	151918	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	399712500	0	0
T1	211048	30556	0	0
T2	490188	87606	0	0
T3	409480	115900	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	82198	0	0
T16	211936	40738	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	151918	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	423200996	0	0
T1	211048	30556	0	0
T2	490188	575498	0	0
T3	409480	133230	0	0
T4	824968	2632	0	0
T5	273132	132276	0	0
T6	696676	85606	0	0
T16	211936	43742	0	0
T17	388220	122562	0	0
T18	4344	84	0	0
T19	4868	64	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	6	0	0
T43	0	167922	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	1535234800	0	0
T1	211048	210816	0	0
T2	490188	490124	0	0
T3	409480	409128	0	0
T4	824968	824720	0	0
T5	273132	272760	0	0
T6	696676	696056	0	0
T16	211936	211612	0	0
T17	388220	387996	0	0
T18	4344	4092	0	0
T19	4868	4660	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	104318593	0	0
GntImpliesValid_A	384667584	104318593	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	104318593	0	0
NoReadyValidNoGrant_A	384667584	43714351	0	0
Priority_A	384667584	110348313	0	0
ReadyAndValidImplyGrant_A	384667584	104318593	0	0
ReqAndReadyImplyGrant_A	384667584	104318593	0	0
ReqImpliesValid_A	384667584	110348313	0	0
ValidKnown_A	384667584	383808700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318593	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318593	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318593	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	43714351	0	0
T1	52762	128	0	0
T2	122547	699998	0	0
T3	102370	31621	0	0
T4	206242	2112	0	0
T5	68283	164	0	0
T6	174169	58356	0	0
T16	52984	32066	0	0
T17	97055	1938	0	0
T18	1086	143	0	0
T19	1217	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	110348313	0	0
T1	52762	6917	0	0
T2	122547	151690	0	0
T3	102370	34042	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	22161	0	0
T16	52984	12046	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318593	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318593	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	110348313	0	0
T1	52762	6917	0	0
T2	122547	151690	0	0
T3	102370	34042	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	22161	0	0
T16	52984	12046	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	104318512	0	0
GntImpliesValid_A	384667584	104318512	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	104318512	0	0
NoReadyValidNoGrant_A	384667584	43714353	0	0
Priority_A	384667584	110348230	0	0
ReadyAndValidImplyGrant_A	384667584	104318512	0	0
ReqAndReadyImplyGrant_A	384667584	104318512	0	0
ReqImpliesValid_A	384667584	110348230	0	0
ValidKnown_A	384667584	383808700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318512	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318512	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318512	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	43714353	0	0
T1	52762	128	0	0
T2	122547	699998	0	0
T3	102370	31621	0	0
T4	206242	2112	0	0
T5	68283	164	0	0
T6	174169	58356	0	0
T16	52984	32066	0	0
T17	97055	1938	0	0
T18	1086	143	0	0
T19	1217	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	110348230	0	0
T1	52762	6917	0	0
T2	122547	151690	0	0
T3	102370	34042	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	22161	0	0
T16	52984	12046	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318512	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	104318512	0	0
T1	52762	6917	0	0
T2	122547	23133	0	0
T3	102370	29283	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	21264	0	0
T16	52984	11462	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	110348230	0	0
T1	52762	6917	0	0
T2	122547	151690	0	0
T3	102370	34042	0	0
T4	206242	1316	0	0
T5	68283	66138	0	0
T6	174169	22161	0	0
T16	52984	12046	0	0
T17	97055	30424	0	0
T18	1086	42	0	0
T19	1217	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	95537767	0	0
GntImpliesValid_A	384667584	95537767	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	95537767	0	0
NoReadyValidNoGrant_A	384667584	40536626	0	0
Priority_A	384667584	101252297	0	0
ReadyAndValidImplyGrant_A	384667584	95537767	0	0
ReqAndReadyImplyGrant_A	384667584	95537767	0	0
ReqImpliesValid_A	384667584	101252297	0	0
ValidKnown_A	384667584	383808700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537767	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537767	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537767	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	40536626	0	0
T2	122547	639611	0	0
T3	102370	29004	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	55073	0	0
T16	52984	26291	0	0
T17	97055	1794	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	12	0	0
T43	195421	21492	0	0
T47	0	18012	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	101252297	0	0
T1	52762	8361	0	0
T2	122547	136059	0	0
T3	102370	32573	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	20642	0	0
T16	52984	9825	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	83961	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537767	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537767	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	101252297	0	0
T1	52762	8361	0	0
T2	122547	136059	0	0
T3	102370	32573	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	20642	0	0
T16	52984	9825	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	83961	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	95537628	0	0
GntImpliesValid_A	384667584	95537628	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	95537628	0	0
NoReadyValidNoGrant_A	384667584	40536628	0	0
Priority_A	384667584	101252156	0	0
ReadyAndValidImplyGrant_A	384667584	95537628	0	0
ReqAndReadyImplyGrant_A	384667584	95537628	0	0
ReqImpliesValid_A	384667584	101252156	0	0
ValidKnown_A	384667584	383808700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537628	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537628	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537628	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	40536628	0	0
T2	122547	639611	0	0
T3	102370	29004	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	55073	0	0
T16	52984	26291	0	0
T17	97055	1794	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	12	0	0
T32	0	8	0	0
T33	0	12	0	0
T43	195421	21492	0	0
T47	0	18012	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	101252156	0	0
T1	52762	8361	0	0
T2	122547	136059	0	0
T3	102370	32573	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	20642	0	0
T16	52984	9825	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	83961	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537628	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95537628	0	0
T1	52762	8361	0	0
T2	122547	20670	0	0
T3	102370	28667	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	19835	0	0
T16	52984	8907	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	75959	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	101252156	0	0
T1	52762	8361	0	0
T2	122547	136059	0	0
T3	102370	32573	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	20642	0	0
T16	52984	9825	0	0
T17	97055	30857	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	6	0	0
T32	0	4	0	0
T33	0	3	0	0
T43	0	83961	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0