Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.11	96.15	94.53			100.00	93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random	92.50	92.31	97.69			100.00	80.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random	92.50	92.31	97.69			100.00	80.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb	95.01	100.00	86.27			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb	95.50	100.00	88.24			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	92.31	97.69			100.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.61			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.01	100.00	86.27			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.01	100.00	86.27			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.50	100.00	88.24			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :

SCORE	LINE
92.50	92.31

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	LINE
92.50	92.31

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	LINE
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
95.01	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T3,T6,T16
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T92
1	0	1	Unreachable	T3,T6,T16
1	1	0	Covered	T3,T6,T16
1	1	1	Unreachable	T3,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T16
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
95.50	88.24

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
95.01	86.27

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	45	88.24
Logical	51	45	88.24
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T6,T16
1	1	1	Covered	T3,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T16
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T91
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :

SCORE	COND
92.50	97.69

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	COND
92.50	97.69

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T54,T178,T179
1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
92.50	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	BRANCH
92.50	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	BRANCH
95.50	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
95.01	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	6348	6348	0	0
GntImpliesReady_A	2147483647	70493475	0	0
GntImpliesValid_A	2147483647	70493475	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	70493475	0	0
LockArbDecision_A	2147483647	65524298	0	0
NoReadyValidNoGrant_A	2147483647	1967601380	0	0
ReadyAndValidImplyGrant_A	2147483647	70493475	0	0
ReqAndReadyImplyGrant_A	2147483647	70493475	0	0
ReqImpliesValid_A	2147483647	325387595	0	0
ReqStaysHighUntilGranted0_M	2147483647	65523972	0	0
RoundRobin_A	2147483647	0	0	6318
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	1538670336	65524504	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	316572	316224	0	0
T2	735282	735186	0	0
T3	614220	613692	0	0
T4	1237452	1237080	0	0
T5	409698	409140	0	0
T6	1045014	1044084	0	0
T16	317904	317418	0	0
T17	582330	581994	0	0
T18	6516	6138	0	0
T19	7302	6990	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6348	6348	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T19	6	6	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70493475	0	0
T1	211048	128	0	0
T2	735282	31026	0	0
T3	614220	88221	0	0
T4	1237452	1532	0	0
T5	409698	138	0	0
T6	1045014	146353	0	0
T16	317904	93639	0	0
T17	582330	968	0	0
T18	6516	129	0	0
T19	7302	128	0	0
T31	0	34	0	0
T43	390842	18170	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70493475	0	0
T1	211048	128	0	0
T2	735282	31026	0	0
T3	614220	88221	0	0
T4	1237452	1532	0	0
T5	409698	138	0	0
T6	1045014	146353	0	0
T16	317904	93639	0	0
T17	582330	968	0	0
T18	6516	129	0	0
T19	7302	128	0	0
T31	0	34	0	0
T43	390842	18170	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	316572	316224	0	0
T2	735282	735186	0	0
T3	614220	613692	0	0
T4	1237452	1237080	0	0
T5	409698	409140	0	0
T6	1045014	1044084	0	0
T16	317904	317418	0	0
T17	582330	581994	0	0
T18	6516	6138	0	0
T19	7302	6990	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	316572	316224	0	0
T2	735282	735186	0	0
T3	614220	613692	0	0
T4	1237452	1237080	0	0
T5	409698	409140	0	0
T6	1045014	1044084	0	0
T16	317904	317418	0	0
T17	582330	581994	0	0
T18	6516	6138	0	0
T19	7302	6990	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70493475	0	0
T1	211048	128	0	0
T2	735282	31026	0	0
T3	614220	88221	0	0
T4	1237452	1532	0	0
T5	409698	138	0	0
T6	1045014	146353	0	0
T16	317904	93639	0	0
T17	582330	968	0	0
T18	6516	129	0	0
T19	7302	128	0	0
T31	0	34	0	0
T43	390842	18170	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	65524298	0	0
T1	211048	128	0	0
T2	490188	134	0	0
T3	409480	71320	0	0
T4	824968	1024	0	0
T5	273132	128	0	0
T6	696676	117140	0	0
T16	211936	74796	0	0
T17	388220	178	0	0
T18	4344	128	0	0
T19	4868	128	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967601380	0	0
T1	316572	315936	0	0
T2	735282	494807	0	0
T3	614220	267257	0	0
T4	1237452	1068419	0	0
T5	409698	407121	0	0
T6	1045014	463091	0	0
T16	317904	62807	0	0
T17	582330	421112	0	0
T18	6516	5150	0	0
T19	7302	6702	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70493475	0	0
T1	211048	128	0	0
T2	735282	31026	0	0
T3	614220	88221	0	0
T4	1237452	1532	0	0
T5	409698	138	0	0
T6	1045014	146353	0	0
T16	317904	93639	0	0
T17	582330	968	0	0
T18	6516	129	0	0
T19	7302	128	0	0
T31	0	34	0	0
T43	390842	18170	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	70493475	0	0
T1	211048	128	0	0
T2	735282	31026	0	0
T3	614220	88221	0	0
T4	1237452	1532	0	0
T5	409698	138	0	0
T6	1045014	146353	0	0
T16	317904	93639	0	0
T17	582330	968	0	0
T18	6516	129	0	0
T19	7302	128	0	0
T31	0	34	0	0
T43	390842	18170	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	325387595	0	0
T1	211048	256	0	0
T2	735282	244855	0	0
T3	614220	346395	0	0
T4	1237452	168625	0	0
T5	409698	1983	0	0
T6	1045014	580921	0	0
T16	317904	254571	0	0
T17	582330	160442	0	0
T18	6516	952	0	0
T19	7302	256	0	0
T31	0	1392	0	0
T32	0	1417	0	0
T43	390842	389919	0	0
T47	0	125793	0	0
T53	0	100997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	65523972	0	0
T1	211048	128	0	0
T2	490188	134	0	0
T3	409480	71320	0	0
T4	824968	1024	0	0
T5	273132	128	0	0
T6	696676	117140	0	0
T16	211936	74796	0	0
T17	388220	178	0	0
T18	4344	128	0	0
T19	4868	128	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	6318

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	316572	316224	0	0
T2	735282	735186	0	0
T3	614220	613692	0	0
T4	1237452	1237080	0	0
T5	409698	409140	0	0
T6	1045014	1044084	0	0
T16	317904	317418	0	0
T17	582330	581994	0	0
T18	6516	6138	0	0
T19	7302	6990	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538670336	65524504	0	0
T1	211048	128	0	0
T2	490188	134	0	0
T3	409480	71320	0	0
T4	824968	1024	0	0
T5	273132	128	0	0
T6	696676	117140	0	0
T16	211936	74796	0	0
T17	388220	178	0	0
T18	4344	128	0	0
T19	4868	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T54,T178,T179
1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	12	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	12	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	2503151	0	0
GntImpliesValid_A	384667584	2503151	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	2503151	0	0
LockArbDecision_A	384667584	0	0	0
NoReadyValidNoGrant_A	384667584	279275041	0	0
ReadyAndValidImplyGrant_A	384667584	2503151	0	0
ReqAndReadyImplyGrant_A	384667584	2503151	0	0
ReqImpliesValid_A	384667584	99289541	0	0
ReqStaysHighUntilGranted0_M	384667584	0	0	0
RoundRobin_A	384667584	0	0	1053
ValidKnown_A	384667584	383808700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2503151	0	0
T2	122547	16140	0	0
T3	102370	8606	0	0
T4	206242	508	0	0
T5	68283	10	0	0
T6	174169	15154	0	0
T16	52984	10284	0	0
T17	97055	400	0	0
T18	1086	1	0	0
T19	1217	0	0	0
T31	0	32	0	0
T43	195421	9500	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2503151	0	0
T2	122547	16140	0	0
T3	102370	8606	0	0
T4	206242	508	0	0
T5	68283	10	0	0
T6	174169	15154	0	0
T16	52984	10284	0	0
T17	97055	400	0	0
T18	1086	1	0	0
T19	1217	0	0	0
T31	0	32	0	0
T43	195421	9500	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2503151	0	0
T2	122547	16140	0	0
T3	102370	8606	0	0
T4	206242	508	0	0
T5	68283	10	0	0
T6	174169	15154	0	0
T16	52984	10284	0	0
T17	97055	400	0	0
T18	1086	1	0	0
T19	1217	0	0	0
T31	0	32	0	0
T43	195421	9500	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	279275041	0	0
T1	52762	52672	0	0
T2	122547	2442	0	0
T3	102370	363	0	0
T4	206242	39567	0	0
T5	68283	66427	0	0
T6	174169	633	0	0
T16	52984	373	0	0
T17	97055	17408	0	0
T18	1086	291	0	0
T19	1217	1133	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2503151	0	0
T2	122547	16140	0	0
T3	102370	8606	0	0
T4	206242	508	0	0
T5	68283	10	0	0
T6	174169	15154	0	0
T16	52984	10284	0	0
T17	97055	400	0	0
T18	1086	1	0	0
T19	1217	0	0	0
T31	0	32	0	0
T43	195421	9500	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2503151	0	0
T2	122547	16140	0	0
T3	102370	8606	0	0
T4	206242	508	0	0
T5	68283	10	0	0
T6	174169	15154	0	0
T16	52984	10284	0	0
T17	97055	400	0	0
T18	1086	1	0	0
T19	1217	0	0	0
T31	0	32	0	0
T43	195421	9500	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	99289541	0	0
T2	122547	122283	0	0
T3	102370	101883	0	0
T4	206242	166577	0	0
T5	68283	1727	0	0
T6	174169	173313	0	0
T16	52984	52494	0	0
T17	97055	79359	0	0
T18	1086	696	0	0
T19	1217	0	0	0
T31	0	482	0	0
T43	195421	194959	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	1053

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T54,T178,T179
1	1	Covered	T2,T3,T6

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T6
1	0	1	Covered	T2,T3,T6
1	1	0	Covered	T2,T3,T6
1	1	1	Covered	T2,T3,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T2,T3,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	12	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	12	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	2465820	0	0
GntImpliesValid_A	384667584	2465820	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	2465820	0	0
LockArbDecision_A	384667584	0	0	0
NoReadyValidNoGrant_A	384667584	284140686	0	0
ReadyAndValidImplyGrant_A	384667584	2465820	0	0
ReqAndReadyImplyGrant_A	384667584	2465820	0	0
ReqImpliesValid_A	384667584	95048939	0	0
ReqStaysHighUntilGranted0_M	384667584	0	0	0
RoundRobin_A	384667584	0	0	1053
ValidKnown_A	384667584	383808700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2465820	0	0
T2	122547	14752	0	0
T3	102370	8295	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	14059	0	0
T16	52984	8559	0	0
T17	97055	390	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	2	0	0
T43	195421	8670	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2465820	0	0
T2	122547	14752	0	0
T3	102370	8295	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	14059	0	0
T16	52984	8559	0	0
T17	97055	390	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	2	0	0
T43	195421	8670	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2465820	0	0
T2	122547	14752	0	0
T3	102370	8295	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	14059	0	0
T16	52984	8559	0	0
T17	97055	390	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	2	0	0
T43	195421	8670	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	284140686	0	0
T1	52762	52704	0	0
T2	122547	2267	0	0
T3	102370	406	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	682	0	0
T16	52984	414	0	0
T17	97055	16064	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2465820	0	0
T2	122547	14752	0	0
T3	102370	8295	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	14059	0	0
T16	52984	8559	0	0
T17	97055	390	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	2	0	0
T43	195421	8670	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	2465820	0	0
T2	122547	14752	0	0
T3	102370	8295	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	14059	0	0
T16	52984	8559	0	0
T17	97055	390	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	2	0	0
T43	195421	8670	0	0
T47	0	8976	0	0
T49	0	2	0	0
T53	0	6572	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	95048939	0	0
T2	122547	122304	0	0
T3	102370	101872	0	0
T4	206242	0	0	0
T5	68283	0	0	0
T6	174169	173328	0	0
T16	52984	52485	0	0
T17	97055	80727	0	0
T18	1086	0	0	0
T19	1217	0	0	0
T31	0	910	0	0
T32	0	1417	0	0
T43	195421	194960	0	0
T47	0	125793	0	0
T53	0	100997	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	1053

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	44	86.27
Logical	51	44	86.27
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T6,T16
1	1	1	Covered	T3,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T16
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	15743508	0	0
GntImpliesValid_A	384667584	15743508	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	15743508	0	0
LockArbDecision_A	384650373	15743424	0	0
NoReadyValidNoGrant_A	384667584	352321680	0	0
ReadyAndValidImplyGrant_A	384667584	15743508	0	0
ReqAndReadyImplyGrant_A	384667584	15743508	0	0
ReqImpliesValid_A	384667584	31487020	0	0
ReqStaysHighUntilGranted0_M	384650373	15743424	0	0
RoundRobin_A	384667584	0	0	1053
ValidKnown_A	384667584	383808700	0	0
gen_data_port_assertion.DataFlow_A	384667584	15743508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384650373	15743424	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	352321680	0	0
T1	52762	52640	0	0
T2	122547	122525	0	0
T3	102370	66622	0	0
T4	206242	205668	0	0
T5	68283	68126	0	0
T6	174169	115444	0	0
T16	52984	15505	0	0
T17	97055	96915	0	0
T18	1086	959	0	0
T19	1217	1101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	31487020	0	0
T1	52762	64	0	0
T2	122547	66	0	0
T3	102370	35660	0	0
T4	206242	512	0	0
T5	68283	64	0	0
T6	174169	58570	0	0
T16	52984	37398	0	0
T17	97055	84	0	0
T18	1086	64	0	0
T19	1217	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	384650373	15743424	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	1053

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	45	88.24
Logical	51	45	88.24
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T3,T6,T16
1	1	1	Covered	T3,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T16
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T91
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	15743508	0	0
GntImpliesValid_A	384667584	15743508	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	15743508	0	0
LockArbDecision_A	384650373	15743424	0	0
NoReadyValidNoGrant_A	384667584	352321595	0	0
ReadyAndValidImplyGrant_A	384667584	15743508	0	0
ReqAndReadyImplyGrant_A	384667584	15743508	0	0
ReqImpliesValid_A	384667584	31487105	0	0
ReqStaysHighUntilGranted0_M	384650373	15743424	0	0
RoundRobin_A	384667584	0	0	1053
ValidKnown_A	384667584	383808700	0	0
gen_data_port_assertion.DataFlow_A	384667584	15743508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384650373	15743424	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	352321595	0	0
T1	52762	52640	0	0
T2	122547	122525	0	0
T3	102370	66622	0	0
T4	206242	205668	0	0
T5	68283	68126	0	0
T6	174169	115444	0	0
T16	52984	15505	0	0
T17	97055	96915	0	0
T18	1086	959	0	0
T19	1217	1101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	31487105	0	0
T1	52762	64	0	0
T2	122547	66	0	0
T3	102370	35660	0	0
T4	206242	512	0	0
T5	68283	64	0	0
T6	174169	58570	0	0
T16	52984	37398	0	0
T17	97055	84	0	0
T18	1086	64	0	0
T19	1217	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	384650373	15743424	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	1053

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	15743508	0	0
T1	52762	32	0	0
T2	122547	33	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	42	0	0
T18	1086	32	0	0
T19	1217	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T3,T6,T16
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T92
1	0	1	Unreachable	T3,T6,T16
1	1	0	Covered	T3,T6,T16
1	1	1	Unreachable	T3,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T16
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	17018728	0	0
GntImpliesValid_A	384667584	17018728	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	17018728	0	0
LockArbDecision_A	384667517	17018725	0	0
NoReadyValidNoGrant_A	384667584	349771205	0	0
ReadyAndValidImplyGrant_A	384667584	17018728	0	0
ReqAndReadyImplyGrant_A	384667584	17018728	0	0
ReqImpliesValid_A	384667584	34037463	0	0
ReqStaysHighUntilGranted0_M	384650581	17018562	0	0
RoundRobin_A	384667584	0	0	1053
ValidKnown_A	384667584	383808700	0	0
gen_data_port_assertion.DataFlow_A	384667584	17018728	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018728	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018728	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018728	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667517	17018725	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	349771205	0	0
T1	52762	52640	0	0
T2	122547	122524	0	0
T3	102370	66622	0	0
T4	206242	205668	0	0
T5	68283	68126	0	0
T6	174169	115444	0	0
T16	52984	15505	0	0
T17	97055	96905	0	0
T18	1086	959	0	0
T19	1217	1101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018728	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018728	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	34037463	0	0
T1	52762	64	0	0
T2	122547	68	0	0
T3	102370	35660	0	0
T4	206242	512	0	0
T5	68283	64	0	0
T6	174169	58570	0	0
T16	52984	37398	0	0
T17	97055	94	0	0
T18	1086	64	0	0
T19	1217	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	384650581	17018562	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	1053

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018728	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T3,T6,T16
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T3,T6,T16
1	1	0	Covered	T3,T6,T16
1	1	1	Unreachable	T3,T6,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T16
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T3,T6,T16
1	1	Covered	T3,T6,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T16
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T16

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384667584	383808700	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	384667584	17018760	0	0
GntImpliesValid_A	384667584	17018760	0	0
GrantKnown_A	384667584	383808700	0	0
IdxKnown_A	384667584	383808700	0	0
IndexIsCorrect_A	384667584	17018760	0	0
LockArbDecision_A	384667517	17018725	0	0
NoReadyValidNoGrant_A	384667584	349771173	0	0
ReadyAndValidImplyGrant_A	384667584	17018760	0	0
ReqAndReadyImplyGrant_A	384667584	17018760	0	0
ReqImpliesValid_A	384667584	34037527	0	0
ReqStaysHighUntilGranted0_M	384650581	17018562	0	0
RoundRobin_A	384667584	0	0	1053
ValidKnown_A	384667584	383808700	0	0
gen_data_port_assertion.DataFlow_A	384667584	17018760	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018760	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018760	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018760	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667517	17018725	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	349771173	0	0
T1	52762	52640	0	0
T2	122547	122524	0	0
T3	102370	66622	0	0
T4	206242	205668	0	0
T5	68283	68126	0	0
T6	174169	115444	0	0
T16	52984	15505	0	0
T17	97055	96905	0	0
T18	1086	959	0	0
T19	1217	1101	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018760	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018760	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	34037527	0	0
T1	52762	64	0	0
T2	122547	68	0	0
T3	102370	35660	0	0
T4	206242	512	0	0
T5	68283	64	0	0
T6	174169	58570	0	0
T16	52984	37398	0	0
T17	97055	94	0	0
T18	1086	64	0	0
T19	1217	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	384650581	17018562	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	0	0	1053

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	383808700	0	0
T1	52762	52704	0	0
T2	122547	122531	0	0
T3	102370	102282	0	0
T4	206242	206180	0	0
T5	68283	68190	0	0
T6	174169	174014	0	0
T16	52984	52903	0	0
T17	97055	96999	0	0
T18	1086	1023	0	0
T19	1217	1165	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384667584	17018760	0	0
T1	52762	32	0	0
T2	122547	34	0	0
T3	102370	17830	0	0
T4	206242	256	0	0
T5	68283	32	0	0
T6	174169	29285	0	0
T16	52984	18699	0	0
T17	97055	47	0	0
T18	1086	32	0	0
T19	1217	32	0	0