Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26036581	1		T1	505		T2	12263		T3	34109
full_word	7731634	1		T2	9492		T3	773		T15	56

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33767945	1		T1	505		T2	21755		T3	34882
auto[TlIntgErrCmd]	96	1		T104	5		T105	5		T225	4
auto[TlIntgErrData]	88	1		T104	7		T105	10		T225	3
auto[TlIntgErrBoth]	86	1		T104	8		T105	5		T225	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29264896	1		T1	497		T2	13943		T3	34122
auto[1]	4503319	1		T1	8		T2	7812		T3	760

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25342186	1		T1	497		T2	11265		T3	34070
auto[TlIntgErrNone]	partial	auto[1]	694154	1		T1	8		T2	998		T3	39
auto[TlIntgErrNone]	full_word	auto[0]	3922577	1		T2	2678		T3	52		T4	4235
auto[TlIntgErrNone]	full_word	auto[1]	3809028	1		T2	6814		T3	721		T15	56
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T105	2		T225	1		T226	4
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T104	4		T105	3		T225	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T225	1		T333	1		T336	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T104	1		T226	1		T332	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T104	2		T105	1		T225	1
auto[TlIntgErrData]	partial	auto[1]	37	1		T104	3		T105	7		T225	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T104	1		T105	1		T337	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T104	1		T105	1		T225	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T104	3		T105	4		T225	1
auto[TlIntgErrBoth]	partial	auto[1]	40	1		T104	4		T105	1		T225	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T336	1		T334	1		T338	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T104	1		T336	1		T339	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21090	1		T66	138		T104	18		T105	19
full_word	3775456	1		T3	191		T4	9320		T16	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3796291	1		T3	191		T4	9320		T16	10
auto[TlIntgErrCmd]	76	1		T104	6		T105	9		T225	4
auto[TlIntgErrData]	83	1		T104	5		T105	4		T225	2
auto[TlIntgErrBoth]	96	1		T104	8		T105	7		T225	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3770236	1		T3	191		T4	9320		T16	10
auto[1]	26310	1		T66	188		T104	11		T105	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1368	1		T66	10		T191	16		T192	30
auto[TlIntgErrNone]	partial	auto[1]	19487	1		T66	128		T191	301		T192	703
auto[TlIntgErrNone]	full_word	auto[0]	3768768	1		T3	191		T4	9320		T16	10
auto[TlIntgErrNone]	full_word	auto[1]	6668	1		T66	60		T191	88		T192	295
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T104	2		T105	4		T226	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T104	4		T105	5		T225	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T225	1		T339	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T340	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1		T104	2		T105	1		T226	3
auto[TlIntgErrData]	partial	auto[1]	33	1		T104	2		T105	2		T226	4
auto[TlIntgErrData]	full_word	auto[0]	6	1		T104	1		T225	1		T259	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T105	1		T225	1		T226	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T104	3		T105	2		T226	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1		T104	5		T105	5		T225	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T341	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T333	1		T341	1		T342	1