Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1521422980	1517790940	0	0
CheckNGreaterZero_A	4224	4224	0	0
GntImpliesReady_A	1521422980	411358133	0	0
GntImpliesValid_A	1521422980	411358133	0	0
GrantKnown_A	1521422980	1517790940	0	0
IdxKnown_A	1521422980	1517790940	0	0
IndexIsCorrect_A	1521422980	411358133	0	0
NoReadyValidNoGrant_A	1521422980	173126786	0	0
Priority_A	1521422980	435621025	0	0
ReadyAndValidImplyGrant_A	1521422980	411358133	0	0
ReqAndReadyImplyGrant_A	1521422980	411358133	0	0
ReqImpliesValid_A	1521422980	435621025	0	0
ValidKnown_A	1521422980	1517790940	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	1517790940	0	0
T1	16032	13280	0	0
T2	654236	653920	0	0
T3	288104	287772	0	0
T4	712652	712424	0	0
T5	353444	353140	0	0
T6	297264	296968	0	0
T15	17624	17264	0	0
T16	6716	6200	0	0
T17	15860	15656	0	0
T18	1469456	1469076	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4224	4224	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	411358133	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136170	0	0
T4	712652	208866	0	0
T5	353444	154894	0	0
T6	297264	46730	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	463898	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	411358133	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136170	0	0
T4	712652	208866	0	0
T5	353444	154894	0	0
T6	297264	46730	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	463898	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	1517790940	0	0
T1	16032	13280	0	0
T2	654236	653920	0	0
T3	288104	287772	0	0
T4	712652	712424	0	0
T5	353444	353140	0	0
T6	297264	296968	0	0
T15	17624	17264	0	0
T16	6716	6200	0	0
T17	15860	15656	0	0
T18	1469456	1469076	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	1517790940	0	0
T1	16032	13280	0	0
T2	654236	653920	0	0
T3	288104	287772	0	0
T4	712652	712424	0	0
T5	353444	353140	0	0
T6	297264	296968	0	0
T15	17624	17264	0	0
T16	6716	6200	0	0
T17	15860	15656	0	0
T18	1469456	1469076	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	411358133	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136170	0	0
T4	712652	208866	0	0
T5	353444	154894	0	0
T6	297264	46730	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	463898	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	173126786	0	0
T1	8016	1408	0	0
T2	654236	7536	0	0
T3	288104	2104	0	0
T4	712652	150312	0	0
T5	353444	1628	0	0
T6	297264	132570	0	0
T15	17624	256	0	0
T16	6716	954	0	0
T17	15860	256	0	0
T18	1469456	200814	0	0
T19	0	984	0	0
T24	0	56	0	0
T25	0	98	0	0
T55	6986	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	435621025	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136792	0	0
T4	712652	242662	0	0
T5	353444	154894	0	0
T6	297264	49776	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	579022	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	411358133	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136170	0	0
T4	712652	208866	0	0
T5	353444	154894	0	0
T6	297264	46730	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	463898	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	411358133	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136170	0	0
T4	712652	208866	0	0
T5	353444	154894	0	0
T6	297264	46730	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	463898	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	435621025	0	0
T1	8016	354	0	0
T2	654236	110680	0	0
T3	288104	136792	0	0
T4	712652	242662	0	0
T5	353444	154894	0	0
T6	297264	49776	0	0
T15	17624	64	0	0
T16	6716	430	0	0
T17	15860	64	0	0
T18	1469456	579022	0	0
T19	0	420474	0	0
T24	0	20	0	0
T25	0	32	0	0
T55	6986	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1521422980	1517790940	0	0
T1	16032	13280	0	0
T2	654236	653920	0	0
T3	288104	287772	0	0
T4	712652	712424	0	0
T5	353444	353140	0	0
T6	297264	296968	0	0
T15	17624	17264	0	0
T16	6716	6200	0	0
T17	15860	15656	0	0
T18	1469456	1469076	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380355745	379447735	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	380355745	110785171	0	0
GntImpliesValid_A	380355745	110785171	0	0
GrantKnown_A	380355745	379447735	0	0
IdxKnown_A	380355745	379447735	0	0
IndexIsCorrect_A	380355745	110785171	0	0
NoReadyValidNoGrant_A	380355745	45174431	0	0
Priority_A	380355745	116708966	0	0
ReadyAndValidImplyGrant_A	380355745	110785171	0	0
ReqAndReadyImplyGrant_A	380355745	110785171	0	0
ReqImpliesValid_A	380355745	116708966	0	0
ValidKnown_A	380355745	379447735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	45174431	0	0
T1	4008	704	0	0
T2	163559	2400	0	0
T3	72026	614	0	0
T4	178163	40208	0	0
T5	88361	422	0	0
T6	74316	31520	0	0
T15	4406	128	0	0
T16	1679	447	0	0
T17	3965	128	0	0
T18	367364	53475	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	116708966	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67748	0	0
T4	178163	77174	0	0
T5	88361	70683	0	0
T6	74316	11886	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	143508	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	116708966	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67748	0	0
T4	178163	77174	0	0
T5	88361	70683	0	0
T6	74316	11886	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	143508	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380355745	379447735	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	380355745	110785171	0	0
GntImpliesValid_A	380355745	110785171	0	0
GrantKnown_A	380355745	379447735	0	0
IdxKnown_A	380355745	379447735	0	0
IndexIsCorrect_A	380355745	110785171	0	0
NoReadyValidNoGrant_A	380355745	45174431	0	0
Priority_A	380355745	116708966	0	0
ReadyAndValidImplyGrant_A	380355745	110785171	0	0
ReqAndReadyImplyGrant_A	380355745	110785171	0	0
ReqImpliesValid_A	380355745	116708966	0	0
ValidKnown_A	380355745	379447735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	45174431	0	0
T1	4008	704	0	0
T2	163559	2400	0	0
T3	72026	614	0	0
T4	178163	40208	0	0
T5	88361	422	0	0
T6	74316	31520	0	0
T15	4406	128	0	0
T16	1679	447	0	0
T17	3965	128	0	0
T18	367364	53475	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	116708966	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67748	0	0
T4	178163	77174	0	0
T5	88361	70683	0	0
T6	74316	11886	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	143508	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	110785171	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67521	0	0
T4	178163	66676	0	0
T5	88361	70683	0	0
T6	74316	11020	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	111984	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	116708966	0	0
T1	4008	177	0	0
T2	163559	34630	0	0
T3	72026	67748	0	0
T4	178163	77174	0	0
T5	88361	70683	0	0
T6	74316	11886	0	0
T15	4406	32	0	0
T16	1679	139	0	0
T17	3965	32	0	0
T18	367364	143508	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380355745	379447735	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	380355745	94893930	0	0
GntImpliesValid_A	380355745	94893930	0	0
GrantKnown_A	380355745	379447735	0	0
IdxKnown_A	380355745	379447735	0	0
IndexIsCorrect_A	380355745	94893930	0	0
NoReadyValidNoGrant_A	380355745	41388965	0	0
Priority_A	380355745	101101578	0	0
ReadyAndValidImplyGrant_A	380355745	94893930	0	0
ReqAndReadyImplyGrant_A	380355745	94893930	0	0
ReqImpliesValid_A	380355745	101101578	0	0
ValidKnown_A	380355745	379447735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893930	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893930	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893930	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	41388965	0	0
T2	163559	1368	0	0
T3	72026	438	0	0
T4	178163	34948	0	0
T5	88361	392	0	0
T6	74316	34765	0	0
T15	4406	0	0	0
T16	1679	30	0	0
T17	3965	0	0	0
T18	367364	46932	0	0
T19	0	492	0	0
T24	0	28	0	0
T25	0	49	0	0
T55	3493	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	101101578	0	0
T2	163559	20710	0	0
T3	72026	648	0	0
T4	178163	44157	0	0
T5	88361	6764	0	0
T6	74316	13002	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	146003	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893930	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893930	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	101101578	0	0
T2	163559	20710	0	0
T3	72026	648	0	0
T4	178163	44157	0	0
T5	88361	6764	0	0
T6	74316	13002	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	146003	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T16
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380355745	379447735	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	380355745	94893861	0	0
GntImpliesValid_A	380355745	94893861	0	0
GrantKnown_A	380355745	379447735	0	0
IdxKnown_A	380355745	379447735	0	0
IndexIsCorrect_A	380355745	94893861	0	0
NoReadyValidNoGrant_A	380355745	41388959	0	0
Priority_A	380355745	101101515	0	0
ReadyAndValidImplyGrant_A	380355745	94893861	0	0
ReqAndReadyImplyGrant_A	380355745	94893861	0	0
ReqImpliesValid_A	380355745	101101515	0	0
ValidKnown_A	380355745	379447735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893861	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893861	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893861	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	41388959	0	0
T2	163559	1368	0	0
T3	72026	438	0	0
T4	178163	34948	0	0
T5	88361	392	0	0
T6	74316	34765	0	0
T15	4406	0	0	0
T16	1679	30	0	0
T17	3965	0	0	0
T18	367364	46932	0	0
T19	0	492	0	0
T24	0	28	0	0
T25	0	49	0	0
T55	3493	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	101101515	0	0
T2	163559	20710	0	0
T3	72026	648	0	0
T4	178163	44157	0	0
T5	88361	6764	0	0
T6	74316	13002	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	146003	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893861	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	94893861	0	0
T2	163559	20710	0	0
T3	72026	564	0	0
T4	178163	37757	0	0
T5	88361	6764	0	0
T6	74316	12345	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	119965	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	101101515	0	0
T2	163559	20710	0	0
T3	72026	648	0	0
T4	178163	44157	0	0
T5	88361	6764	0	0
T6	74316	13002	0	0
T15	4406	0	0	0
T16	1679	76	0	0
T17	3965	0	0	0
T18	367364	146003	0	0
T19	0	210237	0	0
T24	0	10	0	0
T25	0	16	0	0
T55	3493	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380355745	379447735	0	0
T1	4008	3320	0	0
T2	163559	163480	0	0
T3	72026	71943	0	0
T4	178163	178106	0	0
T5	88361	88285	0	0
T6	74316	74242	0	0
T15	4406	4316	0	0
T16	1679	1550	0	0
T17	3965	3914	0	0
T18	367364	367269	0	0