SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 31723394 | 1 | T1 | 14 | T2 | 68154 | T3 | 109 | |||
auto[1] | 5193985 | 1 | T2 | 6548 | T3 | 2 | T17 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36917187 | 1 | T1 | 14 | T2 | 74702 | T3 | 111 | |||
values[1] | 19 | 1 | T75 | 1 | T231 | 1 | T245 | 1 | |||
values[2] | 5 | 1 | T245 | 1 | T251 | 2 | T261 | 2 | |||
values[3] | 96 | 1 | T75 | 8 | T231 | 7 | T245 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36917185 | 1 | T1 | 14 | T2 | 74702 | T3 | 111 | |||
values[1] | 25 | 1 | T231 | 2 | T245 | 3 | T367 | 1 | |||
values[2] | 7 | 1 | T231 | 1 | T261 | 1 | T368 | 1 | |||
values[3] | 87 | 1 | T75 | 4 | T231 | 7 | T245 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 36917089 | 1 | T1 | 14 | T2 | 74702 | T3 | 111 | |||
auto[TlIntgErrCmd] | 96 | 1 | T75 | 7 | T231 | 7 | T245 | 6 | |||
auto[TlIntgErrData] | 98 | 1 | T75 | 3 | T231 | 9 | T245 | 8 | |||
auto[TlIntgErrBoth] | 96 | 1 | T75 | 10 | T231 | 4 | T245 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 3765371 | 0 | T2 | 9414 | T4 | 16649 | T7 | 16679 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3765200 | 1 | T2 | 9414 | T4 | 16649 | T7 | 16679 | |||
values[1] | 17 | 1 | T75 | 1 | T231 | 3 | T245 | 1 | |||
values[2] | 3 | 1 | T367 | 1 | T369 | 1 | T370 | 1 | |||
values[3] | 87 | 1 | T75 | 3 | T231 | 5 | T245 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3765185 | 1 | T2 | 9414 | T4 | 16649 | T7 | 16679 | |||
values[1] | 20 | 1 | T245 | 1 | T367 | 1 | T251 | 2 | |||
values[2] | 4 | 1 | T231 | 2 | T367 | 1 | T369 | 1 | |||
values[3] | 95 | 1 | T75 | 11 | T231 | 8 | T245 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3765100 | 1 | T2 | 9414 | T4 | 16649 | T7 | 16679 | |||
auto[TlIntgErrCmd] | 85 | 1 | T75 | 4 | T231 | 7 | T245 | 5 | |||
auto[TlIntgErrData] | 100 | 1 | T75 | 10 | T231 | 8 | T245 | 9 | |||
auto[TlIntgErrBoth] | 86 | 1 | T75 | 4 | T231 | 5 | T245 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 77899 | 0 | T73 | 139 | T123 | 1586 | T75 | 1272 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 77701 | 1 | T73 | 139 | T123 | 1586 | T75 | 1258 | |||
values[1] | 15 | 1 | T75 | 1 | T231 | 1 | T371 | 1 | |||
values[2] | 5 | 1 | T245 | 1 | T251 | 1 | T371 | 1 | |||
values[3] | 105 | 1 | T75 | 7 | T231 | 6 | T245 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 77697 | 1 | T73 | 139 | T123 | 1586 | T75 | 1261 | |||
values[1] | 20 | 1 | T75 | 2 | T231 | 2 | T251 | 1 | |||
values[2] | 5 | 1 | T231 | 1 | T245 | 1 | T372 | 1 | |||
values[3] | 102 | 1 | T75 | 8 | T231 | 9 | T245 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 77609 | 1 | T73 | 139 | T123 | 1586 | T75 | 1252 | |||
auto[TlIntgErrCmd] | 88 | 1 | T75 | 9 | T231 | 5 | T245 | 5 | |||
auto[TlIntgErrData] | 92 | 1 | T75 | 6 | T231 | 8 | T245 | 7 | |||
auto[TlIntgErrBoth] | 110 | 1 | T75 | 5 | T231 | 7 | T245 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |