Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21268	1		T123	1261		T75	18		T126	1115
full_word	3744103	1		T2	9414		T4	16649		T7	16679

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3765100	1		T2	9414		T4	16649		T7	16679
auto[TlIntgErrCmd]	85	1		T75	4		T231	7		T245	5
auto[TlIntgErrData]	100	1		T75	10		T231	8		T245	9
auto[TlIntgErrBoth]	86	1		T75	4		T231	5		T245	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3738755	1		T2	9414		T4	16649		T7	16679
auto[1]	26616	1		T123	1542		T75	13		T126	1377

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1370	1		T123	65		T126	59		T212	132
auto[TlIntgErrNone]	partial	auto[1]	19642	1		T123	1196		T126	1056		T212	1001
auto[TlIntgErrNone]	full_word	auto[0]	3737270	1		T2	9414		T4	16649		T7	16679
auto[TlIntgErrNone]	full_word	auto[1]	6818	1		T123	346		T126	321		T212	512
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T75	2		T231	3		T245	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T75	2		T231	4		T245	4
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T373	1		T369	1		T374	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T75	2		T231	3		T245	5
auto[TlIntgErrData]	partial	auto[1]	47	1		T75	8		T231	3		T245	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T231	1		T371	1		T372	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T231	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T75	1		T231	3		T245	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T75	3		T231	1		T245	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T231	1		T371	1		T375	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T374	1		T370	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	29255422	1		T1	14		T2	64670		T3	64
full_word	7661957	1		T2	10032		T3	47		T4	45

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36917089	1		T1	14		T2	74702		T3	111
auto[TlIntgErrCmd]	96	1		T75	7		T231	7		T245	6
auto[TlIntgErrData]	98	1		T75	3		T231	9		T245	8
auto[TlIntgErrBoth]	96	1		T75	10		T231	4		T245	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32499598	1		T1	13		T2	67448		T3	61
auto[1]	4417781	1		T1	1		T2	7254		T3	50

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28572188	1		T1	13		T2	63671		T3	61
auto[TlIntgErrNone]	partial	auto[1]	682973	1		T1	1		T2	999		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	3927275	1		T2	3777		T4	1		T11	1
auto[TlIntgErrNone]	full_word	auto[1]	3734653	1		T2	6255		T3	47		T4	44
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T75	2		T231	2		T245	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T75	4		T231	5		T245	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T75	1		T245	1		T251	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T373	1		T376	1		T377	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T75	1		T231	5		T245	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T75	2		T231	4		T245	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T245	1		T251	3		T375	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T251	1		T373	1		T369	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T75	2		T245	1		T367	3
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T75	7		T231	4		T245	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T245	1		T261	1		T378	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T75	1		T251	1		T376	1