Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1556530828	1553273236	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1556530828	413908200	0	0
GntImpliesValid_A	1556530828	413908200	0	0
GrantKnown_A	1556530828	1553273236	0	0
IdxKnown_A	1556530828	1553273236	0	0
IndexIsCorrect_A	1556530828	413908200	0	0
NoReadyValidNoGrant_A	1556530828	177167151	0	0
Priority_A	1556530828	437674857	0	0
ReadyAndValidImplyGrant_A	1556530828	413908200	0	0
ReqAndReadyImplyGrant_A	1556530828	413908200	0	0
ReqImpliesValid_A	1556530828	437674857	0	0
ValidKnown_A	1556530828	1553273236	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	1553273236	0	0
T1	6532	6148	0	0
T2	625136	624764	0	0
T3	6612	5968	0	0
T4	2312268	2311684	0	0
T5	387708	387480	0	0
T7	491752	491704	0	0
T11	15492	12628	0	0
T12	4960	4624	0	0
T17	6592	5988	0	0
T18	27088	26824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	413908200	0	0
T1	3266	64	0	0
T2	625136	194950	0	0
T3	6612	144	0	0
T4	2312268	33372	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	87224	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6296	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	802	0	0
T60	2118	0	0	0
T61	0	270496	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	413908200	0	0
T1	3266	64	0	0
T2	625136	194950	0	0
T3	6612	144	0	0
T4	2312268	33372	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	87224	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6296	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	802	0	0
T60	2118	0	0	0
T61	0	270496	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	1553273236	0	0
T1	6532	6148	0	0
T2	625136	624764	0	0
T3	6612	5968	0	0
T4	2312268	2311684	0	0
T5	387708	387480	0	0
T7	491752	491704	0	0
T11	15492	12628	0	0
T12	4960	4624	0	0
T17	6592	5988	0	0
T18	27088	26824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	1553273236	0	0
T1	6532	6148	0	0
T2	625136	624764	0	0
T3	6612	5968	0	0
T4	2312268	2311684	0	0
T5	387708	387480	0	0
T7	491752	491704	0	0
T11	15492	12628	0	0
T12	4960	4624	0	0
T17	6592	5988	0	0
T18	27088	26824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	413908200	0	0
T1	3266	64	0	0
T2	625136	194950	0	0
T3	6612	144	0	0
T4	2312268	33372	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	87224	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6296	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	802	0	0
T60	2118	0	0	0
T61	0	270496	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	177167151	0	0
T1	3266	256	0	0
T2	625136	117554	0	0
T3	6612	512	0	0
T4	2312268	1208188	0	0
T5	387708	7420	0	0
T6	0	26	0	0
T7	491752	2728716	0	0
T11	15492	1294	0	0
T12	4960	256	0	0
T17	6592	512	0	0
T18	27088	1178	0	0
T29	0	3108	0	0
T30	0	78	0	0
T54	0	1192	0	0
T60	2118	0	0	0
T61	0	108598	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	437674857	0	0
T1	3266	64	0	0
T2	625136	228004	0	0
T3	6612	144	0	0
T4	2312268	512934	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	513252	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6462	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	806	0	0
T60	2118	0	0	0
T61	0	334524	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	413908200	0	0
T1	3266	64	0	0
T2	625136	194950	0	0
T3	6612	144	0	0
T4	2312268	33372	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	87224	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6296	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	802	0	0
T60	2118	0	0	0
T61	0	270496	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	413908200	0	0
T1	3266	64	0	0
T2	625136	194950	0	0
T3	6612	144	0	0
T4	2312268	33372	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	87224	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6296	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	802	0	0
T60	2118	0	0	0
T61	0	270496	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	437674857	0	0
T1	3266	64	0	0
T2	625136	228004	0	0
T3	6612	144	0	0
T4	2312268	512934	0	0
T5	387708	122316	0	0
T6	0	230	0	0
T7	491752	513252	0	0
T11	15492	340	0	0
T12	4960	584	0	0
T17	6592	478	0	0
T18	27088	6462	0	0
T29	0	52834	0	0
T30	0	410	0	0
T54	0	806	0	0
T60	2118	0	0	0
T61	0	334524	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1556530828	1553273236	0	0
T1	6532	6148	0	0
T2	625136	624764	0	0
T3	6612	5968	0	0
T4	2312268	2311684	0	0
T5	387708	387480	0	0
T7	491752	491704	0	0
T11	15492	12628	0	0
T12	4960	4624	0	0
T17	6592	5988	0	0
T18	27088	26824	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389132707	388318309	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	389132707	104824219	0	0
GntImpliesValid_A	389132707	104824219	0	0
GrantKnown_A	389132707	388318309	0	0
IdxKnown_A	389132707	388318309	0	0
IndexIsCorrect_A	389132707	104824219	0	0
NoReadyValidNoGrant_A	389132707	45672369	0	0
Priority_A	389132707	110862677	0	0
ReadyAndValidImplyGrant_A	389132707	104824219	0	0
ReqAndReadyImplyGrant_A	389132707	104824219	0	0
ReqImpliesValid_A	389132707	110862677	0	0
ValidKnown_A	389132707	388318309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824219	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824219	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824219	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	45672369	0	0
T1	1633	128	0	0
T2	156284	33624	0	0
T3	1653	256	0	0
T4	578067	307183	0	0
T5	96927	1754	0	0
T7	122938	645100	0	0
T11	3873	647	0	0
T12	1240	128	0	0
T17	1648	256	0	0
T18	6772	247	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	110862677	0	0
T1	1633	32	0	0
T2	156284	81447	0	0
T3	1653	72	0	0
T4	578067	152794	0	0
T5	96927	27675	0	0
T7	122938	121221	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1635	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824219	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824219	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	110862677	0	0
T1	1633	32	0	0
T2	156284	81447	0	0
T3	1653	72	0	0
T4	578067	152794	0	0
T5	96927	27675	0	0
T7	122938	121221	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1635	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389132707	388318309	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	389132707	104824151	0	0
GntImpliesValid_A	389132707	104824151	0	0
GrantKnown_A	389132707	388318309	0	0
IdxKnown_A	389132707	388318309	0	0
IndexIsCorrect_A	389132707	104824151	0	0
NoReadyValidNoGrant_A	389132707	45672369	0	0
Priority_A	389132707	110862609	0	0
ReadyAndValidImplyGrant_A	389132707	104824151	0	0
ReqAndReadyImplyGrant_A	389132707	104824151	0	0
ReqImpliesValid_A	389132707	110862609	0	0
ValidKnown_A	389132707	388318309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824151	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824151	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824151	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	45672369	0	0
T1	1633	128	0	0
T2	156284	33624	0	0
T3	1653	256	0	0
T4	578067	307183	0	0
T5	96927	1754	0	0
T7	122938	645100	0	0
T11	3873	647	0	0
T12	1240	128	0	0
T17	1648	256	0	0
T18	6772	247	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	110862609	0	0
T1	1633	32	0	0
T2	156284	81447	0	0
T3	1653	72	0	0
T4	578067	152794	0	0
T5	96927	27675	0	0
T7	122938	121221	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1635	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824151	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	104824151	0	0
T1	1633	32	0	0
T2	156284	67200	0	0
T3	1653	72	0	0
T4	578067	8921	0	0
T5	96927	27675	0	0
T7	122938	20323	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1616	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	110862609	0	0
T1	1633	32	0	0
T2	156284	81447	0	0
T3	1653	72	0	0
T4	578067	152794	0	0
T5	96927	27675	0	0
T7	122938	121221	0	0
T11	3873	170	0	0
T12	1240	292	0	0
T17	1648	239	0	0
T18	6772	1635	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T5
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T7,T5
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T7,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389132707	388318309	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	389132707	102129925	0	0
GntImpliesValid_A	389132707	102129925	0	0
GrantKnown_A	389132707	388318309	0	0
IdxKnown_A	389132707	388318309	0	0
IndexIsCorrect_A	389132707	102129925	0	0
NoReadyValidNoGrant_A	389132707	42911222	0	0
Priority_A	389132707	107974780	0	0
ReadyAndValidImplyGrant_A	389132707	102129925	0	0
ReqAndReadyImplyGrant_A	389132707	102129925	0	0
ReqImpliesValid_A	389132707	107974780	0	0
ValidKnown_A	389132707	388318309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129925	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129925	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129925	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	42911222	0	0
T2	156284	25153	0	0
T3	1653	0	0	0
T4	578067	296911	0	0
T5	96927	1956	0	0
T6	0	13	0	0
T7	122938	719258	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	342	0	0
T29	0	1554	0	0
T30	0	39	0	0
T54	0	596	0	0
T60	1059	0	0	0
T61	0	54299	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	107974780	0	0
T2	156284	32555	0	0
T3	1653	0	0	0
T4	578067	103673	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	135405	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1596	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	403	0	0
T60	1059	0	0	0
T61	0	167262	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129925	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129925	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	107974780	0	0
T2	156284	32555	0	0
T3	1653	0	0	0
T4	578067	103673	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	135405	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1596	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	403	0	0
T60	1059	0	0	0
T61	0	167262	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T5
1	0	Covered	T2,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T7,T5
1	1	Covered	T2,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T7,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389132707	388318309	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	389132707	102129905	0	0
GntImpliesValid_A	389132707	102129905	0	0
GrantKnown_A	389132707	388318309	0	0
IdxKnown_A	389132707	388318309	0	0
IndexIsCorrect_A	389132707	102129905	0	0
NoReadyValidNoGrant_A	389132707	42911191	0	0
Priority_A	389132707	107974791	0	0
ReadyAndValidImplyGrant_A	389132707	102129905	0	0
ReqAndReadyImplyGrant_A	389132707	102129905	0	0
ReqImpliesValid_A	389132707	107974791	0	0
ValidKnown_A	389132707	388318309	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129905	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129905	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129905	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	42911191	0	0
T2	156284	25153	0	0
T3	1653	0	0	0
T4	578067	296911	0	0
T5	96927	1956	0	0
T6	0	13	0	0
T7	122938	719258	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	342	0	0
T29	0	1554	0	0
T30	0	39	0	0
T54	0	596	0	0
T60	1059	0	0	0
T61	0	54299	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	107974791	0	0
T2	156284	32555	0	0
T3	1653	0	0	0
T4	578067	103673	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	135405	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1596	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	403	0	0
T60	1059	0	0	0
T61	0	167262	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129905	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	102129905	0	0
T2	156284	30275	0	0
T3	1653	0	0	0
T4	578067	7765	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	23289	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1532	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	401	0	0
T60	1059	0	0	0
T61	0	135248	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	107974791	0	0
T2	156284	32555	0	0
T3	1653	0	0	0
T4	578067	103673	0	0
T5	96927	33483	0	0
T6	0	115	0	0
T7	122938	135405	0	0
T11	3873	0	0	0
T12	1240	0	0	0
T17	1648	0	0	0
T18	6772	1596	0	0
T29	0	26417	0	0
T30	0	205	0	0
T54	0	403	0	0
T60	1059	0	0	0
T61	0	167262	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389132707	388318309	0	0
T1	1633	1537	0	0
T2	156284	156191	0	0
T3	1653	1492	0	0
T4	578067	577921	0	0
T5	96927	96870	0	0
T7	122938	122926	0	0
T11	3873	3157	0	0
T12	1240	1156	0	0
T17	1648	1497	0	0
T18	6772	6706	0	0