Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.07 100.00 72.29 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_sramreqfifo 62.12 78.57 38.46 71.43 60.00
tb.dut.u_to_prog_fifo.u_rspfifo 71.27 92.31 47.06 85.71 60.00
tb.dut.u_to_rd_fifo.u_sramreqfifo 90.62 100.00 62.50 100.00 100.00
tb.dut.u_to_prog_fifo.u_reqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_to_rd_fifo.u_reqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.u_bank_sequence_fifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo 93.75 100.00 75.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo 93.75 100.00 75.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo 93.75 100.00 75.00 100.00 100.00
tb.dut.u_sw_rd_fifo 94.79 100.00 79.17 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo 94.79 100.00 79.17 100.00 100.00
tb.dut.u_prog_fifo 95.83 100.00 83.33 100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo 95.83 100.00 83.33 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo 95.83 100.00 83.33 100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_to_prog_fifo.u_reqfifo

SCORELINE
92.19 100.00
tb.dut.u_to_rd_fifo.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
62.12 78.57
tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORELINE
90.62 100.00
tb.dut.u_to_rd_fifo.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
71.27 92.31
tb.dut.u_to_prog_fifo.u_rspfifo

SCORELINE
95.83 100.00
tb.dut.u_to_rd_fifo.u_rspfifo

SCORELINE
95.83 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORELINE
93.75 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PtrW=4 )
Line Coverage for Module self-instances :
SCORELINE
95.83 100.00
tb.dut.u_prog_fifo

SCORELINE
94.79 100.00
tb.dut.u_sw_rd_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
94.79 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.u_bank_sequence_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=76,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=16,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORELINE
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (6'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
93.75 75.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORECOND
93.75 75.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

TotalCoveredPercent
Conditions161275.00
Logical161275.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T17,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T17,T5
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T11,T17
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (101'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT2,T4,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (64'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
62.12 38.46
tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCORECOND
90.62 62.50
tb.dut.u_to_rd_fifo.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T7
110Not Covered
111CoveredT2,T4,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T4,T7
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=16,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (16'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.u_bank_sequence_fifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T7
110Not Covered
111CoveredT2,T4,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (1'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T4,T7
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PtrW=4 )
Cond Coverage for Module self-instances :
SCORECOND
95.83 83.33
tb.dut.u_prog_fifo

SCORECOND
94.79 79.17
tb.dut.u_sw_rd_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T17,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT18,T46,T47
110Not Covered
111CoveredT2,T3,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T17
110Not Covered
111CoveredT2,T3,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT2,T17,T7
10CoveredT1,T2,T3
11CoveredT2,T3,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T3,T17
10CoveredT2,T3,T17
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (39'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T17
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=76,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT15,T66,T67
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (76'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
71.27 47.06
tb.dut.u_to_prog_fifo.u_rspfifo

SCORECOND
94.79 79.17
tb.dut.u_tl_adapter_eflash.u_rspfifo

SCORECOND
95.83 83.33
tb.dut.u_to_rd_fifo.u_rspfifo

SCORECOND
95.83 83.33
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORECOND
93.75 75.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T61,T48
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT15,T66,T68
110Not Covered
111CoveredT2,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T5,T6
110Not Covered
111CoveredT2,T4,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT55,T15,T66
10CoveredT1,T2,T3
11CoveredT2,T4,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T49,T19
10CoveredT2,T4,T7
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T4,T7
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_to_prog_fifo.u_reqfifo

SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORECOND
92.19 68.75
tb.dut.u_to_rd_fifo.u_reqfifo

SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T7
110Not Covered
111CoveredT2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PtrW=4 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
71.27 85.71
tb.dut.u_to_prog_fifo.u_rspfifo

SCOREBRANCH
95.83 100.00
tb.dut.u_prog_fifo

SCOREBRANCH
94.79 100.00
tb.dut.u_sw_rd_fifo

SCOREBRANCH
94.79 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo

SCOREBRANCH
95.83 100.00
tb.dut.u_to_rd_fifo.u_rspfifo

SCOREBRANCH
95.83 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCOREBRANCH
93.75 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=76,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=16,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
92.19 100.00
tb.dut.u_to_prog_fifo.u_reqfifo

SCOREBRANCH
62.12 71.43
tb.dut.u_to_prog_fifo.u_sramreqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.u_bank_sequence_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

SCOREBRANCH
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCOREBRANCH
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_to_rd_fifo.u_reqfifo

SCOREBRANCH
90.62 100.00
tb.dut.u_to_rd_fifo.u_sramreqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 959044430 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 794689134 0 0
gen_passthru_fifo.paramCheckPass 10208 10208 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 959044430 0 0
T1 14697 384 0 0
T2 4844804 208002 0 0
T3 51243 768 0 0
T4 17920077 1325515 0 0
T5 3004737 6134 0 0
T6 0 13 0 0
T7 3811078 2357409 0 0
T11 120063 1940 0 0
T12 38440 384 0 0
T13 0 26 0 0
T17 51088 768 0 0
T18 209932 1148 0 0
T20 0 74052 0 0
T29 0 1554 0 0
T30 0 58 0 0
T32 0 25208 0 0
T36 0 81 0 0
T48 0 21619 0 0
T54 0 799 0 0
T60 23298 9 0 0
T61 0 194555 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 53889 50721 0 0
T2 5157372 5154303 0 0
T3 54549 49236 0 0
T4 19076211 19071393 0 0
T5 3198591 3196710 0 0
T7 4056954 4056558 0 0
T11 127809 104181 0 0
T12 40920 38148 0 0
T17 54384 49401 0 0
T18 223476 221298 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 53889 50721 0 0
T2 5157372 5154303 0 0
T3 54549 49236 0 0
T4 19076211 19071393 0 0
T5 3198591 3196710 0 0
T7 4056954 4056558 0 0
T11 127809 104181 0 0
T12 40920 38148 0 0
T17 54384 49401 0 0
T18 223476 221298 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 53889 50721 0 0
T2 5157372 5154303 0 0
T3 54549 49236 0 0
T4 19076211 19071393 0 0
T5 3198591 3196710 0 0
T7 4056954 4056558 0 0
T11 127809 104181 0 0
T12 40920 38148 0 0
T17 54384 49401 0 0
T18 223476 221298 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 794689134 0 0
T1 8165 384 0 0
T2 3594532 208002 0 0
T3 38019 768 0 0
T4 13295541 1325515 0 0
T5 2229321 6134 0 0
T6 0 13 0 0
T7 2827574 2357409 0 0
T11 89079 1940 0 0
T12 28520 384 0 0
T13 0 26 0 0
T17 37904 768 0 0
T18 155756 1148 0 0
T20 0 74052 0 0
T29 0 1554 0 0
T30 0 58 0 0
T32 0 25208 0 0
T36 0 81 0 0
T48 0 21619 0 0
T54 0 799 0 0
T60 19062 9 0 0
T61 0 194555 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 10208 10208 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T4 8 8 0 0
T5 8 8 0 0
T7 8 8 0 0
T11 8 8 0 0
T12 8 8 0 0
T17 8 8 0 0
T18 8 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%