Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23233815	1		T1	10221		T2	67		T3	24
full_word	7573823	1		T1	12360		T2	43		T21	62

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30807318	1		T1	22581		T2	110		T3	24
auto[TlIntgErrCmd]	99	1		T74	4		T206	6		T209	4
auto[TlIntgErrData]	97	1		T74	8		T206	2		T209	7
auto[TlIntgErrBoth]	124	1		T74	8		T206	2		T209	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26372077	1		T1	18854		T2	60		T3	23
auto[1]	4435561	1		T1	3727		T2	50		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22548990	1		T1	10031		T2	60		T3	23
auto[TlIntgErrNone]	partial	auto[1]	684533	1		T1	190		T2	7		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	3822950	1		T1	8823		T4	16		T22	1
auto[TlIntgErrNone]	full_word	auto[1]	3750845	1		T1	3537		T2	43		T21	62
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T206	4		T209	1		T227	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T74	4		T206	2		T209	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1		T209	1		T280	1		T281	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T281	1		T287	1		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1		T74	3		T206	2		T209	3
auto[TlIntgErrData]	partial	auto[1]	47	1		T74	5		T209	4		T227	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T287	1		T365	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T283	1		T361	2		T360	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T74	2		T206	2		T209	3
auto[TlIntgErrBoth]	partial	auto[1]	74	1		T74	6		T209	6		T227	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T283	2		T288	2		T258	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T281	1		T288	1		T258	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18826	1		T74	17		T75	55		T118	181
full_word	3828348	1		T7	9062		T26	11		T27	13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3846878	1		T7	9062		T26	11		T27	13
auto[TlIntgErrCmd]	101	1		T74	5		T206	3		T209	6
auto[TlIntgErrData]	95	1		T74	6		T206	4		T209	9
auto[TlIntgErrBoth]	100	1		T74	7		T206	1		T209	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3824500	1		T7	9062		T26	11		T27	13
auto[1]	22674	1		T74	12		T75	70		T118	207

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1321	1		T75	2		T118	22		T205	9
auto[TlIntgErrNone]	partial	auto[1]	17225	1		T75	53		T118	159		T205	92
auto[TlIntgErrNone]	full_word	auto[0]	3823072	1		T7	9062		T26	11		T27	13
auto[TlIntgErrNone]	full_word	auto[1]	5260	1		T75	17		T118	48		T205	49
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T74	1		T206	2		T209	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1		T74	4		T206	1		T209	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T281	1		T287	1		T288	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T280	1		T281	1		T360	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T74	2		T209	3		T278	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T74	3		T206	4		T209	6
auto[TlIntgErrData]	full_word	auto[0]	3	1		T74	1		T278	1		T280	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T281	1		T361	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T74	2		T206	1		T227	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T74	5		T209	4		T227	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T366	1		T367	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T209	1		T365	1		-	-