Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1485675920	1482546456	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1485675920	400655020	0	0
GntImpliesValid_A	1485675920	400655020	0	0
GrantKnown_A	1485675920	1482546456	0	0
IdxKnown_A	1485675920	1482546456	0	0
IndexIsCorrect_A	1485675920	400655020	0	0
NoReadyValidNoGrant_A	1485675920	174402113	0	0
Priority_A	1485675920	424777513	0	0
ReadyAndValidImplyGrant_A	1485675920	400655020	0	0
ReqAndReadyImplyGrant_A	1485675920	400655020	0	0
ReqImpliesValid_A	1485675920	424777513	0	0
ValidKnown_A	1485675920	1482546456	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	1482546456	0	0
T1	653496	653280	0	0
T2	6240	5620	0	0
T3	6040	5820	0	0
T4	7148	6856	0	0
T7	664300	663952	0	0
T20	4576	4332	0	0
T21	11196	10836	0	0
T22	522532	521912	0	0
T23	5704	5336	0	0
T24	4644	3740	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T7	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0
T24	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	400655020	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	197930	0	0
T8	0	20062	0	0
T9	0	37492	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3514	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	400655020	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	197930	0	0
T8	0	20062	0	0
T9	0	37492	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3514	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	1482546456	0	0
T1	653496	653280	0	0
T2	6240	5620	0	0
T3	6040	5820	0	0
T4	7148	6856	0	0
T7	664300	663952	0	0
T20	4576	4332	0	0
T21	11196	10836	0	0
T22	522532	521912	0	0
T23	5704	5336	0	0
T24	4644	3740	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	1482546456	0	0
T1	653496	653280	0	0
T2	6240	5620	0	0
T3	6040	5820	0	0
T4	7148	6856	0	0
T7	664300	663952	0	0
T20	4576	4332	0	0
T21	11196	10836	0	0
T22	522532	521912	0	0
T23	5704	5336	0	0
T24	4644	3740	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	400655020	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	197930	0	0
T8	0	20062	0	0
T9	0	37492	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3514	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	174402113	0	0
T1	326748	2688	0	0
T2	3120	512	0	0
T3	3020	256	0	0
T4	7148	300	0	0
T7	664300	133554	0	0
T8	0	57978	0	0
T9	0	101876	0	0
T20	2288	256	0	0
T21	5598	256	0	0
T22	522532	98784	0	0
T23	5704	256	0	0
T24	4644	522	0	0
T26	4068	86	0	0
T27	0	256	0	0
T28	0	304	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	3054	0	0
T67	0	3612	0	0
T68	0	84736	0	0
T69	7102	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	424777513	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	233702	0	0
T8	0	22094	0	0
T9	0	39634	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3516	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	400655020	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	197930	0	0
T8	0	20062	0	0
T9	0	37492	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3514	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	400655020	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	197930	0	0
T8	0	20062	0	0
T9	0	37492	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3514	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	424777513	0	0
T1	326748	28790	0	0
T2	3120	140	0	0
T3	3020	64	0	0
T4	7148	1164	0	0
T5	0	20172	0	0
T7	664300	233702	0	0
T8	0	22094	0	0
T9	0	39634	0	0
T20	2288	64	0	0
T21	5598	64	0	0
T22	522532	74952	0	0
T23	5704	64	0	0
T24	4644	132	0	0
T26	4068	158	0	0
T27	0	1676	0	0
T28	0	3516	0	0
T48	1353298	0	0	0
T57	6658	0	0	0
T65	5226	0	0	0
T66	0	32130	0	0
T67	0	60886	0	0
T69	7102	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1485675920	1482546456	0	0
T1	653496	653280	0	0
T2	6240	5620	0	0
T3	6040	5820	0	0
T4	7148	6856	0	0
T7	664300	663952	0	0
T20	4576	4332	0	0
T21	11196	10836	0	0
T22	522532	521912	0	0
T23	5704	5336	0	0
T24	4644	3740	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371418980	370636614	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	371418980	104567898	0	0
GntImpliesValid_A	371418980	104567898	0	0
GrantKnown_A	371418980	370636614	0	0
IdxKnown_A	371418980	370636614	0	0
IndexIsCorrect_A	371418980	104567898	0	0
NoReadyValidNoGrant_A	371418980	45329026	0	0
Priority_A	371418980	110658764	0	0
ReadyAndValidImplyGrant_A	371418980	104567898	0	0
ReqAndReadyImplyGrant_A	371418980	104567898	0	0
ReqImpliesValid_A	371418980	110658764	0	0
ValidKnown_A	371418980	370636614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567898	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567898	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567898	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	45329026	0	0
T1	163374	1344	0	0
T2	1560	256	0	0
T3	1510	128	0	0
T4	1787	128	0	0
T7	166075	34245	0	0
T20	1144	128	0	0
T21	2799	128	0	0
T22	130633	49392	0	0
T23	1426	128	0	0
T24	1161	261	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	110658764	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	51198	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567898	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567898	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	110658764	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	51198	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371418980	370636614	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	371418980	104567833	0	0
GntImpliesValid_A	371418980	104567833	0	0
GrantKnown_A	371418980	370636614	0	0
IdxKnown_A	371418980	370636614	0	0
IndexIsCorrect_A	371418980	104567833	0	0
NoReadyValidNoGrant_A	371418980	45329026	0	0
Priority_A	371418980	110658699	0	0
ReadyAndValidImplyGrant_A	371418980	104567833	0	0
ReqAndReadyImplyGrant_A	371418980	104567833	0	0
ReqImpliesValid_A	371418980	110658699	0	0
ValidKnown_A	371418980	370636614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567833	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567833	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567833	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	45329026	0	0
T1	163374	1344	0	0
T2	1560	256	0	0
T3	1510	128	0	0
T4	1787	128	0	0
T7	166075	34245	0	0
T20	1144	128	0	0
T21	2799	128	0	0
T22	130633	49392	0	0
T23	1426	128	0	0
T24	1161	261	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	110658699	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	51198	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567833	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	104567833	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	43936	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	110658699	0	0
T1	163374	14395	0	0
T2	1560	70	0	0
T3	1510	32	0	0
T4	1787	308	0	0
T7	166075	51198	0	0
T20	1144	32	0	0
T21	2799	32	0	0
T22	130633	37476	0	0
T23	1426	32	0	0
T24	1161	66	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T26
1	0	Covered	T7,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T27
1	0	Covered	T4,T7,T26
1	1	Covered	T7,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T4,T7,T26

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T4,T7,T26

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371418980	370636614	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	371418980	95759614	0	0
GntImpliesValid_A	371418980	95759614	0	0
GrantKnown_A	371418980	370636614	0	0
IdxKnown_A	371418980	370636614	0	0
IndexIsCorrect_A	371418980	95759614	0	0
NoReadyValidNoGrant_A	371418980	41872036	0	0
Priority_A	371418980	101729989	0	0
ReadyAndValidImplyGrant_A	371418980	95759614	0	0
ReqAndReadyImplyGrant_A	371418980	95759614	0	0
ReqImpliesValid_A	371418980	101729989	0	0
ValidKnown_A	371418980	370636614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759614	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759614	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759614	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	41872036	0	0
T4	1787	22	0	0
T7	166075	32532	0	0
T8	0	28989	0	0
T9	0	50938	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	43	0	0
T27	0	128	0	0
T28	0	152	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	1527	0	0
T67	0	1806	0	0
T68	0	42368	0	0
T69	3551	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	101729989	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	65653	0	0
T8	0	11047	0	0
T9	0	19817	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1758	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759614	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759614	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	101729989	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	65653	0	0
T8	0	11047	0	0
T9	0	19817	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1758	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T26
1	0	Covered	T7,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T27
1	0	Covered	T4,T7,T26
1	1	Covered	T7,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T4,T7,T26

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T26,T27
1	1	Covered	T4,T7,T26

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T26,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	371418980	370636614	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	371418980	95759675	0	0
GntImpliesValid_A	371418980	95759675	0	0
GrantKnown_A	371418980	370636614	0	0
IdxKnown_A	371418980	370636614	0	0
IndexIsCorrect_A	371418980	95759675	0	0
NoReadyValidNoGrant_A	371418980	41872025	0	0
Priority_A	371418980	101730061	0	0
ReadyAndValidImplyGrant_A	371418980	95759675	0	0
ReqAndReadyImplyGrant_A	371418980	95759675	0	0
ReqImpliesValid_A	371418980	101730061	0	0
ValidKnown_A	371418980	370636614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759675	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759675	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759675	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	41872025	0	0
T4	1787	22	0	0
T7	166075	32532	0	0
T8	0	28989	0	0
T9	0	50938	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	43	0	0
T27	0	128	0	0
T28	0	152	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	1527	0	0
T67	0	1806	0	0
T68	0	42368	0	0
T69	3551	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	101730061	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	65653	0	0
T8	0	11047	0	0
T9	0	19817	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1758	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759675	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	95759675	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	55029	0	0
T8	0	10031	0	0
T9	0	18746	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1757	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	101730061	0	0
T4	1787	274	0	0
T5	0	10086	0	0
T7	166075	65653	0	0
T8	0	11047	0	0
T9	0	19817	0	0
T22	130633	0	0	0
T23	1426	0	0	0
T24	1161	0	0	0
T26	2034	79	0	0
T27	0	838	0	0
T28	0	1758	0	0
T48	676649	0	0	0
T57	3329	0	0	0
T65	2613	0	0	0
T66	0	16065	0	0
T67	0	30443	0	0
T69	3551	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371418980	370636614	0	0
T1	163374	163320	0	0
T2	1560	1405	0	0
T3	1510	1455	0	0
T4	1787	1714	0	0
T7	166075	165988	0	0
T20	1144	1083	0	0
T21	2799	2709	0	0
T22	130633	130478	0	0
T23	1426	1334	0	0
T24	1161	935	0	0