SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 30745244 | 1 | T1 | 114 | T2 | 15 | T3 | 91550 | |||
auto[1] | 5314432 | 1 | T3 | 6852 | T4 | 539 | T5 | 57 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36059458 | 1 | T1 | 114 | T2 | 15 | T3 | 98402 | |||
values[1] | 30 | 1 | T104 | 1 | T106 | 3 | T231 | 3 | |||
values[2] | 7 | 1 | T231 | 1 | T272 | 2 | T274 | 3 | |||
values[3] | 104 | 1 | T67 | 3 | T104 | 8 | T106 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36059462 | 1 | T1 | 114 | T2 | 15 | T3 | 98402 | |||
values[1] | 25 | 1 | T67 | 1 | T231 | 1 | T235 | 1 | |||
values[2] | 4 | 1 | T231 | 1 | T272 | 1 | T275 | 1 | |||
values[3] | 105 | 1 | T67 | 3 | T104 | 8 | T106 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 36059356 | 1 | T1 | 114 | T2 | 15 | T3 | 98402 | |||
auto[TlIntgErrCmd] | 106 | 1 | T67 | 2 | T104 | 8 | T106 | 10 | |||
auto[TlIntgErrData] | 102 | 1 | T67 | 5 | T104 | 4 | T106 | 5 | |||
auto[TlIntgErrBoth] | 112 | 1 | T67 | 3 | T104 | 8 | T106 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 3793564 | 0 | T1 | 7 | T4 | 251 | T5 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3793379 | 1 | T1 | 7 | T4 | 251 | T5 | 40 | |||
values[1] | 18 | 1 | T104 | 3 | T231 | 1 | T235 | 3 | |||
values[2] | 4 | 1 | T231 | 1 | T354 | 1 | T355 | 2 | |||
values[3] | 96 | 1 | T67 | 4 | T104 | 4 | T106 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3793348 | 1 | T1 | 7 | T4 | 251 | T5 | 40 | |||
values[1] | 29 | 1 | T104 | 1 | T106 | 1 | T231 | 3 | |||
values[2] | 6 | 1 | T67 | 1 | T231 | 1 | T274 | 1 | |||
values[3] | 106 | 1 | T67 | 4 | T104 | 6 | T106 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3793262 | 1 | T1 | 7 | T4 | 251 | T5 | 40 | |||
auto[TlIntgErrCmd] | 86 | 1 | T67 | 4 | T104 | 5 | T106 | 6 | |||
auto[TlIntgErrData] | 117 | 1 | T67 | 4 | T104 | 8 | T106 | 8 | |||
auto[TlIntgErrBoth] | 99 | 1 | T67 | 2 | T104 | 5 | T106 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 83068 | 0 | T66 | 42 | T67 | 640 | T103 | 91 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82846 | 1 | T66 | 42 | T67 | 634 | T103 | 91 | |||
values[1] | 29 | 1 | T67 | 1 | T104 | 4 | T106 | 1 | |||
values[2] | 4 | 1 | T104 | 1 | T106 | 1 | T272 | 1 | |||
values[3] | 123 | 1 | T67 | 4 | T104 | 6 | T106 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 82868 | 1 | T66 | 42 | T67 | 634 | T103 | 91 | |||
values[1] | 17 | 1 | T67 | 1 | T104 | 2 | T106 | 2 | |||
values[2] | 3 | 1 | T106 | 1 | T275 | 1 | T356 | 1 | |||
values[3] | 104 | 1 | T67 | 2 | T104 | 7 | T106 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 82748 | 1 | T66 | 42 | T67 | 630 | T103 | 91 | |||
auto[TlIntgErrCmd] | 120 | 1 | T67 | 4 | T104 | 8 | T106 | 8 | |||
auto[TlIntgErrData] | 98 | 1 | T67 | 4 | T104 | 7 | T106 | 4 | |||
auto[TlIntgErrBoth] | 102 | 1 | T67 | 2 | T104 | 5 | T106 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |