Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	28087652	1		T1	71		T2	14		T3	87714
full_word	7972024	1		T1	43		T2	1		T3	10688

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36059356	1		T1	114		T2	15		T3	98402
auto[TlIntgErrCmd]	106	1		T67	2		T104	8		T106	10
auto[TlIntgErrData]	102	1		T67	5		T104	4		T106	5
auto[TlIntgErrBoth]	112	1		T67	3		T104	8		T106	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31473784	1		T1	68		T2	14		T3	87310
auto[1]	4585892	1		T1	46		T2	1		T3	11092

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27338869	1		T1	64		T2	13		T3	86621
auto[TlIntgErrNone]	partial	auto[1]	748494	1		T1	7		T2	1		T3	1093
auto[TlIntgErrNone]	full_word	auto[0]	4134756	1		T1	4		T2	1		T3	689
auto[TlIntgErrNone]	full_word	auto[1]	3837237	1		T1	39		T3	9999		T4	1938
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T67	1		T104	4		T106	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T67	1		T104	3		T106	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T106	1		T274	1		T256	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T104	1		T274	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	63	1		T67	5		T104	2		T106	4
auto[TlIntgErrData]	partial	auto[1]	31	1		T104	2		T106	1		T231	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T274	1		T358	1		T355	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T256	1		T359	1		T354	2
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T67	1		T104	2		T106	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T67	2		T104	4		T106	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T104	1		T272	1		T354	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T104	1		T235	1		T274	3

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19385	1		T67	10		T103	8		T104	17
full_word	3774179	1		T1	7		T4	251		T5	40

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3793262	1		T1	7		T4	251		T5	40
auto[TlIntgErrCmd]	86	1		T67	4		T104	5		T106	6
auto[TlIntgErrData]	117	1		T67	4		T104	8		T106	8
auto[TlIntgErrBoth]	99	1		T67	2		T104	5		T106	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3769040	1		T1	7		T4	251		T5	40
auto[1]	24524	1		T67	6		T103	10		T104	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1314	1		T220	80		T221	19		T230	32
auto[TlIntgErrNone]	partial	auto[1]	17786	1		T103	8		T220	814		T221	466
auto[TlIntgErrNone]	full_word	auto[0]	3767606	1		T1	7		T4	251		T5	40
auto[TlIntgErrNone]	full_word	auto[1]	6556	1		T103	2		T220	134		T221	86
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T67	2		T104	4		T106	4
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T67	2		T104	1		T106	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T272	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T359	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1		T67	1		T106	4		T231	3
auto[TlIntgErrData]	partial	auto[1]	63	1		T67	3		T104	7		T106	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T357	1		T358	1		T266	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T104	1		T274	1		T360	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T67	1		T106	2		T231	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T67	1		T104	5		T106	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T235	1		T357	1		T359	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T106	1		T231	1		T274	1