SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 74 | 1 | T30 | 1 | T31 | 1 | T42 | 1 | |||
others[1] | 90 | 1 | T31 | 3 | T42 | 3 | T229 | 3 | |||
others[2] | 76 | 1 | T30 | 2 | T31 | 1 | T196 | 3 | |||
others[3] | 140 | 1 | T30 | 4 | T31 | 3 | T42 | 3 | |||
false | 29504 | 1 | T2 | 1 | T4 | 1 | T5 | 3 | |||
true | 24362 | 1 | T1 | 2 | T3 | 2 | T5 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 3 | 1 | T81 | 1 | T363 | 1 | T364 | 1 | |||
others[1] | 3 | 1 | T365 | 1 | T366 | 1 | T367 | 1 | |||
others[2] | 3 | 1 | T48 | 1 | T368 | 1 | T369 | 1 | |||
others[3] | 8 | 1 | T370 | 1 | T371 | 1 | T372 | 1 | |||
false | 12760 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | |||
true | 8 | 1 | T79 | 1 | T99 | 1 | T100 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2621 | 1 | T30 | 1 | T31 | 1 | T52 | 40 | |||
others[1] | 2629 | 1 | T30 | 2 | T52 | 36 | T42 | 1 | |||
others[2] | 2614 | 1 | T31 | 1 | T52 | 36 | T229 | 1 | |||
others[3] | 4253 | 1 | T31 | 2 | T52 | 67 | T42 | 2 | |||
false | 7364 | 1 | T1 | 1 | T2 | 1 | T4 | 1 | |||
true | 1505 | 1 | T1 | 1 | T3 | 2 | T5 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2531 | 1 | T52 | 49 | T229 | 1 | T97 | 34 | |||
others[1] | 2550 | 1 | T30 | 2 | T52 | 34 | T42 | 1 | |||
others[2] | 2698 | 1 | T30 | 2 | T31 | 1 | T52 | 31 | |||
others[3] | 4336 | 1 | T30 | 3 | T31 | 1 | T52 | 46 | |||
false | 7397 | 1 | T1 | 1 | T2 | 1 | T4 | 1 | |||
true | 1511 | 1 | T1 | 1 | T3 | 2 | T5 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2594 | 1 | T52 | 24 | T97 | 20 | T98 | 77 | |||
others[1] | 2505 | 1 | T52 | 24 | T97 | 36 | T98 | 103 | |||
others[2] | 2589 | 1 | T52 | 49 | T97 | 39 | T98 | 71 | |||
others[3] | 4122 | 1 | T52 | 62 | T97 | 34 | T98 | 98 | |||
false | 7937 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | |||
true | 41 | 1 | T2 | 1 | T17 | 1 | T101 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 79 | 1 | T31 | 2 | T42 | 1 | T229 | 1 | |||
others[1] | 86 | 1 | T30 | 3 | T31 | 2 | T42 | 1 | |||
others[2] | 90 | 1 | T30 | 2 | T31 | 1 | T42 | 4 | |||
others[3] | 144 | 1 | T30 | 3 | T31 | 4 | T42 | 3 | |||
false | 29415 | 1 | T2 | 1 | T4 | 1 | T5 | 3 | |||
true | 24387 | 1 | T1 | 2 | T3 | 2 | T5 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8389 | 1 | T52 | 121 | T97 | 94 | T98 | 234 | |||
others[1] | 8342 | 1 | T52 | 115 | T97 | 101 | T98 | 281 | |||
others[2] | 8444 | 1 | T52 | 115 | T97 | 92 | T98 | 259 | |||
others[3] | 14010 | 1 | T52 | 206 | T97 | 157 | T98 | 421 | |||
false | 4164 | 1 | T52 | 52 | T97 | 43 | T98 | 134 | |||
true | 20377 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |