Module Definition
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Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.96 100.00 65.52 85.71 84.62


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.99 89.66 64.82 80.23 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 79.64 100.00 68.57 50.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 69.33 91.43 57.14 68.75 60.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 72.63 94.44 54.84 81.25 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.89 100.00 75.00 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.03 87.86 75.35 80.00 86.96 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 86.36 100.00 71.79 70.00 90.00 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 98.30 100.00 91.49 100.00 100.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 85.85 100.00 69.23 70.00 90.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.26 100.00 80.47 96.55 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.90 92.89 82.41 97.66 96.55 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
gen_data_xor_addr_fifo.u_sramreqaddrfifo 96.53 100.00 86.11 100.00 100.00
u_err 89.46 100.00 82.86 75.00 100.00
u_reqfifo 94.41 100.00 82.05 90.00 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 95.02 100.00 85.11 90.00 100.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 94.41 100.00 82.05 90.00 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
83.96 100.00
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL6868100.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS27988100.00
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47500
CONT_ASSIGN47700
CONT_ASSIGN47911100.00
CONT_ASSIGN48600
ALWAYS49244100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
CONT_ASSIGN62011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
162 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
446 1 1
447 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 unreachable
477 unreachable
479 1 1
486 unreachable
492 1 1
496 1 1
498 1 1
504 unreachable
510 1 1
MISSING_ELSE
526 1 1
531 1 1
536 unreachable
620 1 1


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
92.89 100.00
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL7272100.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12944100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS27988100.00
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48611100.00
ALWAYS49244100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
CONT_ASSIGN62011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE
138 1 1
144 1 1
151 1 1
156 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
446 1 1
447 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 1 1
477 1 1
479 1 1
486 1 1
492 1 1
496 1 1
498 1 1
504 unreachable
510 1 1
MISSING_ELSE
526 1 1
531 1 1
536 unreachable
620 1 1


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
94.26 100.00
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL7171100.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12944100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS27988100.00
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48611100.00
ALWAYS49244100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE
138 1 1
144 1 1
151 1 1
156 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
446 1 1
447 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 1 1
477 1 1
479 1 1
486 1 1
492 1 1
496 1 1
498 1 1
504 1 1
510 unreachable
MISSING_ELSE
526 1 1
531 1 1
536 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
83.96 65.52
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1167665.52
Logical1167665.52
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT2,T4,T5
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT3,T5,T18
000001Unreachable
000010CoveredT1,T3,T4
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11CoveredT3,T5,T18

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T18,T19
11CoveredT3,T5,T18

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T31,T42
11CoveredT3,T5,T18

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T5,T18
1Not Covered

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T5,T18
1Not Covered

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT3,T5,T18
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T18

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T18
11Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT3,T5,T18
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T5,T18
110Not Covered
111CoveredT3,T5,T18

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T18

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT10
1CoveredT3,T5,T18

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT3,T5,T18

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11Not Covered

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT3,T5,T18
10Unreachable
11Unreachable

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
92.89 75.00
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1249375.00
Logical1249375.00
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100CoveredT15,T16,T43
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT15,T16,T43
00010Not Covered
00100Not Covered
01000CoveredT15,T16,T43
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT2,T4,T5
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T5,T7
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT4,T5,T7
11CoveredT4,T5,T7

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T18
11CoveredT4,T5,T7

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT44,T45,T46
11CoveredT4,T5,T7

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10
1CoveredT4,T5,T7

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10
1CoveredT4,T5,T7

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT4,T5,T7
01Not Covered
10CoveredT47,T48,T49

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT4,T5,T7

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT47,T48,T49
11CoveredT4,T5,T7

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T5,T7
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11CoveredT47,T48,T49

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT4,T50,T19
1101Not Covered
1110Unreachable
1111CoveredT4,T5,T7

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T7

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T7
110Not Covered
111CoveredT4,T5,T7

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT4,T5,T7
1Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T7

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T50,T19
10Not Covered
11CoveredT4,T5,T7

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T7

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
94.26 80.47
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions12810380.47
Logical12810380.47
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT11,T21,T51

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT11,T21,T51
00010Not Covered
00100Not Covered
01000Not Covered
10000CoveredT11,T21,T51

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT3,T5,T6
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T6

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT37,T38,T23
01CoveredT5,T6,T52
10CoveredT5,T6,T12

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT5,T6,T52
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T5
000001Not Covered
000010CoveredT2,T5,T6
000100CoveredT4,T53,T54
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T53,T55
10CoveredT1,T4,T7
11CoveredT1,T4,T5

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT1,T4,T5

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T7
11CoveredT1,T4,T5

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10,T14
1CoveredT1,T4,T5

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10,T11,T51
1CoveredT1,T4,T5

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT4,T53,T54
10CoveredT56,T57,T58

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT4,T53,T54
1110Not Covered
1111CoveredT1,T4,T5

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT56,T57,T58
11CoveredT1,T4,T5

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT4,T53,T54
10CoveredT1,T4,T5
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T7
101CoveredT1,T2,T3
110CoveredT4,T53,T54
111CoveredT4,T53,T54

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T51

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT11,T51

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11CoveredT4,T56,T57

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT54,T59
1101Not Covered
1110Not Covered
1111CoveredT1,T4,T5

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T53,T54
10CoveredT1,T4,T5

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T7,T8
110CoveredT4,T53,T54
111CoveredT1,T4,T5

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10Not Covered
11CoveredT1,T4,T5

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T53,T54
11CoveredT1,T4,T5

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 30 29 96.67
TERNARY 144 2 2 100.00
TERNARY 341 2 2 100.00
TERNARY 347 3 2 66.67
TERNARY 393 2 2 100.00
TERNARY 531 2 2 100.00
IF 129 3 3 100.00
IF 281 4 4 100.00
IF 301 3 3 100.00
IF 362 2 2 100.00
IF 426 2 2 100.00
IF 438 2 2 100.00
IF 496 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 341 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 347 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T16,T10
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 281 if (reqfifo_rvalid) -2-: 282 if (reqfifo_rdata.error) -3-: 285 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T4,T53,T54
1 0 1 Covered T1,T4,T5
1 0 0 Covered T3,T5,T18
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 301 if (reqfifo_rvalid) -2-: 302 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T5
1 0 Covered T3,T5,T18
0 - Covered T1,T2,T3


LineNo. Expression -1-: 362 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 438 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 496 if ((|sramreqfifo_rdata.mask)) -2-: 498 if (DataXorAddr)

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T5
1 0 Covered T4,T5,T7
0 - Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1235042385 1232442090 0 0
DataIntgOptions_A 3123 3123 0 0
ReqOutKnown_A 1235042385 1232442090 0 0
SramDwHasByteGranularity_A 3123 3123 0 0
SramDwIsMultipleOfTlulWidth_A 3123 3123 0 0
TlOutKnownIfFifoKnown_A 1235042385 1232442090 0 0
TlOutValidKnown_A 1235042385 1232442090 0 0
WdataOutKnown_A 1235042385 1232442090 0 0
WeOutKnown_A 1235042385 1232442090 0 0
WmaskOutKnown_A 1235042385 1232442090 0 0
adapterNoReadOrWrite 3123 3123 0 0
rvalidHighReqFifoEmpty 1235042385 7384315 0 0
rvalidHighWhenRspFifoFull 1234398879 7377683 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3123 3123 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T12 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3123 3123 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T12 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3123 3123 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T12 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 1232442090 0 0
T1 3060 2853 0 0
T2 3834 3609 0 0
T3 593409 593208 0 0
T4 106629 106473 0 0
T5 229560 227856 0 0
T6 6231 5889 0 0
T7 440106 439710 0 0
T12 1917 1713 0 0
T17 4233 4041 0 0
T18 292278 292032 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 3123 3123 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T7 3 3 0 0
T12 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1235042385 7384315 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 71086 754 0 0
T5 153040 58 0 0
T6 4154 10 0 0
T7 293404 39352 0 0
T8 0 16400 0 0
T12 1278 19 0 0
T17 2822 0 0 0
T18 194852 2420 0 0
T19 2516 20 0 0
T22 0 46 0 0
T30 0 6656 0 0
T44 139177 166 0 0
T45 0 41 0 0
T46 0 41530 0 0
T50 1729 11 0 0
T60 0 28 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1234398879 7377683 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 71086 754 0 0
T5 153040 58 0 0
T6 4154 10 0 0
T7 293404 39352 0 0
T8 0 16400 0 0
T12 1278 19 0 0
T17 2822 0 0 0
T18 194852 2420 0 0
T19 2516 20 0 0
T22 0 46 0 0
T30 0 6656 0 0
T44 139177 166 0 0
T45 0 41 0 0
T46 0 41530 0 0
T50 1729 11 0 0
T60 0 28 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL6868100.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS27988100.00
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47500
CONT_ASSIGN47700
CONT_ASSIGN47911100.00
CONT_ASSIGN48600
ALWAYS49244100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
CONT_ASSIGN62011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
162 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
446 1 1
447 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 unreachable
477 unreachable
479 1 1
486 unreachable
492 1 1
496 1 1
498 1 1
504 unreachable
510 1 1
MISSING_ELSE
526 1 1
531 1 1
536 unreachable
620 1 1


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1167665.52
Logical1167665.52
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT2,T4,T5
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT3,T5,T18
000001Unreachable
000010CoveredT1,T3,T4
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11CoveredT3,T5,T18

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T18,T19
11CoveredT3,T5,T18

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T31,T42
11CoveredT3,T5,T18

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T5,T18
1Not Covered

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT3,T5,T18
1Not Covered

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT3,T5,T18
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T18

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T18
11Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT3,T5,T18
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T5,T18
110Not Covered
111CoveredT3,T5,T18

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T18

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T18

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT10
1CoveredT3,T5,T18

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT3,T5,T18

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T18
11Not Covered

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT3,T5,T18
10Unreachable
11Unreachable

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 28 24 85.71
TERNARY 144 2 2 100.00
TERNARY 341 2 1 50.00
TERNARY 347 3 1 33.33
TERNARY 393 2 2 100.00
TERNARY 531 2 1 50.00
IF 129 2 2 100.00
IF 281 4 4 100.00
IF 301 3 3 100.00
IF 362 2 2 100.00
IF 426 2 2 100.00
IF 438 2 2 100.00
IF 496 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 341 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 347 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T3,T5,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 281 if (reqfifo_rvalid) -2-: 282 if (reqfifo_rdata.error) -3-: 285 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T10,T14
1 0 1 Covered T10,T14
1 0 0 Covered T3,T5,T18
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 301 if (reqfifo_rvalid) -2-: 302 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T10,T14
1 0 Covered T3,T5,T18
0 - Covered T1,T2,T3


LineNo. Expression -1-: 362 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T5,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 438 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T3,T5,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 496 if ((|sramreqfifo_rdata.mask)) -2-: 498 if (DataXorAddr)

Branches:
-1--2-StatusTests
1 1 Unreachable
1 0 Covered T10,T14
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 11 84.62
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 11 84.62




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 411680795 410814030 0 0
DataIntgOptions_A 1041 1041 0 0
ReqOutKnown_A 411680795 410814030 0 0
SramDwHasByteGranularity_A 1041 1041 0 0
SramDwIsMultipleOfTlulWidth_A 1041 1041 0 0
TlOutKnownIfFifoKnown_A 411680795 410814030 0 0
TlOutValidKnown_A 411680795 410814030 0 0
WdataOutKnown_A 411680795 410814030 0 0
WeOutKnown_A 411680795 410814030 0 0
WmaskOutKnown_A 411680795 410814030 0 0
adapterNoReadOrWrite 1041 1041 0 0
rvalidHighReqFifoEmpty 411680795 0 0 0
rvalidHighWhenRspFifoFull 411680795 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL7272100.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12944100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS27988100.00
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48611100.00
ALWAYS49244100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
CONT_ASSIGN62011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE
138 1 1
144 1 1
151 1 1
156 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
446 1 1
447 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 1 1
477 1 1
479 1 1
486 1 1
492 1 1
496 1 1
498 1 1
504 unreachable
510 1 1
MISSING_ELSE
526 1 1
531 1 1
536 unreachable
620 1 1


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1249375.00
Logical1249375.00
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100CoveredT15,T16,T43
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT15,T16,T43
00010Not Covered
00100Not Covered
01000CoveredT15,T16,T43
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT2,T4,T5
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT4,T5,T7
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT4,T5,T7
11CoveredT4,T5,T7

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T18
11CoveredT4,T5,T7

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT44,T45,T46
11CoveredT4,T5,T7

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10
1CoveredT4,T5,T7

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10
1CoveredT4,T5,T7

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT4,T5,T7
01Not Covered
10CoveredT47,T48,T49

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT4,T5,T7

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT47,T48,T49
11CoveredT4,T5,T7

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT4,T5,T7
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11Not Covered

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11CoveredT47,T48,T49

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT4,T50,T19
1101Not Covered
1110Unreachable
1111CoveredT4,T5,T7

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T7

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T7
110Not Covered
111CoveredT4,T5,T7

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT4,T5,T7
1Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T7
11Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T7

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT4,T50,T19
10Not Covered
11CoveredT4,T5,T7

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T7

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T7

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 144 2 2 100.00
TERNARY 341 2 2 100.00
TERNARY 347 3 2 66.67
TERNARY 393 2 2 100.00
TERNARY 531 2 2 100.00
IF 129 3 3 100.00
IF 281 4 4 100.00
IF 301 3 3 100.00
IF 362 2 2 100.00
IF 426 2 2 100.00
IF 438 2 2 100.00
IF 496 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 341 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 347 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T4,T5,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T15,T16,T10
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 281 if (reqfifo_rvalid) -2-: 282 if (reqfifo_rdata.error) -3-: 285 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T10
1 0 1 Covered T4,T5,T7
1 0 0 Covered T10
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 301 if (reqfifo_rvalid) -2-: 302 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T4,T5,T7
1 0 Covered T10
0 - Covered T1,T2,T3


LineNo. Expression -1-: 362 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 438 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T4,T5,T7
0 Covered T1,T3,T4


LineNo. Expression -1-: 496 if ((|sramreqfifo_rdata.mask)) -2-: 498 if (DataXorAddr)

Branches:
-1--2-StatusTests
1 1 Unreachable
1 0 Covered T4,T5,T7
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 411680795 410814030 0 0
DataIntgOptions_A 1041 1041 0 0
ReqOutKnown_A 411680795 410814030 0 0
SramDwHasByteGranularity_A 1041 1041 0 0
SramDwIsMultipleOfTlulWidth_A 1041 1041 0 0
TlOutKnownIfFifoKnown_A 411680795 410814030 0 0
TlOutValidKnown_A 411680795 410814030 0 0
WdataOutKnown_A 411680795 410814030 0 0
WeOutKnown_A 411680795 410814030 0 0
WmaskOutKnown_A 411680795 410814030 0 0
adapterNoReadOrWrite 1041 1041 0 0
rvalidHighReqFifoEmpty 411680795 3302061 0 0
rvalidHighWhenRspFifoFull 411037289 3295429 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 3302061 0 0
T4 35543 539 0 0
T5 76520 18 0 0
T6 2077 0 0 0
T7 146702 22688 0 0
T12 639 0 0 0
T17 1411 0 0 0
T18 97426 2420 0 0
T19 2516 20 0 0
T22 0 38 0 0
T30 0 6656 0 0
T44 139177 166 0 0
T45 0 41 0 0
T50 1729 11 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 411037289 3295429 0 0
T4 35543 539 0 0
T5 76520 18 0 0
T6 2077 0 0 0
T7 146702 22688 0 0
T12 639 0 0 0
T17 1411 0 0 0
T18 97426 2420 0 0
T19 2516 20 0 0
T22 0 38 0 0
T30 0 6656 0 0
T44 139177 166 0 0
T45 0 41 0 0
T50 1729 11 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL7171100.00
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12944100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS27988100.00
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48611100.00
ALWAYS49244100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE
138 1 1
144 1 1
151 1 1
156 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 1 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
446 1 1
447 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 1 1
477 1 1
479 1 1
486 1 1
492 1 1
496 1 1
498 1 1
504 1 1
510 unreachable
MISSING_ELSE
526 1 1
531 1 1
536 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions12810380.47
Logical12810380.47
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT11,T21,T51

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT11,T21,T51
00010Not Covered
00100Not Covered
01000Not Covered
10000CoveredT11,T21,T51

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT3,T5,T6
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T6

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT37,T38,T23
01CoveredT5,T6,T52
10CoveredT5,T6,T12

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT5,T6,T52
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT2,T5,T6
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T5
000001Not Covered
000010CoveredT2,T5,T6
000100CoveredT4,T53,T54
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT4,T53,T55
10CoveredT1,T4,T7
11CoveredT1,T4,T5

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT1,T4,T5

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T7
11CoveredT1,T4,T5

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10,T14
1CoveredT1,T4,T5

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT10,T11,T51
1CoveredT1,T4,T5

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T4,T5
01CoveredT4,T53,T54
10CoveredT56,T57,T58

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT4,T53,T54
1110Not Covered
1111CoveredT1,T4,T5

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT56,T57,T58
11CoveredT1,T4,T5

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT4,T53,T54
10CoveredT1,T4,T5
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T4,T7
101CoveredT1,T2,T3
110CoveredT4,T53,T54
111CoveredT4,T53,T54

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T51

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT11,T51

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11CoveredT4,T56,T57

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT54,T59
1101Not Covered
1110Not Covered
1111CoveredT1,T4,T5

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T53,T54
10CoveredT1,T4,T5

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T7,T8
110CoveredT4,T53,T54
111CoveredT1,T4,T5

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11Not Covered

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T4,T5
1Not Covered

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T5
11Not Covered

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T5
10Not Covered
11CoveredT1,T4,T5

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T53,T54
11CoveredT1,T4,T5

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 29 28 96.55
TERNARY 144 2 2 100.00
TERNARY 341 2 2 100.00
TERNARY 347 3 2 66.67
TERNARY 393 2 2 100.00
TERNARY 531 2 2 100.00
IF 129 3 3 100.00
IF 281 4 4 100.00
IF 301 3 3 100.00
IF 362 2 2 100.00
IF 426 2 2 100.00
IF 438 2 2 100.00
IF 496 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 341 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 347 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T11,T21
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 281 if (reqfifo_rvalid) -2-: 282 if (reqfifo_rdata.error) -3-: 285 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T4,T53,T54
1 0 1 Covered T1,T4,T5
1 0 0 Covered T10,T14
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 301 if (reqfifo_rvalid) -2-: 302 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T5
1 0 Covered T10,T11,T51
0 - Covered T1,T2,T3


LineNo. Expression -1-: 362 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 438 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 496 if ((|sramreqfifo_rdata.mask)) -2-: 498 if (DataXorAddr)

Branches:
-1--2-StatusTests
1 1 Covered T1,T4,T5
1 0 Unreachable
0 - Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 411680795 410814030 0 0
DataIntgOptions_A 1041 1041 0 0
ReqOutKnown_A 411680795 410814030 0 0
SramDwHasByteGranularity_A 1041 1041 0 0
SramDwIsMultipleOfTlulWidth_A 1041 1041 0 0
TlOutKnownIfFifoKnown_A 411680795 410814030 0 0
TlOutValidKnown_A 411680795 410814030 0 0
WdataOutKnown_A 411680795 410814030 0 0
WeOutKnown_A 411680795 410814030 0 0
WmaskOutKnown_A 411680795 410814030 0 0
adapterNoReadOrWrite 1041 1041 0 0
rvalidHighReqFifoEmpty 411680795 4082254 0 0
rvalidHighWhenRspFifoFull 411680795 4082254 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1041 1041 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T12 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 4082254 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 35543 215 0 0
T5 76520 40 0 0
T6 2077 10 0 0
T7 146702 16664 0 0
T8 0 16400 0 0
T12 639 19 0 0
T17 1411 0 0 0
T18 97426 0 0 0
T22 0 8 0 0
T46 0 41530 0 0
T60 0 28 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 4082254 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 35543 215 0 0
T5 76520 40 0 0
T6 2077 10 0 0
T7 146702 16664 0 0
T8 0 16400 0 0
T12 639 19 0 0
T17 1411 0 0 0
T18 97426 0 0 0
T22 0 8 0 0
T46 0 41530 0 0
T60 0 28 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%