Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.76 100.00 91.05 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T4,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T4,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T4,T5

Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T4,T5
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 823361590 6856455 0 0
BufferDepRsp_A 823361590 821628060 0 0
BufferIncrOverFlow_A 823361590 6856472 0 0
DepBufferRspOrder_A 823361591 16651057 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 823361590 6856455 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 71086 754 0 0
T5 153040 58 0 0
T6 4154 10 0 0
T7 293404 39352 0 0
T8 0 16400 0 0
T12 1278 19 0 0
T17 2822 0 0 0
T18 194852 2420 0 0
T19 2516 20 0 0
T22 0 30 0 0
T44 139177 166 0 0
T45 0 41 0 0
T50 1729 11 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 823361590 821628060 0 0
T1 2040 1902 0 0
T2 2556 2406 0 0
T3 395606 395472 0 0
T4 71086 70982 0 0
T5 153040 151904 0 0
T6 4154 3926 0 0
T7 293404 293140 0 0
T12 1278 1142 0 0
T17 2822 2694 0 0
T18 194852 194688 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 823361590 6856472 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 71086 754 0 0
T5 153040 58 0 0
T6 4154 10 0 0
T7 293404 39352 0 0
T8 0 16400 0 0
T12 1278 19 0 0
T17 2822 0 0 0
T18 194852 2420 0 0
T19 2516 20 0 0
T22 0 30 0 0
T44 139177 166 0 0
T45 0 42 0 0
T50 1729 11 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 823361591 16651057 0 0
T1 2040 39 0 0
T2 2556 32 0 0
T3 395606 32 0 0
T4 71086 786 0 0
T5 153040 314 0 0
T6 4154 74 0 0
T7 293404 39389 0 0
T8 0 8808 0 0
T12 1278 51 0 0
T17 2822 32 0 0
T18 194852 2452 0 0
T22 0 30 0 0
T44 0 88 0 0
T45 0 26 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT4,T5,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T6
110Not Covered
111CoveredT4,T5,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T4,T5,T6
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 411680795 3753088 0 0
BufferDepRsp_A 411680795 410814030 0 0
BufferIncrOverFlow_A 411680795 3753098 0 0
DepBufferRspOrder_A 411680795 8983400 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 3753088 0 0
T4 35543 431 0 0
T5 76520 54 0 0
T6 2077 10 0 0
T7 146702 19891 0 0
T8 0 7592 0 0
T12 639 0 0 0
T17 1411 0 0 0
T18 97426 1312 0 0
T19 2516 20 0 0
T44 139177 78 0 0
T45 0 16 0 0
T50 1729 11 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 3753098 0 0
T4 35543 431 0 0
T5 76520 54 0 0
T6 2077 10 0 0
T7 146702 19891 0 0
T8 0 7592 0 0
T12 639 0 0 0
T17 1411 0 0 0
T18 97426 1312 0 0
T19 2516 20 0 0
T44 139177 78 0 0
T45 0 16 0 0
T50 1729 11 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 8983400 0 0
T1 1020 32 0 0
T2 1278 32 0 0
T3 197803 32 0 0
T4 35543 463 0 0
T5 76520 310 0 0
T6 2077 74 0 0
T7 146702 19928 0 0
T12 639 32 0 0
T17 1411 32 0 0
T18 97426 1344 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT85,T113,T80
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T4,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T4,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T12
11CoveredT1,T4,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T4,T12
10CoveredT1,T2,T3
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T4,T5
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 411680795 3103367 0 0
BufferDepRsp_A 411680795 410814030 0 0
BufferIncrOverFlow_A 411680795 3103374 0 0
DepBufferRspOrder_A 411680796 7667657 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 3103367 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 35543 323 0 0
T5 76520 4 0 0
T6 2077 0 0 0
T7 146702 19461 0 0
T8 0 8808 0 0
T12 639 19 0 0
T17 1411 0 0 0
T18 97426 1108 0 0
T22 0 30 0 0
T44 0 88 0 0
T45 0 25 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 410814030 0 0
T1 1020 951 0 0
T2 1278 1203 0 0
T3 197803 197736 0 0
T4 35543 35491 0 0
T5 76520 75952 0 0
T6 2077 1963 0 0
T7 146702 146570 0 0
T12 639 571 0 0
T17 1411 1347 0 0
T18 97426 97344 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680795 3103374 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 35543 323 0 0
T5 76520 4 0 0
T6 2077 0 0 0
T7 146702 19461 0 0
T8 0 8808 0 0
T12 639 19 0 0
T17 1411 0 0 0
T18 97426 1108 0 0
T22 0 30 0 0
T44 0 88 0 0
T45 0 26 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 411680796 7667657 0 0
T1 1020 7 0 0
T2 1278 0 0 0
T3 197803 0 0 0
T4 35543 323 0 0
T5 76520 4 0 0
T6 2077 0 0 0
T7 146702 19461 0 0
T8 0 8808 0 0
T12 639 19 0 0
T17 1411 0 0 0
T18 97426 1108 0 0
T22 0 30 0 0
T44 0 88 0 0
T45 0 26 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%