Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1646723180	1643256120	0	0
CheckNGreaterZero_A	4164	4164	0	0
GntImpliesReady_A	1646723180	411164354	0	0
GntImpliesValid_A	1646723180	411164354	0	0
GrantKnown_A	1646723180	1643256120	0	0
IdxKnown_A	1646723180	1643256120	0	0
IndexIsCorrect_A	1646723180	411164354	0	0
NoReadyValidNoGrant_A	1646723180	175745332	0	0
Priority_A	1646723180	434942118	0	0
ReadyAndValidImplyGrant_A	1646723180	411164354	0	0
ReqAndReadyImplyGrant_A	1646723180	411164354	0	0
ReqImpliesValid_A	1646723180	434942118	0	0
ValidKnown_A	1646723180	1643256120	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	1643256120	0	0
T1	4080	3804	0	0
T2	5112	4812	0	0
T3	791212	790944	0	0
T4	142172	141964	0	0
T5	306080	303808	0	0
T6	8308	7852	0	0
T7	586808	586280	0	0
T12	2556	2284	0	0
T17	5644	5388	0	0
T18	389704	389376	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4164	4164	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	411164354	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1572	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	78778	0	0
T8	0	17616	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	411164354	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1572	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	78778	0	0
T8	0	17616	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	1643256120	0	0
T1	4080	3804	0	0
T2	5112	4812	0	0
T3	791212	790944	0	0
T4	142172	141964	0	0
T5	306080	303808	0	0
T6	8308	7852	0	0
T7	586808	586280	0	0
T12	2556	2284	0	0
T17	5644	5388	0	0
T18	389704	389376	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	1643256120	0	0
T1	4080	3804	0	0
T2	5112	4812	0	0
T3	791212	790944	0	0
T4	142172	141964	0	0
T5	306080	303808	0	0
T6	8308	7852	0	0
T7	586808	586280	0	0
T12	2556	2284	0	0
T17	5644	5388	0	0
T18	389704	389376	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	411164354	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1572	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	78778	0	0
T8	0	17616	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	175745332	0	0
T1	4080	294	0	0
T2	5112	256	0	0
T3	791212	256	0	0
T4	142172	2528	0	0
T5	306080	2226	0	0
T6	8308	542	0	0
T7	586808	215004	0	0
T8	0	621234	0	0
T12	2556	354	0	0
T17	5644	256	0	0
T18	389704	7516	0	0
T22	0	162	0	0
T44	0	394	0	0
T45	0	102	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	434942118	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1574	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	82502	0	0
T8	0	287060	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	411164354	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1572	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	78778	0	0
T8	0	17616	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	411164354	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1572	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	78778	0	0
T8	0	17616	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	434942118	0	0
T1	4080	78	0	0
T2	5112	64	0	0
T3	791212	347884	0	0
T4	142172	1574	0	0
T5	306080	134570	0	0
T6	8308	148	0	0
T7	586808	82502	0	0
T8	0	287060	0	0
T12	2556	102	0	0
T17	5644	64	0	0
T18	389704	123244	0	0
T44	0	135376	0	0
T45	0	20546	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646723180	1643256120	0	0
T1	4080	3804	0	0
T2	5112	4812	0	0
T3	791212	790944	0	0
T4	142172	141964	0	0
T5	306080	303808	0	0
T6	8308	7852	0	0
T7	586808	586280	0	0
T12	2556	2284	0	0
T17	5644	5388	0	0
T18	389704	389376	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411680795	410814030	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	411680795	109915397	0	0
GntImpliesValid_A	411680795	109915397	0	0
GrantKnown_A	411680795	410814030	0	0
IdxKnown_A	411680795	410814030	0	0
IndexIsCorrect_A	411680795	109915397	0	0
NoReadyValidNoGrant_A	411680795	45758028	0	0
Priority_A	411680795	115827263	0	0
ReadyAndValidImplyGrant_A	411680795	109915397	0	0
ReqAndReadyImplyGrant_A	411680795	109915397	0	0
ReqImpliesValid_A	411680795	115827263	0	0
ValidKnown_A	411680795	410814030	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	45758028	0	0
T1	1020	128	0	0
T2	1278	128	0	0
T3	197803	128	0	0
T4	35543	777	0	0
T5	76520	1106	0	0
T6	2077	271	0	0
T7	146702	54682	0	0
T12	639	128	0	0
T17	1411	128	0	0
T18	97426	2096	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	115827263	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	464	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	20733	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	115827263	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	464	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	20733	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411680795	410814030	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	411680795	109915397	0	0
GntImpliesValid_A	411680795	109915397	0	0
GrantKnown_A	411680795	410814030	0	0
IdxKnown_A	411680795	410814030	0	0
IndexIsCorrect_A	411680795	109915397	0	0
NoReadyValidNoGrant_A	411680795	45758028	0	0
Priority_A	411680795	115827263	0	0
ReadyAndValidImplyGrant_A	411680795	109915397	0	0
ReqAndReadyImplyGrant_A	411680795	109915397	0	0
ReqImpliesValid_A	411680795	115827263	0	0
ValidKnown_A	411680795	410814030	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	45758028	0	0
T1	1020	128	0	0
T2	1278	128	0	0
T3	197803	128	0	0
T4	35543	777	0	0
T5	76520	1106	0	0
T6	2077	271	0	0
T7	146702	54682	0	0
T12	639	128	0	0
T17	1411	128	0	0
T18	97426	2096	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	115827263	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	464	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	20733	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	109915397	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	463	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	19928	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	115827263	0	0
T1	1020	32	0	0
T2	1278	32	0	0
T3	197803	72410	0	0
T4	35543	464	0	0
T5	76520	1626	0	0
T6	2077	74	0	0
T7	146702	20733	0	0
T12	639	32	0	0
T17	1411	32	0	0
T18	97426	33631	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T12
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411680795	410814030	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	411680795	95666815	0	0
GntImpliesValid_A	411680795	95666815	0	0
GrantKnown_A	411680795	410814030	0	0
IdxKnown_A	411680795	410814030	0	0
IndexIsCorrect_A	411680795	95666815	0	0
NoReadyValidNoGrant_A	411680795	42114638	0	0
Priority_A	411680795	101643831	0	0
ReadyAndValidImplyGrant_A	411680795	95666815	0	0
ReqAndReadyImplyGrant_A	411680795	95666815	0	0
ReqImpliesValid_A	411680795	101643831	0	0
ValidKnown_A	411680795	410814030	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666815	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666815	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666815	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	42114638	0	0
T1	1020	19	0	0
T2	1278	0	0	0
T3	197803	0	0	0
T4	35543	487	0	0
T5	76520	7	0	0
T6	2077	0	0	0
T7	146702	52820	0	0
T8	0	310617	0	0
T12	639	49	0	0
T17	1411	0	0	0
T18	97426	1662	0	0
T22	0	81	0	0
T44	0	197	0	0
T45	0	51	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	101643831	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	20518	0	0
T8	0	143530	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666815	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666815	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	101643831	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	20518	0	0
T8	0	143530	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T4,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T4,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T12
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411680795	410814030	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	411680795	95666745	0	0
GntImpliesValid_A	411680795	95666745	0	0
GrantKnown_A	411680795	410814030	0	0
IdxKnown_A	411680795	410814030	0	0
IndexIsCorrect_A	411680795	95666745	0	0
NoReadyValidNoGrant_A	411680795	42114638	0	0
Priority_A	411680795	101643761	0	0
ReadyAndValidImplyGrant_A	411680795	95666745	0	0
ReqAndReadyImplyGrant_A	411680795	95666745	0	0
ReqImpliesValid_A	411680795	101643761	0	0
ValidKnown_A	411680795	410814030	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666745	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666745	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666745	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	42114638	0	0
T1	1020	19	0	0
T2	1278	0	0	0
T3	197803	0	0	0
T4	35543	487	0	0
T5	76520	7	0	0
T6	2077	0	0	0
T7	146702	52820	0	0
T8	0	310617	0	0
T12	639	49	0	0
T17	1411	0	0	0
T18	97426	1662	0	0
T22	0	81	0	0
T44	0	197	0	0
T45	0	51	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	101643761	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	20518	0	0
T8	0	143530	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666745	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	95666745	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	19461	0	0
T8	0	8808	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	101643761	0	0
T1	1020	7	0	0
T2	1278	0	0	0
T3	197803	101532	0	0
T4	35543	323	0	0
T5	76520	65659	0	0
T6	2077	0	0	0
T7	146702	20518	0	0
T8	0	143530	0	0
T12	639	19	0	0
T17	1411	0	0	0
T18	97426	27991	0	0
T44	0	67688	0	0
T45	0	10273	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411680795	410814030	0	0
T1	1020	951	0	0
T2	1278	1203	0	0
T3	197803	197736	0	0
T4	35543	35491	0	0
T5	76520	75952	0	0
T6	2077	1963	0	0
T7	146702	146570	0	0
T12	639	571	0	0
T17	1411	1347	0	0
T18	97426	97344	0	0