SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.96 | 100.00 | 93.75 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.56 | 97.67 | 86.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10410 | 10410 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21594 |
gen_no_flops.OutputDelay_A | 811436648 | 809703118 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10410 | 10410 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T7 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 9640 | 8950 | 0 | 0 |
T2 | 3870 | 3120 | 0 | 0 |
T3 | 1978030 | 1977360 | 0 | 0 |
T4 | 355430 | 354910 | 0 | 0 |
T5 | 765200 | 759520 | 0 | 0 |
T6 | 20770 | 19630 | 0 | 0 |
T7 | 1467020 | 1465700 | 0 | 0 |
T12 | 6210 | 5530 | 0 | 0 |
T17 | 3730 | 3090 | 0 | 0 |
T18 | 974260 | 973440 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21594 |
T1 | 7600 | 7027 | 0 | 21 |
T2 | 3096 | 2496 | 0 | 0 |
T3 | 1582424 | 1581864 | 0 | 24 |
T4 | 284344 | 283904 | 0 | 24 |
T5 | 612160 | 607424 | 0 | 24 |
T6 | 16616 | 15656 | 0 | 24 |
T7 | 1173616 | 1172512 | 0 | 24 |
T8 | 0 | 0 | 0 | 3 |
T12 | 4932 | 4367 | 0 | 21 |
T17 | 2984 | 2472 | 0 | 0 |
T18 | 779408 | 778728 | 0 | 24 |
T19 | 0 | 0 | 0 | 24 |
T44 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 811436648 | 809703118 | 0 | 0 |
T1 | 2040 | 1902 | 0 | 0 |
T2 | 774 | 624 | 0 | 0 |
T3 | 395606 | 395472 | 0 | 0 |
T4 | 71086 | 70982 | 0 | 0 |
T5 | 153040 | 151904 | 0 | 0 |
T6 | 4154 | 3926 | 0 | 0 |
T7 | 293404 | 293140 | 0 | 0 |
T12 | 1278 | 1142 | 0 | 0 |
T17 | 746 | 618 | 0 | 0 |
T18 | 194852 | 194688 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718345 | 404851580 | 0 | 0 |
gen_flops.OutputDelay_A | 405718345 | 404817512 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404851580 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404817512 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718345 | 404851580 | 0 | 0 |
gen_flops.OutputDelay_A | 405718345 | 404817512 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404851580 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404817512 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718345 | 404851580 | 0 | 0 |
gen_flops.OutputDelay_A | 405718345 | 404817512 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404851580 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404817512 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718345 | 404851580 | 0 | 0 |
gen_flops.OutputDelay_A | 405718345 | 404817512 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404851580 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404817512 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718345 | 404851580 | 0 | 0 |
gen_flops.OutputDelay_A | 405718345 | 404817512 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404851580 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404817512 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718345 | 404851580 | 0 | 0 |
gen_flops.OutputDelay_A | 405718345 | 404817512 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404851580 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718345 | 404817512 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718324 | 404851559 | 0 | 0 |
gen_no_flops.OutputDelay_A | 405718324 | 404851559 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718324 | 404851559 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718324 | 404851559 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405697815 | 404831050 | 0 | 0 |
gen_flops.OutputDelay_A | 405697815 | 404797132 | 0 | 2568 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405697815 | 404831050 | 0 | 0 |
T1 | 460 | 391 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 459 | 391 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405697815 | 404797132 | 0 | 2568 |
T1 | 460 | 391 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T12 | 459 | 391 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T44 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718324 | 404851559 | 0 | 0 |
gen_no_flops.OutputDelay_A | 405718324 | 404851559 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718324 | 404851559 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718324 | 404851559 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1041 | 1041 | 0 | 0 |
OutputsKnown_A | 405718324 | 404851559 | 0 | 0 |
gen_flops.OutputDelay_A | 405718324 | 404817506 | 0 | 2718 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1041 | 1041 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718324 | 404851559 | 0 | 0 |
T1 | 1020 | 951 | 0 | 0 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197736 | 0 | 0 |
T4 | 35543 | 35491 | 0 | 0 |
T5 | 76520 | 75952 | 0 | 0 |
T6 | 2077 | 1963 | 0 | 0 |
T7 | 146702 | 146570 | 0 | 0 |
T12 | 639 | 571 | 0 | 0 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97344 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 405718324 | 404817506 | 0 | 2718 |
T1 | 1020 | 948 | 0 | 3 |
T2 | 387 | 312 | 0 | 0 |
T3 | 197803 | 197733 | 0 | 3 |
T4 | 35543 | 35488 | 0 | 3 |
T5 | 76520 | 75928 | 0 | 3 |
T6 | 2077 | 1957 | 0 | 3 |
T7 | 146702 | 146564 | 0 | 3 |
T12 | 639 | 568 | 0 | 3 |
T17 | 373 | 309 | 0 | 0 |
T18 | 97426 | 97341 | 0 | 3 |
T19 | 0 | 0 | 0 | 3 |
T50 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |