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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.73 93.96 98.31 92.52 98.25 96.89 98.21


Total test records in report: 1256
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T1078 /workspace/coverage/default/13.flash_ctrl_wo.2471931659 Aug 07 07:38:01 PM PDT 24 Aug 07 07:40:06 PM PDT 24 6564379000 ps
T1079 /workspace/coverage/default/12.flash_ctrl_otp_reset.1633417553 Aug 07 07:37:26 PM PDT 24 Aug 07 07:39:17 PM PDT 24 75940200 ps
T1080 /workspace/coverage/default/0.flash_ctrl_disable.3418267410 Aug 07 07:32:00 PM PDT 24 Aug 07 07:32:23 PM PDT 24 16222100 ps
T1081 /workspace/coverage/default/9.flash_ctrl_intr_rd.4122975918 Aug 07 07:36:25 PM PDT 24 Aug 07 07:39:51 PM PDT 24 5418413000 ps
T1082 /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2764987760 Aug 07 07:41:18 PM PDT 24 Aug 07 07:46:40 PM PDT 24 32481719500 ps
T152 /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1147837530 Aug 07 07:34:31 PM PDT 24 Aug 07 07:34:49 PM PDT 24 776668700 ps
T1083 /workspace/coverage/default/23.flash_ctrl_intr_rd.3044322676 Aug 07 07:40:03 PM PDT 24 Aug 07 07:43:22 PM PDT 24 15006948700 ps
T1084 /workspace/coverage/default/3.flash_ctrl_phy_arb.2642569107 Aug 07 07:33:13 PM PDT 24 Aug 07 07:34:21 PM PDT 24 52723400 ps
T1085 /workspace/coverage/default/1.flash_ctrl_rw.4070196135 Aug 07 07:32:31 PM PDT 24 Aug 07 07:39:55 PM PDT 24 14641616400 ps
T1086 /workspace/coverage/default/2.flash_ctrl_otp_reset.643045877 Aug 07 07:32:54 PM PDT 24 Aug 07 07:34:47 PM PDT 24 201428900 ps
T1087 /workspace/coverage/default/17.flash_ctrl_smoke.2208247034 Aug 07 07:39:06 PM PDT 24 Aug 07 07:41:59 PM PDT 24 29808500 ps
T1088 /workspace/coverage/default/14.flash_ctrl_alert_test.3773504650 Aug 07 07:38:22 PM PDT 24 Aug 07 07:38:35 PM PDT 24 26179100 ps
T1089 /workspace/coverage/default/8.flash_ctrl_otp_reset.777282534 Aug 07 07:35:52 PM PDT 24 Aug 07 07:38:02 PM PDT 24 43938800 ps
T1090 /workspace/coverage/default/52.flash_ctrl_otp_reset.1303726143 Aug 07 07:42:31 PM PDT 24 Aug 07 07:44:46 PM PDT 24 73287500 ps
T1091 /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3468823077 Aug 07 07:41:05 PM PDT 24 Aug 07 07:41:37 PM PDT 24 77407600 ps
T1092 /workspace/coverage/default/56.flash_ctrl_otp_reset.1692818533 Aug 07 07:42:41 PM PDT 24 Aug 07 07:44:54 PM PDT 24 140963300 ps
T1093 /workspace/coverage/default/6.flash_ctrl_connect.1226431944 Aug 07 07:35:16 PM PDT 24 Aug 07 07:35:33 PM PDT 24 57802400 ps
T1094 /workspace/coverage/default/25.flash_ctrl_prog_reset.2814241237 Aug 07 07:40:33 PM PDT 24 Aug 07 07:40:47 PM PDT 24 59545100 ps
T1095 /workspace/coverage/default/6.flash_ctrl_intr_rd.1302979289 Aug 07 07:35:04 PM PDT 24 Aug 07 07:38:53 PM PDT 24 22477740000 ps
T1096 /workspace/coverage/default/7.flash_ctrl_smoke.994388163 Aug 07 07:35:13 PM PDT 24 Aug 07 07:36:56 PM PDT 24 66069900 ps
T1097 /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.4184272554 Aug 07 07:41:57 PM PDT 24 Aug 07 07:44:33 PM PDT 24 3656224500 ps
T1098 /workspace/coverage/default/78.flash_ctrl_otp_reset.2472940575 Aug 07 07:43:01 PM PDT 24 Aug 07 07:45:13 PM PDT 24 284327000 ps
T1099 /workspace/coverage/default/23.flash_ctrl_disable.1250455550 Aug 07 07:40:16 PM PDT 24 Aug 07 07:40:37 PM PDT 24 12819300 ps
T1100 /workspace/coverage/default/10.flash_ctrl_invalid_op.591831132 Aug 07 07:37:19 PM PDT 24 Aug 07 07:38:20 PM PDT 24 2682500100 ps
T1101 /workspace/coverage/default/30.flash_ctrl_sec_info_access.370928800 Aug 07 07:41:04 PM PDT 24 Aug 07 07:42:08 PM PDT 24 1008970200 ps
T1102 /workspace/coverage/default/0.flash_ctrl_rw_serr.3820091283 Aug 07 07:31:52 PM PDT 24 Aug 07 07:35:45 PM PDT 24 9593863700 ps
T1103 /workspace/coverage/default/10.flash_ctrl_smoke.70537592 Aug 07 07:37:10 PM PDT 24 Aug 07 07:39:39 PM PDT 24 29944200 ps
T1104 /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.361922301 Aug 07 07:33:14 PM PDT 24 Aug 07 07:47:33 PM PDT 24 130166018000 ps
T1105 /workspace/coverage/default/5.flash_ctrl_wo.2374149947 Aug 07 07:34:48 PM PDT 24 Aug 07 07:37:42 PM PDT 24 2500848900 ps
T1106 /workspace/coverage/default/8.flash_ctrl_rand_ops.2278272018 Aug 07 07:35:48 PM PDT 24 Aug 07 07:49:05 PM PDT 24 678250400 ps
T346 /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1967697943 Aug 07 07:40:52 PM PDT 24 Aug 07 07:41:23 PM PDT 24 148669500 ps
T1107 /workspace/coverage/default/2.flash_ctrl_wo.635014831 Aug 07 07:32:53 PM PDT 24 Aug 07 07:35:55 PM PDT 24 2053852700 ps
T1108 /workspace/coverage/default/6.flash_ctrl_disable.2302419526 Aug 07 07:35:13 PM PDT 24 Aug 07 07:35:35 PM PDT 24 10294300 ps
T1109 /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.105240713 Aug 07 07:34:15 PM PDT 24 Aug 07 07:40:19 PM PDT 24 65390227300 ps
T1110 /workspace/coverage/default/36.flash_ctrl_otp_reset.1193443009 Aug 07 07:41:45 PM PDT 24 Aug 07 07:43:35 PM PDT 24 51386000 ps
T1111 /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2318226010 Aug 07 07:39:48 PM PDT 24 Aug 07 07:40:02 PM PDT 24 48382900 ps
T1112 /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2850605198 Aug 07 07:31:53 PM PDT 24 Aug 07 07:32:09 PM PDT 24 77268300 ps
T1113 /workspace/coverage/default/1.flash_ctrl_fetch_code.1411712829 Aug 07 07:32:21 PM PDT 24 Aug 07 07:32:48 PM PDT 24 640658400 ps
T277 /workspace/coverage/default/0.flash_ctrl_host_dir_rd.4137020904 Aug 07 07:31:49 PM PDT 24 Aug 07 07:32:50 PM PDT 24 158259700 ps
T1114 /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.637934988 Aug 07 07:42:05 PM PDT 24 Aug 07 07:43:29 PM PDT 24 2034224400 ps
T1115 /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.3462917275 Aug 07 07:41:41 PM PDT 24 Aug 07 07:43:10 PM PDT 24 2446852000 ps
T65 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3090041208 Aug 07 07:25:33 PM PDT 24 Aug 07 07:26:03 PM PDT 24 930009600 ps
T1116 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3730170316 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:04 PM PDT 24 16603500 ps
T258 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2999930887 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:05 PM PDT 24 48389000 ps
T1117 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3816378592 Aug 07 07:26:33 PM PDT 24 Aug 07 07:26:48 PM PDT 24 22564400 ps
T66 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3470794314 Aug 07 07:25:42 PM PDT 24 Aug 07 07:26:13 PM PDT 24 31533300 ps
T67 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.362074956 Aug 07 07:25:40 PM PDT 24 Aug 07 07:33:21 PM PDT 24 426115200 ps
T103 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2326706969 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:40 PM PDT 24 226173900 ps
T105 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.65344907 Aug 07 07:25:17 PM PDT 24 Aug 07 07:25:34 PM PDT 24 32254400 ps
T104 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2074318457 Aug 07 07:26:25 PM PDT 24 Aug 07 07:41:26 PM PDT 24 6222371800 ps
T254 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.729326151 Aug 07 07:25:34 PM PDT 24 Aug 07 07:27:08 PM PDT 24 24794128500 ps
T259 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1856831209 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:39 PM PDT 24 44715200 ps
T106 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1329453379 Aug 07 07:26:05 PM PDT 24 Aug 07 07:41:12 PM PDT 24 6587913200 ps
T309 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.397219786 Aug 07 07:26:54 PM PDT 24 Aug 07 07:27:08 PM PDT 24 132091800 ps
T310 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.874949640 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:07 PM PDT 24 24420800 ps
T312 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2083116517 Aug 07 07:26:44 PM PDT 24 Aug 07 07:26:58 PM PDT 24 25939600 ps
T311 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3757261836 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:07 PM PDT 24 190941900 ps
T1118 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1190799712 Aug 07 07:25:22 PM PDT 24 Aug 07 07:25:38 PM PDT 24 37702800 ps
T1119 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.154452231 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:07 PM PDT 24 23710600 ps
T1120 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4039401779 Aug 07 07:26:02 PM PDT 24 Aug 07 07:26:15 PM PDT 24 14983800 ps
T1121 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.621805232 Aug 07 07:26:24 PM PDT 24 Aug 07 07:26:40 PM PDT 24 11295000 ps
T220 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3730112600 Aug 07 07:25:11 PM PDT 24 Aug 07 07:25:28 PM PDT 24 147636900 ps
T242 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1676663959 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:42 PM PDT 24 76595900 ps
T221 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2923674750 Aug 07 07:25:43 PM PDT 24 Aug 07 07:26:03 PM PDT 24 136796800 ps
T243 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2875274720 Aug 07 07:25:25 PM PDT 24 Aug 07 07:25:43 PM PDT 24 274858000 ps
T362 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2030862843 Aug 07 07:25:24 PM PDT 24 Aug 07 07:25:57 PM PDT 24 432381100 ps
T244 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2360981666 Aug 07 07:26:24 PM PDT 24 Aug 07 07:26:42 PM PDT 24 368406200 ps
T230 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4244429408 Aug 07 07:26:15 PM PDT 24 Aug 07 07:26:31 PM PDT 24 60440000 ps
T231 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.994389796 Aug 07 07:26:29 PM PDT 24 Aug 07 07:39:07 PM PDT 24 605620000 ps
T1122 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.784418222 Aug 07 07:25:42 PM PDT 24 Aug 07 07:25:55 PM PDT 24 13412100 ps
T1123 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1495336860 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:39 PM PDT 24 74287300 ps
T245 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3532185833 Aug 07 07:25:43 PM PDT 24 Aug 07 07:26:01 PM PDT 24 303399900 ps
T1124 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1581519481 Aug 07 07:25:32 PM PDT 24 Aug 07 07:25:45 PM PDT 24 18645000 ps
T246 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2183147268 Aug 07 07:26:04 PM PDT 24 Aug 07 07:26:21 PM PDT 24 32533200 ps
T232 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3654891201 Aug 07 07:26:04 PM PDT 24 Aug 07 07:26:22 PM PDT 24 73248200 ps
T233 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2432183942 Aug 07 07:26:43 PM PDT 24 Aug 07 07:27:02 PM PDT 24 82988100 ps
T1125 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4019786596 Aug 07 07:26:24 PM PDT 24 Aug 07 07:26:40 PM PDT 24 16655000 ps
T1126 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1650428779 Aug 07 07:25:53 PM PDT 24 Aug 07 07:26:09 PM PDT 24 22243900 ps
T1127 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2017321998 Aug 07 07:26:16 PM PDT 24 Aug 07 07:26:29 PM PDT 24 152013100 ps
T1128 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.858075575 Aug 07 07:26:42 PM PDT 24 Aug 07 07:26:57 PM PDT 24 20471100 ps
T1129 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.883541862 Aug 07 07:25:41 PM PDT 24 Aug 07 07:26:12 PM PDT 24 49904600 ps
T1130 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3191198584 Aug 07 07:26:42 PM PDT 24 Aug 07 07:26:58 PM PDT 24 20072600 ps
T247 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3985760774 Aug 07 07:26:44 PM PDT 24 Aug 07 07:27:19 PM PDT 24 62718100 ps
T234 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1448472429 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:46 PM PDT 24 238924800 ps
T1131 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1980313177 Aug 07 07:26:54 PM PDT 24 Aug 07 07:27:08 PM PDT 24 17951300 ps
T1132 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1475909864 Aug 07 07:25:50 PM PDT 24 Aug 07 07:26:04 PM PDT 24 17438700 ps
T248 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2667520576 Aug 07 07:26:33 PM PDT 24 Aug 07 07:27:04 PM PDT 24 125367900 ps
T235 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3017365604 Aug 07 07:25:32 PM PDT 24 Aug 07 07:38:11 PM PDT 24 457048600 ps
T249 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.291357993 Aug 07 07:26:03 PM PDT 24 Aug 07 07:26:17 PM PDT 24 37249300 ps
T1133 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2392125574 Aug 07 07:25:15 PM PDT 24 Aug 07 07:25:28 PM PDT 24 27708900 ps
T314 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2077488803 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:06 PM PDT 24 26455400 ps
T1134 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1998338478 Aug 07 07:25:19 PM PDT 24 Aug 07 07:26:01 PM PDT 24 669938000 ps
T313 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3967840444 Aug 07 07:27:01 PM PDT 24 Aug 07 07:27:15 PM PDT 24 31920800 ps
T292 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2162607592 Aug 07 07:26:14 PM PDT 24 Aug 07 07:26:30 PM PDT 24 355273700 ps
T272 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4180924188 Aug 07 07:25:52 PM PDT 24 Aug 07 07:38:49 PM PDT 24 1338796200 ps
T315 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4268291590 Aug 07 07:26:42 PM PDT 24 Aug 07 07:26:55 PM PDT 24 39335900 ps
T274 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.20643235 Aug 07 07:25:25 PM PDT 24 Aug 07 07:40:31 PM PDT 24 1800459100 ps
T263 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.823818041 Aug 07 07:26:13 PM PDT 24 Aug 07 07:26:30 PM PDT 24 126003900 ps
T1135 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3533270983 Aug 07 07:25:52 PM PDT 24 Aug 07 07:26:08 PM PDT 24 15812600 ps
T1136 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3369049526 Aug 07 07:26:26 PM PDT 24 Aug 07 07:26:55 PM PDT 24 82490300 ps
T1137 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4201328201 Aug 07 07:26:35 PM PDT 24 Aug 07 07:26:51 PM PDT 24 51219100 ps
T255 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1511079860 Aug 07 07:25:32 PM PDT 24 Aug 07 07:25:52 PM PDT 24 134532100 ps
T1138 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.75265042 Aug 07 07:25:33 PM PDT 24 Aug 07 07:25:49 PM PDT 24 29407900 ps
T1139 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3876514449 Aug 07 07:26:05 PM PDT 24 Aug 07 07:26:20 PM PDT 24 24902600 ps
T1140 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1832397199 Aug 07 07:26:15 PM PDT 24 Aug 07 07:26:28 PM PDT 24 51976400 ps
T1141 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.222402048 Aug 07 07:26:45 PM PDT 24 Aug 07 07:26:59 PM PDT 24 49668200 ps
T1142 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1554825602 Aug 07 07:27:01 PM PDT 24 Aug 07 07:27:15 PM PDT 24 18536200 ps
T1143 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2578313006 Aug 07 07:25:41 PM PDT 24 Aug 07 07:25:54 PM PDT 24 16954200 ps
T256 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1596983957 Aug 07 07:25:51 PM PDT 24 Aug 07 07:38:27 PM PDT 24 1314980400 ps
T1144 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2660838891 Aug 07 07:26:34 PM PDT 24 Aug 07 07:26:48 PM PDT 24 54101800 ps
T357 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2760253627 Aug 07 07:26:13 PM PDT 24 Aug 07 07:33:57 PM PDT 24 183756100 ps
T293 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2766371579 Aug 07 07:26:15 PM PDT 24 Aug 07 07:26:33 PM PDT 24 984674200 ps
T294 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2110349323 Aug 07 07:26:03 PM PDT 24 Aug 07 07:26:23 PM PDT 24 178426300 ps
T1145 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2835183802 Aug 07 07:25:27 PM PDT 24 Aug 07 07:25:44 PM PDT 24 27293800 ps
T1146 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1983159014 Aug 07 07:26:13 PM PDT 24 Aug 07 07:26:30 PM PDT 24 92356400 ps
T358 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2598708599 Aug 07 07:26:15 PM PDT 24 Aug 07 07:32:43 PM PDT 24 526103500 ps
T257 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2419974990 Aug 07 07:26:05 PM PDT 24 Aug 07 07:26:22 PM PDT 24 71459900 ps
T1147 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4206206455 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:41 PM PDT 24 20805400 ps
T1148 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.955593734 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:07 PM PDT 24 28178500 ps
T268 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2699016685 Aug 07 07:25:52 PM PDT 24 Aug 07 07:26:09 PM PDT 24 34323900 ps
T1149 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.352103741 Aug 07 07:25:15 PM PDT 24 Aug 07 07:26:01 PM PDT 24 27298600 ps
T275 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3901736156 Aug 07 07:26:35 PM PDT 24 Aug 07 07:34:13 PM PDT 24 421888700 ps
T1150 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2312619840 Aug 07 07:25:22 PM PDT 24 Aug 07 07:25:38 PM PDT 24 66002000 ps
T270 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2013687458 Aug 07 07:26:34 PM PDT 24 Aug 07 07:26:51 PM PDT 24 40133000 ps
T296 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2019379559 Aug 07 07:25:22 PM PDT 24 Aug 07 07:25:40 PM PDT 24 335658800 ps
T1151 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2659994933 Aug 07 07:26:16 PM PDT 24 Aug 07 07:26:33 PM PDT 24 56464600 ps
T1152 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1961237627 Aug 07 07:26:42 PM PDT 24 Aug 07 07:26:59 PM PDT 24 309705600 ps
T269 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1817199180 Aug 07 07:26:46 PM PDT 24 Aug 07 07:27:06 PM PDT 24 186148500 ps
T297 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2686250566 Aug 07 07:25:27 PM PDT 24 Aug 07 07:25:44 PM PDT 24 89501200 ps
T1153 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1506351211 Aug 07 07:25:33 PM PDT 24 Aug 07 07:25:49 PM PDT 24 31287400 ps
T1154 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1444330130 Aug 07 07:25:53 PM PDT 24 Aug 07 07:26:11 PM PDT 24 133091800 ps
T1155 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1548212668 Aug 07 07:26:03 PM PDT 24 Aug 07 07:26:17 PM PDT 24 28871700 ps
T1156 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3549755299 Aug 07 07:26:43 PM PDT 24 Aug 07 07:27:00 PM PDT 24 45904900 ps
T1157 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.195531135 Aug 07 07:25:42 PM PDT 24 Aug 07 07:26:52 PM PDT 24 637658500 ps
T1158 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.709496849 Aug 07 07:26:36 PM PDT 24 Aug 07 07:26:49 PM PDT 24 76215700 ps
T295 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1161153029 Aug 07 07:26:46 PM PDT 24 Aug 07 07:27:05 PM PDT 24 100208500 ps
T1159 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3447211659 Aug 07 07:25:14 PM PDT 24 Aug 07 07:25:30 PM PDT 24 31657600 ps
T298 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2906171276 Aug 07 07:25:42 PM PDT 24 Aug 07 07:26:00 PM PDT 24 66357200 ps
T1160 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.421205831 Aug 07 07:25:22 PM PDT 24 Aug 07 07:25:35 PM PDT 24 34851200 ps
T1161 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2414188045 Aug 07 07:26:43 PM PDT 24 Aug 07 07:26:59 PM PDT 24 23369500 ps
T1162 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2225242156 Aug 07 07:25:31 PM PDT 24 Aug 07 07:25:44 PM PDT 24 15887300 ps
T273 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3209346336 Aug 07 07:26:04 PM PDT 24 Aug 07 07:26:25 PM PDT 24 165945600 ps
T265 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1739922234 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:08 PM PDT 24 36081100 ps
T1163 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1740813236 Aug 07 07:26:06 PM PDT 24 Aug 07 07:26:21 PM PDT 24 12823000 ps
T1164 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3616217818 Aug 07 07:26:02 PM PDT 24 Aug 07 07:26:19 PM PDT 24 31130700 ps
T356 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.621432392 Aug 07 07:25:19 PM PDT 24 Aug 07 07:40:14 PM PDT 24 661200200 ps
T1165 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4293114366 Aug 07 07:26:05 PM PDT 24 Aug 07 07:26:22 PM PDT 24 118427700 ps
T1166 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3027961821 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:45 PM PDT 24 245412600 ps
T1167 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.434628183 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:06 PM PDT 24 56755900 ps
T1168 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.470843787 Aug 07 07:26:26 PM PDT 24 Aug 07 07:26:41 PM PDT 24 175822400 ps
T1169 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3995067778 Aug 07 07:25:13 PM PDT 24 Aug 07 07:25:27 PM PDT 24 26360800 ps
T1170 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3435613899 Aug 07 07:25:26 PM PDT 24 Aug 07 07:25:39 PM PDT 24 44454600 ps
T1171 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4226824006 Aug 07 07:26:36 PM PDT 24 Aug 07 07:26:53 PM PDT 24 27811300 ps
T1172 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2859950642 Aug 07 07:27:03 PM PDT 24 Aug 07 07:27:17 PM PDT 24 15719000 ps
T1173 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2428522353 Aug 07 07:25:27 PM PDT 24 Aug 07 07:25:43 PM PDT 24 13371100 ps
T1174 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4110664352 Aug 07 07:26:04 PM PDT 24 Aug 07 07:26:18 PM PDT 24 49760300 ps
T299 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.398055506 Aug 07 07:25:50 PM PDT 24 Aug 07 07:26:11 PM PDT 24 217065600 ps
T1175 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2574378436 Aug 07 07:25:40 PM PDT 24 Aug 07 07:25:54 PM PDT 24 15482000 ps
T1176 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.481833790 Aug 07 07:26:26 PM PDT 24 Aug 07 07:26:39 PM PDT 24 41762200 ps
T1177 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1958188995 Aug 07 07:25:33 PM PDT 24 Aug 07 07:25:46 PM PDT 24 17763600 ps
T1178 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.138159379 Aug 07 07:26:05 PM PDT 24 Aug 07 07:26:20 PM PDT 24 22813500 ps
T1179 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.991102714 Aug 07 07:25:50 PM PDT 24 Aug 07 07:26:09 PM PDT 24 97294400 ps
T1180 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3373081632 Aug 07 07:26:06 PM PDT 24 Aug 07 07:26:24 PM PDT 24 68111600 ps
T1181 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2379960170 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:06 PM PDT 24 25423400 ps
T1182 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4021271291 Aug 07 07:26:23 PM PDT 24 Aug 07 07:26:39 PM PDT 24 25170600 ps
T264 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4165107052 Aug 07 07:26:24 PM PDT 24 Aug 07 07:32:46 PM PDT 24 657603900 ps
T261 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2411033255 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:11 PM PDT 24 55320600 ps
T1183 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2074046728 Aug 07 07:25:42 PM PDT 24 Aug 07 07:25:56 PM PDT 24 66528900 ps
T300 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.720550074 Aug 07 07:25:52 PM PDT 24 Aug 07 07:26:10 PM PDT 24 430131500 ps
T1184 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.182515483 Aug 07 07:26:02 PM PDT 24 Aug 07 07:26:18 PM PDT 24 92512100 ps
T1185 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1518416158 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:46 PM PDT 24 2011180100 ps
T360 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3225075505 Aug 07 07:25:24 PM PDT 24 Aug 07 07:31:48 PM PDT 24 459164100 ps
T1186 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1467963444 Aug 07 07:25:50 PM PDT 24 Aug 07 07:26:06 PM PDT 24 501579800 ps
T1187 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.372591476 Aug 07 07:26:51 PM PDT 24 Aug 07 07:27:05 PM PDT 24 24528800 ps
T359 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2520972985 Aug 07 07:26:02 PM PDT 24 Aug 07 07:32:25 PM PDT 24 647180400 ps
T354 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2709708972 Aug 07 07:26:05 PM PDT 24 Aug 07 07:41:02 PM PDT 24 702678600 ps
T1188 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.136094721 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:06 PM PDT 24 14718100 ps
T1189 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1079208617 Aug 07 07:26:13 PM PDT 24 Aug 07 07:26:33 PM PDT 24 300540400 ps
T1190 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2995811114 Aug 07 07:25:52 PM PDT 24 Aug 07 07:26:06 PM PDT 24 56451700 ps
T1191 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2873803893 Aug 07 07:26:05 PM PDT 24 Aug 07 07:26:21 PM PDT 24 22991200 ps
T266 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1245940604 Aug 07 07:26:43 PM PDT 24 Aug 07 07:39:31 PM PDT 24 1319179100 ps
T1192 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3453377054 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:06 PM PDT 24 16512800 ps
T1193 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1389934913 Aug 07 07:25:26 PM PDT 24 Aug 07 07:25:40 PM PDT 24 18160400 ps
T1194 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1050447913 Aug 07 07:26:06 PM PDT 24 Aug 07 07:26:19 PM PDT 24 14848200 ps
T1195 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1449538206 Aug 07 07:25:40 PM PDT 24 Aug 07 07:26:13 PM PDT 24 221083300 ps
T1196 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1821666746 Aug 07 07:25:24 PM PDT 24 Aug 07 07:26:03 PM PDT 24 156053000 ps
T1197 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.110167672 Aug 07 07:26:45 PM PDT 24 Aug 07 07:27:00 PM PDT 24 50092800 ps
T267 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3543884393 Aug 07 07:25:24 PM PDT 24 Aug 07 07:25:40 PM PDT 24 32016700 ps
T1198 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3359170266 Aug 07 07:25:32 PM PDT 24 Aug 07 07:26:02 PM PDT 24 68101400 ps
T1199 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1456634213 Aug 07 07:25:53 PM PDT 24 Aug 07 07:26:07 PM PDT 24 93493300 ps
T1200 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1462737115 Aug 07 07:26:43 PM PDT 24 Aug 07 07:27:19 PM PDT 24 434845900 ps
T237 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2737523519 Aug 07 07:25:42 PM PDT 24 Aug 07 07:25:56 PM PDT 24 77788700 ps
T1201 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3145361171 Aug 07 07:26:24 PM PDT 24 Aug 07 07:26:40 PM PDT 24 48840300 ps
T238 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1329785263 Aug 07 07:25:22 PM PDT 24 Aug 07 07:25:36 PM PDT 24 27368900 ps
T1202 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.351777030 Aug 07 07:26:05 PM PDT 24 Aug 07 07:26:22 PM PDT 24 32504000 ps
T1203 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4056652914 Aug 07 07:26:44 PM PDT 24 Aug 07 07:27:00 PM PDT 24 23896800 ps
T260 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2349632160 Aug 07 07:26:26 PM PDT 24 Aug 07 07:26:45 PM PDT 24 124693200 ps
T1204 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1052185192 Aug 07 07:26:02 PM PDT 24 Aug 07 07:26:19 PM PDT 24 75803700 ps
T1205 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.640646732 Aug 07 07:26:54 PM PDT 24 Aug 07 07:27:08 PM PDT 24 23874700 ps
T1206 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1433857525 Aug 07 07:26:24 PM PDT 24 Aug 07 07:26:43 PM PDT 24 95216500 ps
T1207 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1236043054 Aug 07 07:27:01 PM PDT 24 Aug 07 07:27:15 PM PDT 24 57589400 ps
T1208 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2348231669 Aug 07 07:25:31 PM PDT 24 Aug 07 07:26:05 PM PDT 24 826926300 ps
T1209 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.705100259 Aug 07 07:26:13 PM PDT 24 Aug 07 07:26:43 PM PDT 24 62189800 ps
T1210 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.691850949 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:43 PM PDT 24 1577810300 ps
T1211 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3865711664 Aug 07 07:27:01 PM PDT 24 Aug 07 07:27:15 PM PDT 24 19717600 ps
T1212 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2504261713 Aug 07 07:25:32 PM PDT 24 Aug 07 07:25:49 PM PDT 24 97194400 ps
T1213 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1320097073 Aug 07 07:26:35 PM PDT 24 Aug 07 07:26:50 PM PDT 24 32430300 ps
T1214 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.688042829 Aug 07 07:25:22 PM PDT 24 Aug 07 07:25:38 PM PDT 24 34305700 ps
T1215 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1306237995 Aug 07 07:26:37 PM PDT 24 Aug 07 07:26:55 PM PDT 24 212113600 ps
T1216 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1930910131 Aug 07 07:25:42 PM PDT 24 Aug 07 07:25:55 PM PDT 24 27492600 ps
T271 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4000015087 Aug 07 07:26:03 PM PDT 24 Aug 07 07:26:23 PM PDT 24 88871400 ps
T1217 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3234550495 Aug 07 07:25:32 PM PDT 24 Aug 07 07:25:49 PM PDT 24 677635100 ps
T239 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.885700706 Aug 07 07:25:26 PM PDT 24 Aug 07 07:25:40 PM PDT 24 32108200 ps
T1218 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3199113203 Aug 07 07:26:36 PM PDT 24 Aug 07 07:26:51 PM PDT 24 191925000 ps
T1219 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1244068318 Aug 07 07:26:54 PM PDT 24 Aug 07 07:27:08 PM PDT 24 14742900 ps
T1220 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.975755084 Aug 07 07:26:28 PM PDT 24 Aug 07 07:26:44 PM PDT 24 19783400 ps
T1221 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2220554408 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:08 PM PDT 24 57172200 ps
T1222 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.973004859 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:06 PM PDT 24 16462500 ps
T1223 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1208750092 Aug 07 07:25:27 PM PDT 24 Aug 07 07:26:05 PM PDT 24 1786774900 ps
T262 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.633824282 Aug 07 07:25:44 PM PDT 24 Aug 07 07:26:01 PM PDT 24 78674300 ps
T1224 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2301443185 Aug 07 07:26:34 PM PDT 24 Aug 07 07:26:48 PM PDT 24 50092800 ps
T1225 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4009682743 Aug 07 07:26:42 PM PDT 24 Aug 07 07:27:12 PM PDT 24 117630600 ps
T1226 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2312823625 Aug 07 07:25:51 PM PDT 24 Aug 07 07:26:04 PM PDT 24 42500600 ps
T1227 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.449406953 Aug 07 07:25:25 PM PDT 24 Aug 07 07:25:46 PM PDT 24 246313400 ps
T1228 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1876753643 Aug 07 07:25:52 PM PDT 24 Aug 07 07:26:11 PM PDT 24 164966900 ps
T240 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.75937361 Aug 07 07:25:31 PM PDT 24 Aug 07 07:25:44 PM PDT 24 29871500 ps
T1229 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3671826642 Aug 07 07:26:44 PM PDT 24 Aug 07 07:27:01 PM PDT 24 378114700 ps
T1230 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.718096220 Aug 07 07:27:02 PM PDT 24 Aug 07 07:27:16 PM PDT 24 50891800 ps
T1231 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3044913885 Aug 07 07:25:50 PM PDT 24 Aug 07 07:32:18 PM PDT 24 647471100 ps
T1232 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2773405787 Aug 07 07:25:50 PM PDT 24 Aug 07 07:26:04 PM PDT 24 13398900 ps
T1233 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1154898733 Aug 07 07:26:25 PM PDT 24 Aug 07 07:26:40 PM PDT 24 152839400 ps
T1234 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2711575268 Aug 07 07:25:24 PM PDT 24 Aug 07 07:25:43 PM PDT 24 613552300 ps
T1235 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1937401164 Aug 07 07:25:15 PM PDT 24 Aug 07 07:25:28 PM PDT 24 37188100 ps
T241 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2381322582 Aug 07 07:25:16 PM PDT 24 Aug 07 07:25:30 PM PDT 24 18540500 ps
T1236 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1069871403 Aug 07 07:26:34 PM PDT 24 Aug 07 07:26:53 PM PDT 24 77923200 ps
T1237 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.583031400 Aug 07 07:26:34 PM PDT 24 Aug 07 07:26:50 PM PDT 24 14195900 ps
T1238 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4267311939 Aug 07 07:26:52 PM PDT 24 Aug 07 07:27:05 PM PDT 24 16539600 ps
T1239 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2098028802 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:06 PM PDT 24 14961400 ps
T1240 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.21750701 Aug 07 07:26:34 PM PDT 24 Aug 07 07:26:50 PM PDT 24 178726300 ps
T1241 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2527884509 Aug 07 07:26:36 PM PDT 24 Aug 07 07:27:11 PM PDT 24 364321800 ps
T1242 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1231087083 Aug 07 07:25:50 PM PDT 24 Aug 07 07:26:07 PM PDT 24 189055600 ps
T1243 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4089810145 Aug 07 07:25:32 PM PDT 24 Aug 07 07:26:33 PM PDT 24 2530700500 ps
T1244 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.166299210 Aug 07 07:26:26 PM PDT 24 Aug 07 07:26:39 PM PDT 24 26122800 ps
T1245 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2923125233 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:06 PM PDT 24 16980200 ps
T1246 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1760062069 Aug 07 07:26:12 PM PDT 24 Aug 07 07:26:28 PM PDT 24 14134300 ps
T1247 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1709827266 Aug 07 07:26:24 PM PDT 24 Aug 07 07:26:43 PM PDT 24 90611200 ps
T1248 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3653322200 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:07 PM PDT 24 28855800 ps
T1249 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.277770275 Aug 07 07:26:53 PM PDT 24 Aug 07 07:27:07 PM PDT 24 18844700 ps
T355 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2400172939 Aug 07 07:26:45 PM PDT 24 Aug 07 07:41:59 PM PDT 24 1289561100 ps
T1250 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.419253852 Aug 07 07:26:36 PM PDT 24 Aug 07 07:41:42 PM PDT 24 1493093800 ps
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