Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.73 93.96 98.31 92.52 98.25 96.89 98.21


Total test records in report: 1256
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T1251 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1675445053 Aug 07 07:26:26 PM PDT 24 Aug 07 07:26:46 PM PDT 24 341198000 ps
T1252 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3060252075 Aug 07 07:26:02 PM PDT 24 Aug 07 07:26:22 PM PDT 24 440326800 ps
T1253 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1402176481 Aug 07 07:26:36 PM PDT 24 Aug 07 07:26:55 PM PDT 24 71400000 ps
T1254 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.256509193 Aug 07 07:26:42 PM PDT 24 Aug 07 07:26:56 PM PDT 24 15009800 ps
T1255 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.468899957 Aug 07 07:27:01 PM PDT 24 Aug 07 07:27:15 PM PDT 24 20682900 ps
T1256 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2684878251 Aug 07 07:26:59 PM PDT 24 Aug 07 07:27:13 PM PDT 24 19662500 ps

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1080473112
Short name T5
Test name
Test status
Simulation time 1561026700 ps
CPU time 499.98 seconds
Started Aug 07 07:33:33 PM PDT 24
Finished Aug 07 07:41:53 PM PDT 24
Peak memory 280832 kb
Host smart-52deb9e9-eced-4e63-9100-55e7887589da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080473112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1080473112
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2074318457
Short name T104
Test name
Test status
Simulation time 6222371800 ps
CPU time 900.25 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:41:26 PM PDT 24
Peak memory 264300 kb
Host smart-c4b6921e-8c3c-486c-9ce6-c7dc26bd81e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074318457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.2074318457
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3319059650
Short name T32
Test name
Test status
Simulation time 13250123200 ps
CPU time 370.05 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:45:45 PM PDT 24
Peak memory 274888 kb
Host smart-03b386b8-146f-43e8-b9f4-c0442df948c7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319059650 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.3319059650
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.1860209634
Short name T46
Test name
Test status
Simulation time 35279607900 ps
CPU time 594.29 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:42:47 PM PDT 24
Peak memory 314820 kb
Host smart-4575a1c6-dbd0-49c0-97f3-c5c3e7309dca
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860209634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.1860209634
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.2297545639
Short name T70
Test name
Test status
Simulation time 39542400 ps
CPU time 133.04 seconds
Started Aug 07 07:42:59 PM PDT 24
Finished Aug 07 07:45:12 PM PDT 24
Peak memory 260284 kb
Host smart-05497976-6df3-4fcc-bb41-d7fe916b3f7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297545639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.2297545639
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1795780145
Short name T15
Test name
Test status
Simulation time 7611036600 ps
CPU time 5022.53 seconds
Started Aug 07 07:33:06 PM PDT 24
Finished Aug 07 08:56:50 PM PDT 24
Peak memory 289856 kb
Host smart-b83f22b4-2965-4d1c-adb4-a01bc7b8b4a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795780145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1795780145
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2490077118
Short name T113
Test name
Test status
Simulation time 160197970200 ps
CPU time 984.85 seconds
Started Aug 07 07:36:19 PM PDT 24
Finished Aug 07 07:52:44 PM PDT 24
Peak memory 264548 kb
Host smart-9f769965-7ea1-4632-8afa-944e9f669f37
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490077118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2490077118
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2984478144
Short name T45
Test name
Test status
Simulation time 3285448700 ps
CPU time 72.4 seconds
Started Aug 07 07:31:53 PM PDT 24
Finished Aug 07 07:33:05 PM PDT 24
Peak memory 260652 kb
Host smart-ff6055b3-ef48-42c0-a12c-b37068028ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984478144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2984478144
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1150528003
Short name T7
Test name
Test status
Simulation time 20949153800 ps
CPU time 209.05 seconds
Started Aug 07 07:41:17 PM PDT 24
Finished Aug 07 07:44:46 PM PDT 24
Peak memory 291156 kb
Host smart-9020b71d-20e3-407e-8cc7-84fd65f479ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150528003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1150528003
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1798139227
Short name T44
Test name
Test status
Simulation time 8712575100 ps
CPU time 378.17 seconds
Started Aug 07 07:33:46 PM PDT 24
Finished Aug 07 07:40:04 PM PDT 24
Peak memory 263612 kb
Host smart-4dd97f24-cc56-4eb7-b1a4-e393d8e3a96c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1798139227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1798139227
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1719401421
Short name T10
Test name
Test status
Simulation time 77342300 ps
CPU time 13.59 seconds
Started Aug 07 07:33:49 PM PDT 24
Finished Aug 07 07:34:03 PM PDT 24
Peak memory 262904 kb
Host smart-a6d5d682-7640-4792-9f47-c23014b99917
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719401421 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1719401421
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3419580280
Short name T98
Test name
Test status
Simulation time 68499399700 ps
CPU time 207.29 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:44:43 PM PDT 24
Peak memory 263056 kb
Host smart-ae5bac38-1a49-4703-a4d1-50e98e08ee48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419580280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3419580280
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1448472429
Short name T234
Test name
Test status
Simulation time 238924800 ps
CPU time 21.02 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:46 PM PDT 24
Peak memory 264412 kb
Host smart-6cc91284-7a14-4ec8-8e7a-d2e15efbd005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448472429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1448472429
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.441669065
Short name T454
Test name
Test status
Simulation time 143215100 ps
CPU time 133.05 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:39:32 PM PDT 24
Peak memory 265148 kb
Host smart-9653b8d8-293c-4354-a093-d96797aa8da4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441669065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ot
p_reset.441669065
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.562995089
Short name T85
Test name
Test status
Simulation time 10012942200 ps
CPU time 335.43 seconds
Started Aug 07 07:37:50 PM PDT 24
Finished Aug 07 07:43:25 PM PDT 24
Peak memory 317300 kb
Host smart-336f0c52-2aa3-412e-82ba-f986028bf25d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562995089 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.562995089
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2083116517
Short name T312
Test name
Test status
Simulation time 25939600 ps
CPU time 13.4 seconds
Started Aug 07 07:26:44 PM PDT 24
Finished Aug 07 07:26:58 PM PDT 24
Peak memory 261840 kb
Host smart-88f780a8-0718-4cb9-a569-30c3c998a1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083116517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2083116517
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.738530213
Short name T23
Test name
Test status
Simulation time 30899800 ps
CPU time 31.63 seconds
Started Aug 07 07:37:37 PM PDT 24
Finished Aug 07 07:38:09 PM PDT 24
Peak memory 273876 kb
Host smart-42d98ee2-00f7-4aee-a2a3-932a12a60fdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738530213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.738530213
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.861345148
Short name T178
Test name
Test status
Simulation time 121654500 ps
CPU time 132.51 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:44:53 PM PDT 24
Peak memory 265052 kb
Host smart-cb205082-87bf-438d-946d-c458f7b20554
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861345148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.861345148
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2435920822
Short name T80
Test name
Test status
Simulation time 338593903800 ps
CPU time 2291.36 seconds
Started Aug 07 07:33:12 PM PDT 24
Finished Aug 07 08:11:24 PM PDT 24
Peak memory 264288 kb
Host smart-e944d8e2-f213-4a60-9b2b-27c577f44a98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435920822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2435920822
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.3790712137
Short name T153
Test name
Test status
Simulation time 2844390700 ps
CPU time 285.8 seconds
Started Aug 07 07:35:31 PM PDT 24
Finished Aug 07 07:40:17 PM PDT 24
Peak memory 282104 kb
Host smart-6f4ee9c5-f9c0-450d-a993-4ec66b2ad766
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790712137 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_derr.3790712137
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.2160742545
Short name T9
Test name
Test status
Simulation time 85369300 ps
CPU time 15.22 seconds
Started Aug 07 07:32:01 PM PDT 24
Finished Aug 07 07:32:16 PM PDT 24
Peak memory 261084 kb
Host smart-818e289e-d5cb-4a34-afde-31ca734ffa29
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160742545 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.2160742545
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2251574765
Short name T175
Test name
Test status
Simulation time 98374141000 ps
CPU time 1436.77 seconds
Started Aug 07 07:32:12 PM PDT 24
Finished Aug 07 07:56:09 PM PDT 24
Peak memory 521072 kb
Host smart-00c879e0-394c-4d78-9729-6455c4f4b44f
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251574765 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2251574765
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1059446890
Short name T409
Test name
Test status
Simulation time 5406206100 ps
CPU time 205.41 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:37:41 PM PDT 24
Peak memory 277608 kb
Host smart-bbaad4d2-4346-4a1f-9ca5-698b77e41bee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059446890 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.1059446890
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3079916381
Short name T54
Test name
Test status
Simulation time 381818000 ps
CPU time 24.7 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:35:30 PM PDT 24
Peak memory 262832 kb
Host smart-33d0ef02-05f9-4716-aebf-01cd14009e4c
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079916381 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_fetch_code.3079916381
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.272292424
Short name T180
Test name
Test status
Simulation time 42672100 ps
CPU time 111.66 seconds
Started Aug 07 07:40:23 PM PDT 24
Finished Aug 07 07:42:14 PM PDT 24
Peak memory 265220 kb
Host smart-92846c8f-ea03-4d90-9d3b-35f46c171076
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272292424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.272292424
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.3292216306
Short name T416
Test name
Test status
Simulation time 29708400 ps
CPU time 13.75 seconds
Started Aug 07 07:32:11 PM PDT 24
Finished Aug 07 07:32:25 PM PDT 24
Peak memory 265328 kb
Host smart-d22323b0-a9cd-4b2d-afde-b4e87c01fb7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292216306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3
292216306
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1519195493
Short name T92
Test name
Test status
Simulation time 2675472100 ps
CPU time 72.02 seconds
Started Aug 07 07:32:23 PM PDT 24
Finished Aug 07 07:33:35 PM PDT 24
Peak memory 260996 kb
Host smart-72c4a1da-81fb-4d1d-95d7-1394d623fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519195493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1519195493
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1475972080
Short name T31
Test name
Test status
Simulation time 3240617300 ps
CPU time 61.98 seconds
Started Aug 07 07:33:35 PM PDT 24
Finished Aug 07 07:34:37 PM PDT 24
Peak memory 263944 kb
Host smart-82abfbad-f968-4b29-99d5-c15168ed2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475972080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1475972080
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.994389796
Short name T231
Test name
Test status
Simulation time 605620000 ps
CPU time 758.34 seconds
Started Aug 07 07:26:29 PM PDT 24
Finished Aug 07 07:39:07 PM PDT 24
Peak memory 264340 kb
Host smart-ca91e862-7050-4991-b364-53c31f6bef38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994389796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_tl_intg_err.994389796
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.3765118110
Short name T37
Test name
Test status
Simulation time 2795431100 ps
CPU time 168.79 seconds
Started Aug 07 07:36:27 PM PDT 24
Finished Aug 07 07:39:16 PM PDT 24
Peak memory 295300 kb
Host smart-3d00b9f9-a6a7-4963-a87f-93283929c19a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765118110 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3765118110
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1905635840
Short name T558
Test name
Test status
Simulation time 25050800 ps
CPU time 13.62 seconds
Started Aug 07 07:38:52 PM PDT 24
Finished Aug 07 07:39:05 PM PDT 24
Peak memory 260332 kb
Host smart-819473c8-451b-4e66-b121-6e76b01aa942
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905635840 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1905635840
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.2118798032
Short name T205
Test name
Test status
Simulation time 553772900 ps
CPU time 135.52 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:43:56 PM PDT 24
Peak memory 294560 kb
Host smart-956a8295-7adb-4775-bf6b-8c940af3437c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118798032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.2118798032
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.885700706
Short name T239
Test name
Test status
Simulation time 32108200 ps
CPU time 13.85 seconds
Started Aug 07 07:25:26 PM PDT 24
Finished Aug 07 07:25:40 PM PDT 24
Peak memory 263628 kb
Host smart-27ed1f9b-e90c-4faa-b704-61def04f4c91
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885700706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_mem_partial_access.885700706
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2606956982
Short name T334
Test name
Test status
Simulation time 65323600 ps
CPU time 32.92 seconds
Started Aug 07 07:32:08 PM PDT 24
Finished Aug 07 07:32:41 PM PDT 24
Peak memory 273904 kb
Host smart-6b06e167-9e3b-4cdf-9343-86c7630c1251
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606956982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2606956982
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2360701335
Short name T326
Test name
Test status
Simulation time 12231821600 ps
CPU time 275.63 seconds
Started Aug 07 07:40:08 PM PDT 24
Finished Aug 07 07:44:43 PM PDT 24
Peak memory 290232 kb
Host smart-5ecc484e-b8cd-4597-9efb-079ce76aa56c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360701335 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2360701335
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.734087376
Short name T133
Test name
Test status
Simulation time 8394762600 ps
CPU time 68.56 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:40:32 PM PDT 24
Peak memory 263724 kb
Host smart-2db2169e-09af-4dc8-bf08-4e06c4e5d507
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734087376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.734087376
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2411033255
Short name T261
Test name
Test status
Simulation time 55320600 ps
CPU time 20 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:11 PM PDT 24
Peak memory 264428 kb
Host smart-159cbaeb-ebc5-470a-a3fb-9b3c79e9dbeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411033255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
411033255
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2432393965
Short name T187
Test name
Test status
Simulation time 10011907100 ps
CPU time 131.15 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:34:25 PM PDT 24
Peak memory 362492 kb
Host smart-d535fcc5-a2cc-4f2a-a493-eb1a809cf7b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432393965 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2432393965
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.4225859612
Short name T124
Test name
Test status
Simulation time 38037887500 ps
CPU time 230.87 seconds
Started Aug 07 07:35:22 PM PDT 24
Finished Aug 07 07:39:13 PM PDT 24
Peak memory 274364 kb
Host smart-0d4cc180-89bc-4048-b1cb-89a6628a05b5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225859612 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.4225859612
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.381027888
Short name T325
Test name
Test status
Simulation time 3371744200 ps
CPU time 148.97 seconds
Started Aug 07 07:40:31 PM PDT 24
Finished Aug 07 07:43:00 PM PDT 24
Peak memory 294484 kb
Host smart-43cda2a8-07af-4f1f-9f81-4309cb413294
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381027888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.381027888
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2360981666
Short name T244
Test name
Test status
Simulation time 368406200 ps
CPU time 17.75 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:26:42 PM PDT 24
Peak memory 264324 kb
Host smart-a39ba3e8-228c-4897-bd4b-c2805378ec11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360981666 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2360981666
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.874949640
Short name T310
Test name
Test status
Simulation time 24420800 ps
CPU time 13.99 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:07 PM PDT 24
Peak memory 261796 kb
Host smart-65cdc1c9-30ae-41bf-af97-431398ff51d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874949640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.874949640
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.2493053593
Short name T210
Test name
Test status
Simulation time 1557138800 ps
CPU time 273.3 seconds
Started Aug 07 07:33:02 PM PDT 24
Finished Aug 07 07:37:36 PM PDT 24
Peak memory 285484 kb
Host smart-1d635c07-9fa7-47c1-b107-aa63f194731a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493053593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.2493053593
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.2649022030
Short name T57
Test name
Test status
Simulation time 71294500 ps
CPU time 30.6 seconds
Started Aug 07 07:33:05 PM PDT 24
Finished Aug 07 07:33:36 PM PDT 24
Peak memory 275864 kb
Host smart-30e7fe1c-a7a7-4066-b474-569f59c41818
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649022030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.2649022030
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.853802452
Short name T209
Test name
Test status
Simulation time 62011200 ps
CPU time 35.08 seconds
Started Aug 07 07:34:49 PM PDT 24
Finished Aug 07 07:35:24 PM PDT 24
Peak memory 275940 kb
Host smart-3711bf1f-519c-442b-87dd-d18b8fc75335
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853802452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_re_evict.853802452
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.2581656960
Short name T110
Test name
Test status
Simulation time 407529200 ps
CPU time 111.59 seconds
Started Aug 07 07:38:49 PM PDT 24
Finished Aug 07 07:40:41 PM PDT 24
Peak memory 264924 kb
Host smart-cac309cc-5fea-47d5-b086-0b84c4dcd777
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581656960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.2581656960
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1511079860
Short name T255
Test name
Test status
Simulation time 134532100 ps
CPU time 20.17 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:25:52 PM PDT 24
Peak memory 264388 kb
Host smart-99c4f7fe-ba1f-4962-a20d-c21e4f94b407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511079860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
511079860
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.2489208026
Short name T100
Test name
Test status
Simulation time 20181700 ps
CPU time 21.94 seconds
Started Aug 07 07:42:19 PM PDT 24
Finished Aug 07 07:42:41 PM PDT 24
Peak memory 273836 kb
Host smart-9bad43fc-5c09-4736-a9f2-e82ce87f89fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489208026 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.2489208026
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1183636596
Short name T198
Test name
Test status
Simulation time 36151700 ps
CPU time 14.12 seconds
Started Aug 07 07:33:45 PM PDT 24
Finished Aug 07 07:33:59 PM PDT 24
Peak memory 261896 kb
Host smart-a21dbff4-b390-4285-a0b1-56b1956498f1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1183636596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1183636596
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.996320387
Short name T77
Test name
Test status
Simulation time 976175900 ps
CPU time 15.68 seconds
Started Aug 07 07:32:44 PM PDT 24
Finished Aug 07 07:33:00 PM PDT 24
Peak memory 263356 kb
Host smart-9fbba042-216f-44a3-938f-2b94e51642e8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996320387 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.996320387
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3155164438
Short name T11
Test name
Test status
Simulation time 22065700 ps
CPU time 13.64 seconds
Started Aug 07 07:32:48 PM PDT 24
Finished Aug 07 07:33:02 PM PDT 24
Peak memory 261876 kb
Host smart-781eb13f-40d8-40f8-9f17-cdded55b1c29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155164438 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3155164438
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2520972985
Short name T359
Test name
Test status
Simulation time 647180400 ps
CPU time 382.73 seconds
Started Aug 07 07:26:02 PM PDT 24
Finished Aug 07 07:32:25 PM PDT 24
Peak memory 264336 kb
Host smart-a7ebaa54-191a-4484-91f3-accb4f73f0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520972985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2520972985
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.813657007
Short name T83
Test name
Test status
Simulation time 1712076700 ps
CPU time 43.84 seconds
Started Aug 07 07:33:33 PM PDT 24
Finished Aug 07 07:34:17 PM PDT 24
Peak memory 262852 kb
Host smart-7b036fe2-3ed3-4ea6-84ea-4f42a859966c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813657007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_fs_sup.813657007
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1285772093
Short name T17
Test name
Test status
Simulation time 29386800 ps
CPU time 15.97 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:37:34 PM PDT 24
Peak memory 283308 kb
Host smart-5b5b1040-c54c-49b8-9d64-98ef23dc76fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285772093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1285772093
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.3148175393
Short name T1001
Test name
Test status
Simulation time 5607949600 ps
CPU time 2299.95 seconds
Started Aug 07 07:31:51 PM PDT 24
Finished Aug 07 08:10:11 PM PDT 24
Peak memory 262304 kb
Host smart-86905f38-2eee-41f1-b6aa-7245996032ad
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148175393 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.3148175393
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1222663544
Short name T195
Test name
Test status
Simulation time 1915809700 ps
CPU time 820.77 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:46:34 PM PDT 24
Peak memory 270644 kb
Host smart-8a08a39c-39f9-4e7c-82eb-e401fd7d8f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222663544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1222663544
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1355449675
Short name T34
Test name
Test status
Simulation time 3512378100 ps
CPU time 215.99 seconds
Started Aug 07 07:37:20 PM PDT 24
Finished Aug 07 07:40:56 PM PDT 24
Peak memory 291208 kb
Host smart-b9df37fe-2dab-4efc-aa35-c10bc8334bdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355449675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1355449675
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2647063893
Short name T333
Test name
Test status
Simulation time 44038800 ps
CPU time 28.72 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:39:52 PM PDT 24
Peak memory 273880 kb
Host smart-3a3f1804-bfc8-4872-8840-52aebdb82b94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647063893 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2647063893
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3669921940
Short name T570
Test name
Test status
Simulation time 49012300 ps
CPU time 13.71 seconds
Started Aug 07 07:37:49 PM PDT 24
Finished Aug 07 07:38:02 PM PDT 24
Peak memory 260332 kb
Host smart-4e9eee77-5ed7-49e2-ba29-a5dcaf53a481
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669921940 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3669921940
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3016689530
Short name T166
Test name
Test status
Simulation time 45186000 ps
CPU time 13.96 seconds
Started Aug 07 07:32:51 PM PDT 24
Finished Aug 07 07:33:05 PM PDT 24
Peak memory 258568 kb
Host smart-6585bb43-91f4-4d9a-ac95-1cf73b57ade0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016689530 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3016689530
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2448643469
Short name T491
Test name
Test status
Simulation time 10094200400 ps
CPU time 39.09 seconds
Started Aug 07 07:37:17 PM PDT 24
Finished Aug 07 07:37:57 PM PDT 24
Peak memory 265632 kb
Host smart-c4170fa0-cf28-4512-94fa-bd50aed9f6c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448643469 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2448643469
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.621432392
Short name T356
Test name
Test status
Simulation time 661200200 ps
CPU time 894.8 seconds
Started Aug 07 07:25:19 PM PDT 24
Finished Aug 07 07:40:14 PM PDT 24
Peak memory 264304 kb
Host smart-88d70b13-bc9a-48e8-a048-8eeec0620ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621432392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.621432392
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2598708599
Short name T358
Test name
Test status
Simulation time 526103500 ps
CPU time 387.83 seconds
Started Aug 07 07:26:15 PM PDT 24
Finished Aug 07 07:32:43 PM PDT 24
Peak memory 264320 kb
Host smart-71434a62-6ed4-4284-acb5-28cf1fd3397a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598708599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2598708599
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.1067815787
Short name T388
Test name
Test status
Simulation time 1699881200 ps
CPU time 65.54 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:38:25 PM PDT 24
Peak memory 265332 kb
Host smart-0b765018-a2fd-4603-b564-f274ba352bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067815787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1067815787
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.290527483
Short name T379
Test name
Test status
Simulation time 6214484500 ps
CPU time 68.11 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:34:12 PM PDT 24
Peak memory 263680 kb
Host smart-35038660-5a6a-4f36-afd8-760a723f39cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290527483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.290527483
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1242706899
Short name T218
Test name
Test status
Simulation time 14640701400 ps
CPU time 507.34 seconds
Started Aug 07 07:31:54 PM PDT 24
Finished Aug 07 07:40:22 PM PDT 24
Peak memory 310004 kb
Host smart-a265ff6b-2fd7-4a2e-b53d-7f8a57a5de91
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242706899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1242706899
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2923689280
Short name T90
Test name
Test status
Simulation time 4190125200 ps
CPU time 609.34 seconds
Started Aug 07 07:38:01 PM PDT 24
Finished Aug 07 07:48:10 PM PDT 24
Peak memory 319396 kb
Host smart-ecb5e670-b62a-4edf-9f9b-5d80375c2c24
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923689280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.2923689280
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.88138314
Short name T63
Test name
Test status
Simulation time 15977100 ps
CPU time 13.84 seconds
Started Aug 07 07:32:48 PM PDT 24
Finished Aug 07 07:33:02 PM PDT 24
Peak memory 277484 kb
Host smart-4f483842-4b58-4d08-9f1e-4aff3179bf15
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=88138314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.88138314
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.994812250
Short name T78
Test name
Test status
Simulation time 846770200 ps
CPU time 18.41 seconds
Started Aug 07 07:33:05 PM PDT 24
Finished Aug 07 07:33:23 PM PDT 24
Peak memory 263464 kb
Host smart-30c1ac26-f49f-40f3-b39b-8256e4e8d364
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994812250 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.994812250
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2318865741
Short name T16
Test name
Test status
Simulation time 1782287900 ps
CPU time 4923.02 seconds
Started Aug 07 07:32:34 PM PDT 24
Finished Aug 07 08:54:38 PM PDT 24
Peak memory 286644 kb
Host smart-faf6b1c3-3194-442a-b198-02c6a05a08c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318865741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2318865741
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3107508164
Short name T724
Test name
Test status
Simulation time 1966572900 ps
CPU time 189.23 seconds
Started Aug 07 07:32:30 PM PDT 24
Finished Aug 07 07:35:39 PM PDT 24
Peak memory 282136 kb
Host smart-eec0f7d5-64f2-4032-bdf6-be812a7471cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107508164 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_derr_detect.3107508164
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.3041145413
Short name T81
Test name
Test status
Simulation time 101096700 ps
CPU time 21.89 seconds
Started Aug 07 07:41:39 PM PDT 24
Finished Aug 07 07:42:01 PM PDT 24
Peak memory 273884 kb
Host smart-0e6e64dd-f0c3-4c81-8136-ea0fcdf84a53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041145413 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.3041145413
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3435613899
Short name T1170
Test name
Test status
Simulation time 44454600 ps
CPU time 13.25 seconds
Started Aug 07 07:25:26 PM PDT 24
Finished Aug 07 07:25:39 PM PDT 24
Peak memory 261848 kb
Host smart-6d8210c3-c9c4-4d5a-8822-eff21b96b4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435613899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
435613899
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4180924188
Short name T272
Test name
Test status
Simulation time 1338796200 ps
CPU time 777.09 seconds
Started Aug 07 07:25:52 PM PDT 24
Finished Aug 07 07:38:49 PM PDT 24
Peak memory 264348 kb
Host smart-ad7e49e5-230a-4697-881f-70ac4ab4026c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180924188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.4180924188
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.1119127551
Short name T219
Test name
Test status
Simulation time 116711900 ps
CPU time 14.07 seconds
Started Aug 07 07:32:11 PM PDT 24
Finished Aug 07 07:32:25 PM PDT 24
Peak memory 265032 kb
Host smart-24d626c5-fb9d-4c75-9b81-2b3a7d1ece12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119127551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.1119127551
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.3418267410
Short name T1080
Test name
Test status
Simulation time 16222100 ps
CPU time 22.7 seconds
Started Aug 07 07:32:00 PM PDT 24
Finished Aug 07 07:32:23 PM PDT 24
Peak memory 273804 kb
Host smart-a13024ce-0b52-413a-85d7-d12aec6b1520
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418267410 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.3418267410
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.4049757826
Short name T330
Test name
Test status
Simulation time 49168300 ps
CPU time 13.62 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:32:27 PM PDT 24
Peak memory 260312 kb
Host smart-99182663-4075-4608-ae2e-0051d72ee48f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049757826 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.4049757826
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.1786448571
Short name T711
Test name
Test status
Simulation time 2181533600 ps
CPU time 306.06 seconds
Started Aug 07 07:32:08 PM PDT 24
Finished Aug 07 07:37:15 PM PDT 24
Peak memory 285404 kb
Host smart-0f325a90-6553-4585-a72c-67171f6b2979
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786448571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.1786448571
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.3707855661
Short name T867
Test name
Test status
Simulation time 30352600 ps
CPU time 28.68 seconds
Started Aug 07 07:32:00 PM PDT 24
Finished Aug 07 07:32:29 PM PDT 24
Peak memory 275900 kb
Host smart-fb872e03-cade-4e75-82a1-cb1864e0d77e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707855661 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.3707855661
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.4282183160
Short name T380
Test name
Test status
Simulation time 4952897400 ps
CPU time 71.81 seconds
Started Aug 07 07:32:09 PM PDT 24
Finished Aug 07 07:33:21 PM PDT 24
Peak memory 260176 kb
Host smart-379e0842-ff56-42b0-bb6a-1529f740458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282183160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.4282183160
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2941973550
Short name T920
Test name
Test status
Simulation time 86143300 ps
CPU time 29.13 seconds
Started Aug 07 07:32:36 PM PDT 24
Finished Aug 07 07:33:05 PM PDT 24
Peak memory 268072 kb
Host smart-e32d4c23-87c9-4e31-b2e4-3a5e1cb464f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941973550 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2941973550
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.533006558
Short name T366
Test name
Test status
Simulation time 10688000 ps
CPU time 22 seconds
Started Aug 07 07:37:29 PM PDT 24
Finished Aug 07 07:37:52 PM PDT 24
Peak memory 273892 kb
Host smart-601040a7-3863-423f-946e-2c0e0def5ce4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533006558 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.533006558
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.2587970123
Short name T369
Test name
Test status
Simulation time 38763900 ps
CPU time 22.46 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:38:46 PM PDT 24
Peak memory 273832 kb
Host smart-7066d5aa-34a3-4b3a-b21e-011581f8cb47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587970123 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.2587970123
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1016447464
Short name T402
Test name
Test status
Simulation time 3297743800 ps
CPU time 63.38 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:39:27 PM PDT 24
Peak memory 263692 kb
Host smart-1a002548-23f8-4271-9283-52cd78929fde
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016447464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
016447464
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1094047392
Short name T389
Test name
Test status
Simulation time 4064833800 ps
CPU time 66.54 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:39:31 PM PDT 24
Peak memory 264060 kb
Host smart-c61847de-eddd-4a8e-b7ae-8b4fa85c858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094047392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1094047392
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.4127298448
Short name T392
Test name
Test status
Simulation time 2346705100 ps
CPU time 65.54 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:39:40 PM PDT 24
Peak memory 265012 kb
Host smart-8fe8f549-95ea-4a05-9282-b754e5689c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127298448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.4127298448
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2516943018
Short name T780
Test name
Test status
Simulation time 68510900 ps
CPU time 21.63 seconds
Started Aug 07 07:38:50 PM PDT 24
Finished Aug 07 07:39:12 PM PDT 24
Peak memory 273868 kb
Host smart-0c3b60f4-cd63-453e-8481-19bc319009a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516943018 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2516943018
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2788224237
Short name T382
Test name
Test status
Simulation time 2336026000 ps
CPU time 76.25 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:40:52 PM PDT 24
Peak memory 263856 kb
Host smart-68436fd6-a7e9-434f-b527-be4506ded7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788224237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2788224237
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3112423979
Short name T42
Test name
Test status
Simulation time 2593688200 ps
CPU time 70.18 seconds
Started Aug 07 07:39:47 PM PDT 24
Finished Aug 07 07:40:57 PM PDT 24
Peak memory 263348 kb
Host smart-6199a886-902d-4641-9d20-fbf820a5ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112423979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3112423979
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3596340711
Short name T338
Test name
Test status
Simulation time 92816700 ps
CPU time 29.57 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:40:33 PM PDT 24
Peak memory 275944 kb
Host smart-aa376721-35d0-4ff0-b998-ec19ea90e24d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596340711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3596340711
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.439062881
Short name T375
Test name
Test status
Simulation time 21312800 ps
CPU time 21.88 seconds
Started Aug 07 07:33:35 PM PDT 24
Finished Aug 07 07:33:57 PM PDT 24
Peak memory 273848 kb
Host smart-1075a570-80f4-42b5-a2e0-b634f0ea8080
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439062881 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.439062881
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2575439664
Short name T385
Test name
Test status
Simulation time 5852482600 ps
CPU time 70.78 seconds
Started Aug 07 07:41:17 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 263924 kb
Host smart-b3dec80b-2e48-4d8e-ab9b-dee76acc81c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575439664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2575439664
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1187551772
Short name T337
Test name
Test status
Simulation time 2399877300 ps
CPU time 41.71 seconds
Started Aug 07 07:34:33 PM PDT 24
Finished Aug 07 07:35:14 PM PDT 24
Peak memory 265508 kb
Host smart-6bd00e4f-361c-4a29-8001-6b74cdfd0a2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187551772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1187551772
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3649441076
Short name T28
Test name
Test status
Simulation time 2879731500 ps
CPU time 74.97 seconds
Started Aug 07 07:32:03 PM PDT 24
Finished Aug 07 07:33:18 PM PDT 24
Peak memory 260896 kb
Host smart-6f36aa8c-4f78-4b86-818a-d89340b3d4e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649441076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3649441076
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.2013453945
Short name T76
Test name
Test status
Simulation time 1002903500 ps
CPU time 18.68 seconds
Started Aug 07 07:32:02 PM PDT 24
Finished Aug 07 07:32:21 PM PDT 24
Peak memory 265376 kb
Host smart-dea66e7d-9b9a-4b54-9030-0c999a8c4c2a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013453945 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2013453945
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.2640999980
Short name T202
Test name
Test status
Simulation time 1907464000 ps
CPU time 265.18 seconds
Started Aug 07 07:33:31 PM PDT 24
Finished Aug 07 07:37:57 PM PDT 24
Peak memory 286784 kb
Host smart-86dcf412-2023-4b49-810a-d0c0ace058c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640999980 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_derr.2640999980
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1140665675
Short name T173
Test name
Test status
Simulation time 210190391900 ps
CPU time 1007.67 seconds
Started Aug 07 07:35:23 PM PDT 24
Finished Aug 07 07:52:11 PM PDT 24
Peak memory 265176 kb
Host smart-ac4ddb8c-6294-4149-bcd9-0ef83e33b9fe
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140665675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1140665675
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2326706969
Short name T103
Test name
Test status
Simulation time 226173900 ps
CPU time 14.9 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:40 PM PDT 24
Peak memory 272604 kb
Host smart-b85f1e94-ebea-4836-be7b-186fa8f10fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326706969 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2326706969
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.2139347012
Short name T204
Test name
Test status
Simulation time 16131897500 ps
CPU time 250.02 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:40:08 PM PDT 24
Peak memory 295412 kb
Host smart-9d96195e-bf74-444d-a2de-e866f6e004c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139347012 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.flash_ctrl_rw_serr.2139347012
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2419974990
Short name T257
Test name
Test status
Simulation time 71459900 ps
CPU time 17.42 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:26:22 PM PDT 24
Peak memory 263908 kb
Host smart-05814b6e-406f-4944-be1a-de9fef227d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419974990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2419974990
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4165107052
Short name T264
Test name
Test status
Simulation time 657603900 ps
CPU time 381.47 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:32:46 PM PDT 24
Peak memory 264324 kb
Host smart-85ac8070-7a8d-4596-b82e-103bbfbc2f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165107052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.4165107052
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3901736156
Short name T275
Test name
Test status
Simulation time 421888700 ps
CPU time 456.82 seconds
Started Aug 07 07:26:35 PM PDT 24
Finished Aug 07 07:34:13 PM PDT 24
Peak memory 264300 kb
Host smart-e11efc9a-f93f-412f-b0c3-b65d8a5bd6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901736156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.3901736156
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.1025588274
Short name T227
Test name
Test status
Simulation time 6368300500 ps
CPU time 2428.76 seconds
Started Aug 07 07:31:54 PM PDT 24
Finished Aug 07 08:12:23 PM PDT 24
Peak memory 265400 kb
Host smart-d457602b-948e-417b-a3b5-92c843b6e175
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1025588274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.1025588274
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3350420074
Short name T55
Test name
Test status
Simulation time 117775000 ps
CPU time 22.05 seconds
Started Aug 07 07:31:58 PM PDT 24
Finished Aug 07 07:32:21 PM PDT 24
Peak memory 263980 kb
Host smart-c361824b-95e1-48ad-a29f-7801b48ef82b
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350420074 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_fetch_code.3350420074
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3260575238
Short name T112
Test name
Test status
Simulation time 334680770600 ps
CPU time 2388.05 seconds
Started Aug 07 07:31:50 PM PDT 24
Finished Aug 07 08:11:38 PM PDT 24
Peak memory 264304 kb
Host smart-94bb7eca-a5a4-41ae-b68c-aed3832870dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260575238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.3260575238
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.4137020904
Short name T277
Test name
Test status
Simulation time 158259700 ps
CPU time 60.99 seconds
Started Aug 07 07:31:49 PM PDT 24
Finished Aug 07 07:32:50 PM PDT 24
Peak memory 262984 kb
Host smart-419bc9de-5d4e-46f5-860b-d823cc4e5b7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137020904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.4137020904
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1071199681
Short name T183
Test name
Test status
Simulation time 247053187600 ps
CPU time 2670.99 seconds
Started Aug 07 07:32:21 PM PDT 24
Finished Aug 07 08:16:53 PM PDT 24
Peak memory 264224 kb
Host smart-c52d6f69-3dec-4f47-a131-f62ec6c004d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071199681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1071199681
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.1137259510
Short name T215
Test name
Test status
Simulation time 223305700 ps
CPU time 32.59 seconds
Started Aug 07 07:38:13 PM PDT 24
Finished Aug 07 07:38:46 PM PDT 24
Peak memory 276240 kb
Host smart-6a1b650c-043d-44aa-acd8-c996c5c9a4ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137259510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.1137259510
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.904564318
Short name T96
Test name
Test status
Simulation time 52080500 ps
CPU time 15.18 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:33:19 PM PDT 24
Peak memory 261024 kb
Host smart-d224f723-a00c-4624-a55f-4e2adaafcc41
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904564318 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.904564318
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.865007920
Short name T207
Test name
Test status
Simulation time 573659900 ps
CPU time 128.52 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:38:06 PM PDT 24
Peak memory 295560 kb
Host smart-3754b273-c99e-4de3-a738-78454723fff4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865007920 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.865007920
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1208750092
Short name T1223
Test name
Test status
Simulation time 1786774900 ps
CPU time 38.72 seconds
Started Aug 07 07:25:27 PM PDT 24
Finished Aug 07 07:26:05 PM PDT 24
Peak memory 261676 kb
Host smart-d01ecbcd-264e-4aac-9dbf-d1c8c2cd9f67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208750092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1208750092
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1998338478
Short name T1134
Test name
Test status
Simulation time 669938000 ps
CPU time 42.28 seconds
Started Aug 07 07:25:19 PM PDT 24
Finished Aug 07 07:26:01 PM PDT 24
Peak memory 261908 kb
Host smart-9e7c3c2a-a22a-4102-9ba3-3dfe5ed4a710
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998338478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.1998338478
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.352103741
Short name T1149
Test name
Test status
Simulation time 27298600 ps
CPU time 45.58 seconds
Started Aug 07 07:25:15 PM PDT 24
Finished Aug 07 07:26:01 PM PDT 24
Peak memory 261768 kb
Host smart-8aa675b4-11af-4c3f-8311-61049d626bed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352103741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_hw_reset.352103741
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2835183802
Short name T1145
Test name
Test status
Simulation time 27293800 ps
CPU time 17.61 seconds
Started Aug 07 07:25:27 PM PDT 24
Finished Aug 07 07:25:44 PM PDT 24
Peak memory 264168 kb
Host smart-13c070da-6363-4e48-8bfe-69f79f01319b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835183802 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.2835183802
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.65344907
Short name T105
Test name
Test status
Simulation time 32254400 ps
CPU time 17.57 seconds
Started Aug 07 07:25:17 PM PDT 24
Finished Aug 07 07:25:34 PM PDT 24
Peak memory 261824 kb
Host smart-55d172e8-3fd9-461c-b867-ced917fb0d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65344907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_csr_rw.65344907
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3995067778
Short name T1169
Test name
Test status
Simulation time 26360800 ps
CPU time 13.51 seconds
Started Aug 07 07:25:13 PM PDT 24
Finished Aug 07 07:25:27 PM PDT 24
Peak memory 261840 kb
Host smart-ae12c5a7-87cf-4ff5-845d-8c6ed6de6815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995067778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
995067778
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2381322582
Short name T241
Test name
Test status
Simulation time 18540500 ps
CPU time 13.46 seconds
Started Aug 07 07:25:16 PM PDT 24
Finished Aug 07 07:25:30 PM PDT 24
Peak memory 262748 kb
Host smart-df4ff264-5d2c-489e-b892-83b9b215c7a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381322582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2381322582
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2392125574
Short name T1133
Test name
Test status
Simulation time 27708900 ps
CPU time 13.39 seconds
Started Aug 07 07:25:15 PM PDT 24
Finished Aug 07 07:25:28 PM PDT 24
Peak memory 261760 kb
Host smart-4bd8289c-3db0-4eda-a864-35e9f5cf3cfc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392125574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2392125574
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2019379559
Short name T296
Test name
Test status
Simulation time 335658800 ps
CPU time 18.61 seconds
Started Aug 07 07:25:22 PM PDT 24
Finished Aug 07 07:25:40 PM PDT 24
Peak memory 264116 kb
Host smart-5350fe68-4d73-4f78-a012-4574ed16bd19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019379559 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.2019379559
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1937401164
Short name T1235
Test name
Test status
Simulation time 37188100 ps
CPU time 13.39 seconds
Started Aug 07 07:25:15 PM PDT 24
Finished Aug 07 07:25:28 PM PDT 24
Peak memory 253544 kb
Host smart-955422fc-4f7f-4d39-995d-07ed2ae98a40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937401164 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1937401164
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3447211659
Short name T1159
Test name
Test status
Simulation time 31657600 ps
CPU time 15.62 seconds
Started Aug 07 07:25:14 PM PDT 24
Finished Aug 07 07:25:30 PM PDT 24
Peak memory 253656 kb
Host smart-726035f6-563e-44ea-b925-6092b3702e94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447211659 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3447211659
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3730112600
Short name T220
Test name
Test status
Simulation time 147636900 ps
CPU time 17.35 seconds
Started Aug 07 07:25:11 PM PDT 24
Finished Aug 07 07:25:28 PM PDT 24
Peak memory 264372 kb
Host smart-dd70464c-849d-4ac1-9b6b-02233a0e6e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730112600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3
730112600
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2030862843
Short name T362
Test name
Test status
Simulation time 432381100 ps
CPU time 33.16 seconds
Started Aug 07 07:25:24 PM PDT 24
Finished Aug 07 07:25:57 PM PDT 24
Peak memory 261776 kb
Host smart-407f4ea1-1f68-4785-af11-b193f81e98fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030862843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2030862843
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.4089810145
Short name T1243
Test name
Test status
Simulation time 2530700500 ps
CPU time 61.04 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:26:33 PM PDT 24
Peak memory 261676 kb
Host smart-8feb6dbb-0ee9-4a9f-971c-1c2db748dd9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089810145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.4089810145
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3359170266
Short name T1198
Test name
Test status
Simulation time 68101400 ps
CPU time 30.42 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:26:02 PM PDT 24
Peak memory 263472 kb
Host smart-6045ab64-215f-4305-a342-c0f888145fad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359170266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3359170266
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2504261713
Short name T1212
Test name
Test status
Simulation time 97194400 ps
CPU time 17.35 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:25:49 PM PDT 24
Peak memory 272604 kb
Host smart-918a6777-b560-469e-844d-14387acb6243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504261713 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2504261713
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2686250566
Short name T297
Test name
Test status
Simulation time 89501200 ps
CPU time 16.92 seconds
Started Aug 07 07:25:27 PM PDT 24
Finished Aug 07 07:25:44 PM PDT 24
Peak memory 264276 kb
Host smart-fe7ffdab-b9cd-41a8-9fcb-79bea8de717d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686250566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.2686250566
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.421205831
Short name T1160
Test name
Test status
Simulation time 34851200 ps
CPU time 13.51 seconds
Started Aug 07 07:25:22 PM PDT 24
Finished Aug 07 07:25:35 PM PDT 24
Peak memory 261648 kb
Host smart-214110bf-047c-416f-ac43-d08e363587d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421205831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.421205831
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2711575268
Short name T1234
Test name
Test status
Simulation time 613552300 ps
CPU time 18.47 seconds
Started Aug 07 07:25:24 PM PDT 24
Finished Aug 07 07:25:43 PM PDT 24
Peak memory 261972 kb
Host smart-28c468e5-b4b5-4b58-84f5-4bebb878e6d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711575268 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2711575268
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2428522353
Short name T1173
Test name
Test status
Simulation time 13371100 ps
CPU time 15.69 seconds
Started Aug 07 07:25:27 PM PDT 24
Finished Aug 07 07:25:43 PM PDT 24
Peak memory 253636 kb
Host smart-5e063447-9509-460e-b3f2-21707e492fc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428522353 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2428522353
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.688042829
Short name T1214
Test name
Test status
Simulation time 34305700 ps
CPU time 15.86 seconds
Started Aug 07 07:25:22 PM PDT 24
Finished Aug 07 07:25:38 PM PDT 24
Peak memory 253724 kb
Host smart-133deb41-20a3-453a-9f8c-3b4ba6619883
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688042829 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.688042829
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3543884393
Short name T267
Test name
Test status
Simulation time 32016700 ps
CPU time 15.9 seconds
Started Aug 07 07:25:24 PM PDT 24
Finished Aug 07 07:25:40 PM PDT 24
Peak memory 263692 kb
Host smart-f7436635-131e-474c-acd3-4cb7f29aba9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543884393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
543884393
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3225075505
Short name T360
Test name
Test status
Simulation time 459164100 ps
CPU time 383.83 seconds
Started Aug 07 07:25:24 PM PDT 24
Finished Aug 07 07:31:48 PM PDT 24
Peak memory 264252 kb
Host smart-ec0a3e22-7601-46f8-91ad-9343082b436d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225075505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3225075505
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2766371579
Short name T293
Test name
Test status
Simulation time 984674200 ps
CPU time 17.68 seconds
Started Aug 07 07:26:15 PM PDT 24
Finished Aug 07 07:26:33 PM PDT 24
Peak memory 272600 kb
Host smart-7c240ee2-d478-42ff-bd3c-125a3a600faa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766371579 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2766371579
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.291357993
Short name T249
Test name
Test status
Simulation time 37249300 ps
CPU time 14.05 seconds
Started Aug 07 07:26:03 PM PDT 24
Finished Aug 07 07:26:17 PM PDT 24
Peak memory 261836 kb
Host smart-baceb499-13d7-4084-8bb9-e0b897bfb3f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291357993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.291357993
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1548212668
Short name T1155
Test name
Test status
Simulation time 28871700 ps
CPU time 13.57 seconds
Started Aug 07 07:26:03 PM PDT 24
Finished Aug 07 07:26:17 PM PDT 24
Peak memory 261848 kb
Host smart-0773b507-19ce-43fc-b417-4d29370420ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548212668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1548212668
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1079208617
Short name T1189
Test name
Test status
Simulation time 300540400 ps
CPU time 19.8 seconds
Started Aug 07 07:26:13 PM PDT 24
Finished Aug 07 07:26:33 PM PDT 24
Peak memory 263176 kb
Host smart-2dfe6be7-ad0f-4d21-9962-0fc4d8550306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079208617 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1079208617
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.138159379
Short name T1178
Test name
Test status
Simulation time 22813500 ps
CPU time 15.63 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:26:20 PM PDT 24
Peak memory 253660 kb
Host smart-36315eaa-3472-4ace-abd1-c3de3b4f5fa5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138159379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.138159379
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.351777030
Short name T1202
Test name
Test status
Simulation time 32504000 ps
CPU time 16.11 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:26:22 PM PDT 24
Peak memory 253736 kb
Host smart-978d2019-88c1-4407-ad5b-d1ff4872e0e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351777030 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.351777030
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2709708972
Short name T354
Test name
Test status
Simulation time 702678600 ps
CPU time 896.77 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:41:02 PM PDT 24
Peak memory 263840 kb
Host smart-8bda7ccc-af76-48d3-a76d-02b088414889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709708972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.2709708972
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2162607592
Short name T292
Test name
Test status
Simulation time 355273700 ps
CPU time 16.45 seconds
Started Aug 07 07:26:14 PM PDT 24
Finished Aug 07 07:26:30 PM PDT 24
Peak memory 270988 kb
Host smart-ef54ddf4-6198-4fda-b5dd-ea8f0098623a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162607592 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2162607592
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2659994933
Short name T1151
Test name
Test status
Simulation time 56464600 ps
CPU time 17.51 seconds
Started Aug 07 07:26:16 PM PDT 24
Finished Aug 07 07:26:33 PM PDT 24
Peak memory 264264 kb
Host smart-d83c059c-325f-4a4d-bd98-9124a6ed72da
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659994933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.2659994933
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1832397199
Short name T1140
Test name
Test status
Simulation time 51976400 ps
CPU time 13.58 seconds
Started Aug 07 07:26:15 PM PDT 24
Finished Aug 07 07:26:28 PM PDT 24
Peak memory 261852 kb
Host smart-4adbb928-7a76-4b09-a829-7b8e4217b5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832397199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1832397199
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.705100259
Short name T1209
Test name
Test status
Simulation time 62189800 ps
CPU time 29.39 seconds
Started Aug 07 07:26:13 PM PDT 24
Finished Aug 07 07:26:43 PM PDT 24
Peak memory 261892 kb
Host smart-54f58230-08db-4667-85bf-9dca557a9b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705100259 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.705100259
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2017321998
Short name T1127
Test name
Test status
Simulation time 152013100 ps
CPU time 13.26 seconds
Started Aug 07 07:26:16 PM PDT 24
Finished Aug 07 07:26:29 PM PDT 24
Peak memory 253724 kb
Host smart-4ed6a7f1-6a43-4973-aeef-80188fde08c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017321998 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2017321998
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1760062069
Short name T1246
Test name
Test status
Simulation time 14134300 ps
CPU time 15.5 seconds
Started Aug 07 07:26:12 PM PDT 24
Finished Aug 07 07:26:28 PM PDT 24
Peak memory 253700 kb
Host smart-374f6e75-cc7e-4b09-9343-5b9685a11a0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760062069 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1760062069
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4244429408
Short name T230
Test name
Test status
Simulation time 60440000 ps
CPU time 16.46 seconds
Started Aug 07 07:26:15 PM PDT 24
Finished Aug 07 07:26:31 PM PDT 24
Peak memory 264412 kb
Host smart-c9b0395f-ae69-4800-82b7-0a5be6051375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244429408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
4244429408
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3027961821
Short name T1166
Test name
Test status
Simulation time 245412600 ps
CPU time 19.02 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:45 PM PDT 24
Peak memory 272588 kb
Host smart-5e9b745d-d0cc-4bbb-b1fc-2ab7e97555ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027961821 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3027961821
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1676663959
Short name T242
Test name
Test status
Simulation time 76595900 ps
CPU time 17.38 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:42 PM PDT 24
Peak memory 264292 kb
Host smart-73438324-140e-4e09-b1d0-c45f80979590
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676663959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1676663959
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1856831209
Short name T259
Test name
Test status
Simulation time 44715200 ps
CPU time 13.71 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:39 PM PDT 24
Peak memory 261848 kb
Host smart-90b92203-ea0f-4111-a38d-848b3d13d30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856831209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
1856831209
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1675445053
Short name T1251
Test name
Test status
Simulation time 341198000 ps
CPU time 19.84 seconds
Started Aug 07 07:26:26 PM PDT 24
Finished Aug 07 07:26:46 PM PDT 24
Peak memory 264340 kb
Host smart-466b3bf4-43ec-4ef3-aa29-98335acdce64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675445053 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1675445053
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1983159014
Short name T1146
Test name
Test status
Simulation time 92356400 ps
CPU time 16.21 seconds
Started Aug 07 07:26:13 PM PDT 24
Finished Aug 07 07:26:30 PM PDT 24
Peak memory 253656 kb
Host smart-f6c30ae2-9883-425f-a488-e7df058b95c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983159014 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1983159014
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3145361171
Short name T1201
Test name
Test status
Simulation time 48840300 ps
CPU time 15.9 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:26:40 PM PDT 24
Peak memory 253668 kb
Host smart-b67e5bf2-f555-4afe-b1a7-c0b0766cbc47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145361171 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3145361171
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.823818041
Short name T263
Test name
Test status
Simulation time 126003900 ps
CPU time 17.32 seconds
Started Aug 07 07:26:13 PM PDT 24
Finished Aug 07 07:26:30 PM PDT 24
Peak memory 264372 kb
Host smart-b46d8769-95ec-41ee-9be4-875e99fdab22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823818041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.823818041
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2760253627
Short name T357
Test name
Test status
Simulation time 183756100 ps
CPU time 463.44 seconds
Started Aug 07 07:26:13 PM PDT 24
Finished Aug 07 07:33:57 PM PDT 24
Peak memory 264268 kb
Host smart-2396fedf-8104-4c37-9571-90329aececad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760253627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2760253627
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1709827266
Short name T1247
Test name
Test status
Simulation time 90611200 ps
CPU time 19.21 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:26:43 PM PDT 24
Peak memory 272592 kb
Host smart-1d1ef693-d752-42e7-aa1d-2ee809bb1f9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709827266 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1709827266
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.470843787
Short name T1168
Test name
Test status
Simulation time 175822400 ps
CPU time 14.6 seconds
Started Aug 07 07:26:26 PM PDT 24
Finished Aug 07 07:26:41 PM PDT 24
Peak memory 262104 kb
Host smart-1a901959-1e2c-4a74-8a01-c46b9f4c845b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470843787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.470843787
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.166299210
Short name T1244
Test name
Test status
Simulation time 26122800 ps
CPU time 13.4 seconds
Started Aug 07 07:26:26 PM PDT 24
Finished Aug 07 07:26:39 PM PDT 24
Peak memory 261848 kb
Host smart-ce54e56d-9da3-4c8c-939d-7a4cf31f2e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166299210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.166299210
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3369049526
Short name T1136
Test name
Test status
Simulation time 82490300 ps
CPU time 29.04 seconds
Started Aug 07 07:26:26 PM PDT 24
Finished Aug 07 07:26:55 PM PDT 24
Peak memory 264400 kb
Host smart-635c19f6-09ec-4ecf-bd82-ce8157ac0bad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369049526 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.3369049526
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4021271291
Short name T1182
Test name
Test status
Simulation time 25170600 ps
CPU time 15.46 seconds
Started Aug 07 07:26:23 PM PDT 24
Finished Aug 07 07:26:39 PM PDT 24
Peak memory 253700 kb
Host smart-770e8871-af58-4d50-a08b-f3a8bcf5af4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021271291 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.4021271291
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4019786596
Short name T1125
Test name
Test status
Simulation time 16655000 ps
CPU time 16.01 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:26:40 PM PDT 24
Peak memory 253716 kb
Host smart-62d6d2c4-34e3-4427-9622-195621f3c323
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019786596 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.4019786596
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1433857525
Short name T1206
Test name
Test status
Simulation time 95216500 ps
CPU time 18.85 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:26:43 PM PDT 24
Peak memory 264424 kb
Host smart-5b21d70a-cc94-4c4a-ae32-af4b85162105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433857525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
1433857525
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1154898733
Short name T1233
Test name
Test status
Simulation time 152839400 ps
CPU time 14.77 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:40 PM PDT 24
Peak memory 264276 kb
Host smart-7ea0bc78-17c5-4cc9-a773-6b59021b4f3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154898733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1154898733
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1495336860
Short name T1123
Test name
Test status
Simulation time 74287300 ps
CPU time 13.56 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:39 PM PDT 24
Peak memory 261812 kb
Host smart-68f01dfb-1caf-40e6-ba72-9d3c0f656930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495336860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
1495336860
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.621805232
Short name T1121
Test name
Test status
Simulation time 11295000 ps
CPU time 15.55 seconds
Started Aug 07 07:26:24 PM PDT 24
Finished Aug 07 07:26:40 PM PDT 24
Peak memory 253608 kb
Host smart-fe82d9c4-2d0d-4142-ab86-0f20106a71e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621805232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.621805232
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.975755084
Short name T1220
Test name
Test status
Simulation time 19783400 ps
CPU time 15.72 seconds
Started Aug 07 07:26:28 PM PDT 24
Finished Aug 07 07:26:44 PM PDT 24
Peak memory 253740 kb
Host smart-d4a66d42-f487-4830-8350-1a301c821741
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975755084 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.975755084
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1069871403
Short name T1236
Test name
Test status
Simulation time 77923200 ps
CPU time 18.99 seconds
Started Aug 07 07:26:34 PM PDT 24
Finished Aug 07 07:26:53 PM PDT 24
Peak memory 271960 kb
Host smart-8cc6a783-3fe0-4231-be3b-db54e5e1a75d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069871403 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1069871403
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4226824006
Short name T1171
Test name
Test status
Simulation time 27811300 ps
CPU time 16.57 seconds
Started Aug 07 07:26:36 PM PDT 24
Finished Aug 07 07:26:53 PM PDT 24
Peak memory 261728 kb
Host smart-9e9edade-5f64-437d-901e-3dd2a1d33b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226824006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.4226824006
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2301443185
Short name T1224
Test name
Test status
Simulation time 50092800 ps
CPU time 13.5 seconds
Started Aug 07 07:26:34 PM PDT 24
Finished Aug 07 07:26:48 PM PDT 24
Peak memory 261828 kb
Host smart-247dda4a-7d09-4c97-9fa8-31dbc99d4c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301443185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
2301443185
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2527884509
Short name T1241
Test name
Test status
Simulation time 364321800 ps
CPU time 34.46 seconds
Started Aug 07 07:26:36 PM PDT 24
Finished Aug 07 07:27:11 PM PDT 24
Peak memory 263220 kb
Host smart-71def6b2-05a8-4899-9c39-403d113f8e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527884509 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2527884509
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4206206455
Short name T1147
Test name
Test status
Simulation time 20805400 ps
CPU time 15.57 seconds
Started Aug 07 07:26:25 PM PDT 24
Finished Aug 07 07:26:41 PM PDT 24
Peak memory 253528 kb
Host smart-785be542-ad1a-4ce5-85a1-2617dbd41552
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206206455 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.4206206455
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.481833790
Short name T1176
Test name
Test status
Simulation time 41762200 ps
CPU time 13.36 seconds
Started Aug 07 07:26:26 PM PDT 24
Finished Aug 07 07:26:39 PM PDT 24
Peak memory 253708 kb
Host smart-f85159b5-4931-4e32-989b-e8506b720b48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481833790 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.481833790
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2349632160
Short name T260
Test name
Test status
Simulation time 124693200 ps
CPU time 19.13 seconds
Started Aug 07 07:26:26 PM PDT 24
Finished Aug 07 07:26:45 PM PDT 24
Peak memory 264380 kb
Host smart-db20e51a-7bf1-44e0-b9cb-319fb1c2bee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349632160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2349632160
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3199113203
Short name T1218
Test name
Test status
Simulation time 191925000 ps
CPU time 14.85 seconds
Started Aug 07 07:26:36 PM PDT 24
Finished Aug 07 07:26:51 PM PDT 24
Peak memory 264408 kb
Host smart-787f76a2-767b-42af-8590-65a27f18b090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199113203 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3199113203
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1402176481
Short name T1253
Test name
Test status
Simulation time 71400000 ps
CPU time 17.94 seconds
Started Aug 07 07:26:36 PM PDT 24
Finished Aug 07 07:26:55 PM PDT 24
Peak memory 264292 kb
Host smart-f52be155-1321-49f2-a1bd-9fd32ad134bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402176481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1402176481
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2660838891
Short name T1144
Test name
Test status
Simulation time 54101800 ps
CPU time 13.64 seconds
Started Aug 07 07:26:34 PM PDT 24
Finished Aug 07 07:26:48 PM PDT 24
Peak memory 261804 kb
Host smart-1a5c82c4-e1c7-4582-bc28-f39a27dfcf5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660838891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
2660838891
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2667520576
Short name T248
Test name
Test status
Simulation time 125367900 ps
CPU time 30.28 seconds
Started Aug 07 07:26:33 PM PDT 24
Finished Aug 07 07:27:04 PM PDT 24
Peak memory 263152 kb
Host smart-5aba384b-4c77-48b1-a7e8-b9a7e45b0749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667520576 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2667520576
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1320097073
Short name T1213
Test name
Test status
Simulation time 32430300 ps
CPU time 15.61 seconds
Started Aug 07 07:26:35 PM PDT 24
Finished Aug 07 07:26:50 PM PDT 24
Peak memory 253720 kb
Host smart-06568be2-22f8-4693-86c8-dfe438814a71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320097073 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1320097073
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3816378592
Short name T1117
Test name
Test status
Simulation time 22564400 ps
CPU time 15.33 seconds
Started Aug 07 07:26:33 PM PDT 24
Finished Aug 07 07:26:48 PM PDT 24
Peak memory 253652 kb
Host smart-b1aff9ca-edb7-4cbe-8a98-d573f2451b96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816378592 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.3816378592
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2013687458
Short name T270
Test name
Test status
Simulation time 40133000 ps
CPU time 16.86 seconds
Started Aug 07 07:26:34 PM PDT 24
Finished Aug 07 07:26:51 PM PDT 24
Peak memory 264396 kb
Host smart-a2596b14-88e9-48e2-b7c5-8ccfd0068ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013687458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
2013687458
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1961237627
Short name T1152
Test name
Test status
Simulation time 309705600 ps
CPU time 16.85 seconds
Started Aug 07 07:26:42 PM PDT 24
Finished Aug 07 07:26:59 PM PDT 24
Peak memory 272588 kb
Host smart-753f5b45-5846-4781-ba77-b26c416ddd09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961237627 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1961237627
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1306237995
Short name T1215
Test name
Test status
Simulation time 212113600 ps
CPU time 17.98 seconds
Started Aug 07 07:26:37 PM PDT 24
Finished Aug 07 07:26:55 PM PDT 24
Peak memory 261828 kb
Host smart-d6b97b42-e358-4fd2-bbc7-11042e299d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306237995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1306237995
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.709496849
Short name T1158
Test name
Test status
Simulation time 76215700 ps
CPU time 13.51 seconds
Started Aug 07 07:26:36 PM PDT 24
Finished Aug 07 07:26:49 PM PDT 24
Peak memory 261764 kb
Host smart-ed3a28eb-7a10-448d-ae38-6bc4152c5d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709496849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.709496849
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3985760774
Short name T247
Test name
Test status
Simulation time 62718100 ps
CPU time 34.33 seconds
Started Aug 07 07:26:44 PM PDT 24
Finished Aug 07 07:27:19 PM PDT 24
Peak memory 261792 kb
Host smart-d918f4f8-5d10-4383-b081-caf16fc469e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985760774 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3985760774
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4201328201
Short name T1137
Test name
Test status
Simulation time 51219100 ps
CPU time 15.67 seconds
Started Aug 07 07:26:35 PM PDT 24
Finished Aug 07 07:26:51 PM PDT 24
Peak memory 253748 kb
Host smart-c8180d6a-4d0b-416c-8c70-e0d6089924b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201328201 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.4201328201
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.583031400
Short name T1237
Test name
Test status
Simulation time 14195900 ps
CPU time 15.95 seconds
Started Aug 07 07:26:34 PM PDT 24
Finished Aug 07 07:26:50 PM PDT 24
Peak memory 253164 kb
Host smart-75165a77-4f65-4f49-9c2f-782eb4fe095c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583031400 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.583031400
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.21750701
Short name T1240
Test name
Test status
Simulation time 178726300 ps
CPU time 16.43 seconds
Started Aug 07 07:26:34 PM PDT 24
Finished Aug 07 07:26:50 PM PDT 24
Peak memory 264384 kb
Host smart-f59593a9-8096-4c33-acc7-059643dd5a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21750701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.21750701
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.419253852
Short name T1250
Test name
Test status
Simulation time 1493093800 ps
CPU time 905.02 seconds
Started Aug 07 07:26:36 PM PDT 24
Finished Aug 07 07:41:42 PM PDT 24
Peak memory 264440 kb
Host smart-87e917f5-f6a3-4672-893f-df07117a7114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419253852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.419253852
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1161153029
Short name T295
Test name
Test status
Simulation time 100208500 ps
CPU time 19.06 seconds
Started Aug 07 07:26:46 PM PDT 24
Finished Aug 07 07:27:05 PM PDT 24
Peak memory 270860 kb
Host smart-90f4d5b2-72dd-4703-aa31-fc549b5e6f3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161153029 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1161153029
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.110167672
Short name T1197
Test name
Test status
Simulation time 50092800 ps
CPU time 14.76 seconds
Started Aug 07 07:26:45 PM PDT 24
Finished Aug 07 07:27:00 PM PDT 24
Peak memory 264252 kb
Host smart-c17c6e40-ee17-46bc-8aca-8a3a400fedaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110167672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_csr_rw.110167672
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4009682743
Short name T1225
Test name
Test status
Simulation time 117630600 ps
CPU time 29.55 seconds
Started Aug 07 07:26:42 PM PDT 24
Finished Aug 07 07:27:12 PM PDT 24
Peak memory 263188 kb
Host smart-36060294-d567-4b0f-add3-159325de1c18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009682743 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.4009682743
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3191198584
Short name T1130
Test name
Test status
Simulation time 20072600 ps
CPU time 15.84 seconds
Started Aug 07 07:26:42 PM PDT 24
Finished Aug 07 07:26:58 PM PDT 24
Peak memory 253692 kb
Host smart-224985fb-ad22-46f6-9d56-f86877ed43f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191198584 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.3191198584
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.858075575
Short name T1128
Test name
Test status
Simulation time 20471100 ps
CPU time 15.5 seconds
Started Aug 07 07:26:42 PM PDT 24
Finished Aug 07 07:26:57 PM PDT 24
Peak memory 253652 kb
Host smart-ea3cb2a7-d186-41b3-844d-4dc4e7559db4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858075575 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.858075575
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1817199180
Short name T269
Test name
Test status
Simulation time 186148500 ps
CPU time 19.45 seconds
Started Aug 07 07:26:46 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 264352 kb
Host smart-1d2714ba-34a3-4a17-b5e9-904524f3698e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817199180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
1817199180
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2400172939
Short name T355
Test name
Test status
Simulation time 1289561100 ps
CPU time 914.35 seconds
Started Aug 07 07:26:45 PM PDT 24
Finished Aug 07 07:41:59 PM PDT 24
Peak memory 264332 kb
Host smart-9bed65c8-b80c-4f9b-8cc4-e7d0e16dfa3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400172939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2400172939
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2432183942
Short name T233
Test name
Test status
Simulation time 82988100 ps
CPU time 18.69 seconds
Started Aug 07 07:26:43 PM PDT 24
Finished Aug 07 07:27:02 PM PDT 24
Peak memory 272564 kb
Host smart-ccc47498-6767-4d20-8c4f-c1fde138beaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432183942 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2432183942
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3549755299
Short name T1156
Test name
Test status
Simulation time 45904900 ps
CPU time 16.46 seconds
Started Aug 07 07:26:43 PM PDT 24
Finished Aug 07 07:27:00 PM PDT 24
Peak memory 261592 kb
Host smart-3d45ac6d-31ed-4fff-bbd1-df54fb65227f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549755299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3549755299
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4268291590
Short name T315
Test name
Test status
Simulation time 39335900 ps
CPU time 13.43 seconds
Started Aug 07 07:26:42 PM PDT 24
Finished Aug 07 07:26:55 PM PDT 24
Peak memory 261852 kb
Host smart-fb3ca825-ddf6-4c40-8066-9f945cd3ddee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268291590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
4268291590
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1462737115
Short name T1200
Test name
Test status
Simulation time 434845900 ps
CPU time 35.87 seconds
Started Aug 07 07:26:43 PM PDT 24
Finished Aug 07 07:27:19 PM PDT 24
Peak memory 264296 kb
Host smart-c2644ff4-318c-4fae-b08b-bdea4aac6548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462737115 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1462737115
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4056652914
Short name T1203
Test name
Test status
Simulation time 23896800 ps
CPU time 15.79 seconds
Started Aug 07 07:26:44 PM PDT 24
Finished Aug 07 07:27:00 PM PDT 24
Peak memory 253668 kb
Host smart-f227eb68-ac76-4001-96c2-cf1b1218275c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056652914 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.4056652914
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2414188045
Short name T1161
Test name
Test status
Simulation time 23369500 ps
CPU time 16.04 seconds
Started Aug 07 07:26:43 PM PDT 24
Finished Aug 07 07:26:59 PM PDT 24
Peak memory 253576 kb
Host smart-d754e5d6-42d8-45a4-a80b-49cee3735be8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414188045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2414188045
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3671826642
Short name T1229
Test name
Test status
Simulation time 378114700 ps
CPU time 17.2 seconds
Started Aug 07 07:26:44 PM PDT 24
Finished Aug 07 07:27:01 PM PDT 24
Peak memory 264404 kb
Host smart-8b4c48f1-87c4-431b-b709-6546170cf10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671826642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3671826642
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1245940604
Short name T266
Test name
Test status
Simulation time 1319179100 ps
CPU time 767.69 seconds
Started Aug 07 07:26:43 PM PDT 24
Finished Aug 07 07:39:31 PM PDT 24
Peak memory 264320 kb
Host smart-4c94439a-a43c-4c9a-a059-2c24252a0510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245940604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1245940604
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2348231669
Short name T1208
Test name
Test status
Simulation time 826926300 ps
CPU time 33.32 seconds
Started Aug 07 07:25:31 PM PDT 24
Finished Aug 07 07:26:05 PM PDT 24
Peak memory 261864 kb
Host smart-7d718612-e3e2-442d-985a-74c61339d0e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348231669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2348231669
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.729326151
Short name T254
Test name
Test status
Simulation time 24794128500 ps
CPU time 94.47 seconds
Started Aug 07 07:25:34 PM PDT 24
Finished Aug 07 07:27:08 PM PDT 24
Peak memory 261848 kb
Host smart-8ecdf26e-33d1-46e7-a244-d8d4f77826b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729326151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.729326151
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1821666746
Short name T1196
Test name
Test status
Simulation time 156053000 ps
CPU time 38.69 seconds
Started Aug 07 07:25:24 PM PDT 24
Finished Aug 07 07:26:03 PM PDT 24
Peak memory 261704 kb
Host smart-3ffd3a90-901e-4228-a68e-997ff6345e61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821666746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.1821666746
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3234550495
Short name T1217
Test name
Test status
Simulation time 677635100 ps
CPU time 17.66 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:25:49 PM PDT 24
Peak memory 272112 kb
Host smart-533e4eab-5f3a-4fc0-99d8-b7ef2251fd8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234550495 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3234550495
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2875274720
Short name T243
Test name
Test status
Simulation time 274858000 ps
CPU time 17.87 seconds
Started Aug 07 07:25:25 PM PDT 24
Finished Aug 07 07:25:43 PM PDT 24
Peak memory 261732 kb
Host smart-316c6270-8d27-42bd-bf7a-93a4dea4a54f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875274720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.2875274720
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1389934913
Short name T1193
Test name
Test status
Simulation time 18160400 ps
CPU time 13.54 seconds
Started Aug 07 07:25:26 PM PDT 24
Finished Aug 07 07:25:40 PM PDT 24
Peak memory 261816 kb
Host smart-52b18974-2beb-49f1-ae54-d1ae39c624e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389934913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1
389934913
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1329785263
Short name T238
Test name
Test status
Simulation time 27368900 ps
CPU time 13.52 seconds
Started Aug 07 07:25:22 PM PDT 24
Finished Aug 07 07:25:36 PM PDT 24
Peak memory 262816 kb
Host smart-4dd5dc21-59ce-4835-a4fe-5b236f86211f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329785263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1329785263
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1581519481
Short name T1124
Test name
Test status
Simulation time 18645000 ps
CPU time 13.25 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:25:45 PM PDT 24
Peak memory 261724 kb
Host smart-48e4317b-2940-4c93-8d3d-d116e262c1b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581519481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1581519481
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3090041208
Short name T65
Test name
Test status
Simulation time 930009600 ps
CPU time 30.83 seconds
Started Aug 07 07:25:33 PM PDT 24
Finished Aug 07 07:26:03 PM PDT 24
Peak memory 264360 kb
Host smart-63c59574-816f-4e78-8db8-2f49bbc4e92b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090041208 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3090041208
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1190799712
Short name T1118
Test name
Test status
Simulation time 37702800 ps
CPU time 15.39 seconds
Started Aug 07 07:25:22 PM PDT 24
Finished Aug 07 07:25:38 PM PDT 24
Peak memory 253588 kb
Host smart-f8962fe9-3306-4cca-a556-22f3a6c0ce17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190799712 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.1190799712
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2312619840
Short name T1150
Test name
Test status
Simulation time 66002000 ps
CPU time 15.89 seconds
Started Aug 07 07:25:22 PM PDT 24
Finished Aug 07 07:25:38 PM PDT 24
Peak memory 253600 kb
Host smart-d37c1cc7-17b6-49f7-8313-7f7389815cd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312619840 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2312619840
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.449406953
Short name T1227
Test name
Test status
Simulation time 246313400 ps
CPU time 20.86 seconds
Started Aug 07 07:25:25 PM PDT 24
Finished Aug 07 07:25:46 PM PDT 24
Peak memory 264396 kb
Host smart-8c2ac28e-a3af-44ab-b79e-109330dc6461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449406953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.449406953
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.20643235
Short name T274
Test name
Test status
Simulation time 1800459100 ps
CPU time 906.35 seconds
Started Aug 07 07:25:25 PM PDT 24
Finished Aug 07 07:40:31 PM PDT 24
Peak memory 264256 kb
Host smart-d11c901c-6984-4ee5-94d9-4f1c1063ec15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20643235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_t
l_intg_err.20643235
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.256509193
Short name T1254
Test name
Test status
Simulation time 15009800 ps
CPU time 13.34 seconds
Started Aug 07 07:26:42 PM PDT 24
Finished Aug 07 07:26:56 PM PDT 24
Peak memory 261776 kb
Host smart-5a46ab1b-0869-41b2-b080-955fc7ec5847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256509193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.256509193
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.222402048
Short name T1141
Test name
Test status
Simulation time 49668200 ps
CPU time 13.53 seconds
Started Aug 07 07:26:45 PM PDT 24
Finished Aug 07 07:26:59 PM PDT 24
Peak memory 261848 kb
Host smart-22f30e53-cc43-491f-82c7-04a6a96bcabe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222402048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.222402048
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.955593734
Short name T1148
Test name
Test status
Simulation time 28178500 ps
CPU time 13.52 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:07 PM PDT 24
Peak memory 261796 kb
Host smart-37836a81-4724-4638-a18e-bad5a7002617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955593734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.955593734
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.640646732
Short name T1205
Test name
Test status
Simulation time 23874700 ps
CPU time 13.6 seconds
Started Aug 07 07:26:54 PM PDT 24
Finished Aug 07 07:27:08 PM PDT 24
Peak memory 261872 kb
Host smart-82da472c-1f0e-4af8-8558-8032727a3341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640646732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.640646732
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4267311939
Short name T1238
Test name
Test status
Simulation time 16539600 ps
CPU time 13.49 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:05 PM PDT 24
Peak memory 261812 kb
Host smart-15894544-9ab3-4ca2-a004-3181e4aa0459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267311939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
4267311939
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2379960170
Short name T1181
Test name
Test status
Simulation time 25423400 ps
CPU time 13.74 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261796 kb
Host smart-e084eb33-087a-4fa1-bcfc-b3076287f48a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379960170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
2379960170
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2999930887
Short name T258
Test name
Test status
Simulation time 48389000 ps
CPU time 13.56 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:05 PM PDT 24
Peak memory 261820 kb
Host smart-62240e56-e6ec-419a-b7aa-407df878478b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999930887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2999930887
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.277770275
Short name T1249
Test name
Test status
Simulation time 18844700 ps
CPU time 13.87 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:07 PM PDT 24
Peak memory 261732 kb
Host smart-5f4922be-471f-4bbf-b4bc-418cc6a44020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277770275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.277770275
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2923125233
Short name T1245
Test name
Test status
Simulation time 16980200 ps
CPU time 13.58 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261708 kb
Host smart-c3dd88ba-de1e-40f5-beb1-c582374f4488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923125233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
2923125233
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2098028802
Short name T1239
Test name
Test status
Simulation time 14961400 ps
CPU time 13.53 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261848 kb
Host smart-b97a2a2a-ab3e-4dd1-9ec9-d409f2579c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098028802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2098028802
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1449538206
Short name T1195
Test name
Test status
Simulation time 221083300 ps
CPU time 32.66 seconds
Started Aug 07 07:25:40 PM PDT 24
Finished Aug 07 07:26:13 PM PDT 24
Peak memory 261932 kb
Host smart-8bfe8e2a-56a2-486b-96aa-f17ae6c21da8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449538206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.1449538206
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.195531135
Short name T1157
Test name
Test status
Simulation time 637658500 ps
CPU time 70.71 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:26:52 PM PDT 24
Peak memory 261876 kb
Host smart-897adebc-2d1e-4dd4-8555-3169868179f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195531135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.195531135
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3470794314
Short name T66
Test name
Test status
Simulation time 31533300 ps
CPU time 31.08 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:26:13 PM PDT 24
Peak memory 261832 kb
Host smart-54b06f44-da2a-4c17-a53f-f5c1bab78fcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470794314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3470794314
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2923674750
Short name T221
Test name
Test status
Simulation time 136796800 ps
CPU time 20.47 seconds
Started Aug 07 07:25:43 PM PDT 24
Finished Aug 07 07:26:03 PM PDT 24
Peak memory 271892 kb
Host smart-df6c246a-73af-4484-bb9e-013183896b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923674750 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2923674750
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2906171276
Short name T298
Test name
Test status
Simulation time 66357200 ps
CPU time 17.64 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:26:00 PM PDT 24
Peak memory 264284 kb
Host smart-4f4d7853-4e8b-483e-8a9a-002b7ea8759d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906171276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.2906171276
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2225242156
Short name T1162
Test name
Test status
Simulation time 15887300 ps
CPU time 13.43 seconds
Started Aug 07 07:25:31 PM PDT 24
Finished Aug 07 07:25:44 PM PDT 24
Peak memory 261836 kb
Host smart-939c697b-b4c1-4ce7-a13a-e86696d866c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225242156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
225242156
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.75937361
Short name T240
Test name
Test status
Simulation time 29871500 ps
CPU time 13.44 seconds
Started Aug 07 07:25:31 PM PDT 24
Finished Aug 07 07:25:44 PM PDT 24
Peak memory 262644 kb
Host smart-ac239b53-665d-4fda-bdc4-cb1e48ef90d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75937361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_mem_partial_access.75937361
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1958188995
Short name T1177
Test name
Test status
Simulation time 17763600 ps
CPU time 13.51 seconds
Started Aug 07 07:25:33 PM PDT 24
Finished Aug 07 07:25:46 PM PDT 24
Peak memory 261760 kb
Host smart-f3279d84-73cb-4360-be9c-eacc4a1b9ee6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958188995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1958188995
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3532185833
Short name T245
Test name
Test status
Simulation time 303399900 ps
CPU time 18.33 seconds
Started Aug 07 07:25:43 PM PDT 24
Finished Aug 07 07:26:01 PM PDT 24
Peak memory 261968 kb
Host smart-1a4b6147-5521-4013-900f-682a8d186ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532185833 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3532185833
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1506351211
Short name T1153
Test name
Test status
Simulation time 31287400 ps
CPU time 15.25 seconds
Started Aug 07 07:25:33 PM PDT 24
Finished Aug 07 07:25:49 PM PDT 24
Peak memory 253720 kb
Host smart-a7824f6b-29f6-4082-8e54-b2850831c989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506351211 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1506351211
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.75265042
Short name T1138
Test name
Test status
Simulation time 29407900 ps
CPU time 15.51 seconds
Started Aug 07 07:25:33 PM PDT 24
Finished Aug 07 07:25:49 PM PDT 24
Peak memory 253536 kb
Host smart-9ea68c51-b53b-4887-8b05-e971a0d49c18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75265042 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.75265042
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3017365604
Short name T235
Test name
Test status
Simulation time 457048600 ps
CPU time 758.92 seconds
Started Aug 07 07:25:32 PM PDT 24
Finished Aug 07 07:38:11 PM PDT 24
Peak memory 264272 kb
Host smart-3782a2fb-d285-485e-af13-26d93c85dfa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017365604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.3017365604
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.397219786
Short name T309
Test name
Test status
Simulation time 132091800 ps
CPU time 13.83 seconds
Started Aug 07 07:26:54 PM PDT 24
Finished Aug 07 07:27:08 PM PDT 24
Peak memory 261816 kb
Host smart-52e522fb-a8d9-463b-ae4f-916e540256b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397219786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.397219786
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3757261836
Short name T311
Test name
Test status
Simulation time 190941900 ps
CPU time 13.63 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:07 PM PDT 24
Peak memory 261776 kb
Host smart-02dca57a-c8d5-4b00-8a47-d49a4165700e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757261836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3757261836
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.136094721
Short name T1188
Test name
Test status
Simulation time 14718100 ps
CPU time 13.75 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261856 kb
Host smart-39b329d3-8289-4a14-9ae1-aefb461cbe15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136094721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.136094721
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3453377054
Short name T1192
Test name
Test status
Simulation time 16512800 ps
CPU time 13.58 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261692 kb
Host smart-172b9aef-6fe1-40cc-a8c8-941ace68d040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453377054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
3453377054
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1980313177
Short name T1131
Test name
Test status
Simulation time 17951300 ps
CPU time 13.6 seconds
Started Aug 07 07:26:54 PM PDT 24
Finished Aug 07 07:27:08 PM PDT 24
Peak memory 261872 kb
Host smart-0d373abb-9314-484f-935d-65b34a2d2cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980313177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
1980313177
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.434628183
Short name T1167
Test name
Test status
Simulation time 56755900 ps
CPU time 13.55 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261772 kb
Host smart-e6b444c2-e17f-4371-96c4-8b46b559ef9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434628183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.434628183
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3653322200
Short name T1248
Test name
Test status
Simulation time 28855800 ps
CPU time 13.48 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:07 PM PDT 24
Peak memory 261848 kb
Host smart-7a9f9630-5e1c-4774-a631-20451d7051d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653322200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
3653322200
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.973004859
Short name T1222
Test name
Test status
Simulation time 16462500 ps
CPU time 13.42 seconds
Started Aug 07 07:26:53 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261804 kb
Host smart-424435c6-2a66-46e4-b08e-594280a65f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973004859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.973004859
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.372591476
Short name T1187
Test name
Test status
Simulation time 24528800 ps
CPU time 13.81 seconds
Started Aug 07 07:26:51 PM PDT 24
Finished Aug 07 07:27:05 PM PDT 24
Peak memory 261856 kb
Host smart-a985dd55-8419-4b3d-9264-d94ed3c685c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372591476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.372591476
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1518416158
Short name T1185
Test name
Test status
Simulation time 2011180100 ps
CPU time 55.78 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:46 PM PDT 24
Peak memory 261916 kb
Host smart-36b7f7cb-c97e-42b2-a3ef-6dd1d940d395
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518416158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1518416158
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.691850949
Short name T1210
Test name
Test status
Simulation time 1577810300 ps
CPU time 51.78 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:43 PM PDT 24
Peak memory 261880 kb
Host smart-54b05abb-f251-4fd0-8453-22f32d3e8547
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691850949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_bit_bash.691850949
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.883541862
Short name T1129
Test name
Test status
Simulation time 49904600 ps
CPU time 30.71 seconds
Started Aug 07 07:25:41 PM PDT 24
Finished Aug 07 07:26:12 PM PDT 24
Peak memory 261860 kb
Host smart-733980e0-2d12-4e03-922b-7b88c29faf75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883541862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.883541862
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1231087083
Short name T1242
Test name
Test status
Simulation time 189055600 ps
CPU time 17.52 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:26:07 PM PDT 24
Peak memory 277252 kb
Host smart-8c33e52b-8e11-4885-ba84-edcf43c02635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231087083 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1231087083
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2074046728
Short name T1183
Test name
Test status
Simulation time 66528900 ps
CPU time 14.49 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:25:56 PM PDT 24
Peak memory 261884 kb
Host smart-7dbe9f3e-7285-4025-a541-2fc44df92003
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074046728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2074046728
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2574378436
Short name T1175
Test name
Test status
Simulation time 15482000 ps
CPU time 13.93 seconds
Started Aug 07 07:25:40 PM PDT 24
Finished Aug 07 07:25:54 PM PDT 24
Peak memory 261780 kb
Host smart-f76051f8-babe-4588-b5c9-c9baa67ec4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574378436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
574378436
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2737523519
Short name T237
Test name
Test status
Simulation time 77788700 ps
CPU time 13.75 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:25:56 PM PDT 24
Peak memory 263408 kb
Host smart-23617525-fb22-45ac-89a4-f2e132061cca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737523519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.2737523519
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2578313006
Short name T1143
Test name
Test status
Simulation time 16954200 ps
CPU time 13.49 seconds
Started Aug 07 07:25:41 PM PDT 24
Finished Aug 07 07:25:54 PM PDT 24
Peak memory 261804 kb
Host smart-0f1aafc5-f621-4672-841f-853c1b370fe3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578313006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2578313006
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.720550074
Short name T300
Test name
Test status
Simulation time 430131500 ps
CPU time 18.52 seconds
Started Aug 07 07:25:52 PM PDT 24
Finished Aug 07 07:26:10 PM PDT 24
Peak memory 261856 kb
Host smart-1c7a90a3-8678-430c-9556-40d2b7cab530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720550074 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.720550074
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1930910131
Short name T1216
Test name
Test status
Simulation time 27492600 ps
CPU time 13.27 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:25:55 PM PDT 24
Peak memory 253764 kb
Host smart-4e677e54-bb77-4b04-809c-cdc7e5870e47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930910131 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.1930910131
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.784418222
Short name T1122
Test name
Test status
Simulation time 13412100 ps
CPU time 13.22 seconds
Started Aug 07 07:25:42 PM PDT 24
Finished Aug 07 07:25:55 PM PDT 24
Peak memory 253680 kb
Host smart-1a67ffa9-5282-4813-885b-3864a3b6a81c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784418222 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.784418222
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.633824282
Short name T262
Test name
Test status
Simulation time 78674300 ps
CPU time 17.43 seconds
Started Aug 07 07:25:44 PM PDT 24
Finished Aug 07 07:26:01 PM PDT 24
Peak memory 264408 kb
Host smart-14ae6fcd-c2ca-4bb8-b39d-d85138d4be17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633824282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.633824282
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.362074956
Short name T67
Test name
Test status
Simulation time 426115200 ps
CPU time 460.31 seconds
Started Aug 07 07:25:40 PM PDT 24
Finished Aug 07 07:33:21 PM PDT 24
Peak memory 261788 kb
Host smart-080c3c9f-dce1-4036-9aeb-3a554730dc54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362074956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
tl_intg_err.362074956
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1244068318
Short name T1219
Test name
Test status
Simulation time 14742900 ps
CPU time 13.66 seconds
Started Aug 07 07:26:54 PM PDT 24
Finished Aug 07 07:27:08 PM PDT 24
Peak memory 261788 kb
Host smart-15aba953-bb76-43a0-938c-608189806482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244068318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1244068318
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2077488803
Short name T314
Test name
Test status
Simulation time 26455400 ps
CPU time 13.52 seconds
Started Aug 07 07:26:52 PM PDT 24
Finished Aug 07 07:27:06 PM PDT 24
Peak memory 261860 kb
Host smart-269fee9f-fd6b-45ad-bd66-3eebee0cc02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077488803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2077488803
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.718096220
Short name T1230
Test name
Test status
Simulation time 50891800 ps
CPU time 13.76 seconds
Started Aug 07 07:27:02 PM PDT 24
Finished Aug 07 07:27:16 PM PDT 24
Peak memory 261772 kb
Host smart-50a94a15-126d-46fb-b8ec-29949b011b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718096220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.718096220
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2684878251
Short name T1256
Test name
Test status
Simulation time 19662500 ps
CPU time 13.54 seconds
Started Aug 07 07:26:59 PM PDT 24
Finished Aug 07 07:27:13 PM PDT 24
Peak memory 261852 kb
Host smart-93bcf7ba-f9d1-4b46-8f01-6621127f5b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684878251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
2684878251
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1554825602
Short name T1142
Test name
Test status
Simulation time 18536200 ps
CPU time 13.56 seconds
Started Aug 07 07:27:01 PM PDT 24
Finished Aug 07 07:27:15 PM PDT 24
Peak memory 261840 kb
Host smart-9e597788-d59a-4acb-aaf2-d672aa11e908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554825602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
1554825602
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2859950642
Short name T1172
Test name
Test status
Simulation time 15719000 ps
CPU time 13.67 seconds
Started Aug 07 07:27:03 PM PDT 24
Finished Aug 07 07:27:17 PM PDT 24
Peak memory 261788 kb
Host smart-e92da848-2f10-46dd-98b2-fe87343285d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859950642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2859950642
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3967840444
Short name T313
Test name
Test status
Simulation time 31920800 ps
CPU time 13.87 seconds
Started Aug 07 07:27:01 PM PDT 24
Finished Aug 07 07:27:15 PM PDT 24
Peak memory 261856 kb
Host smart-03079068-748e-4c40-bbc8-46325e2ee4bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967840444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3967840444
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.468899957
Short name T1255
Test name
Test status
Simulation time 20682900 ps
CPU time 13.88 seconds
Started Aug 07 07:27:01 PM PDT 24
Finished Aug 07 07:27:15 PM PDT 24
Peak memory 261732 kb
Host smart-09b491c7-3c3a-4eb6-a59c-944c5d591e65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468899957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.468899957
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1236043054
Short name T1207
Test name
Test status
Simulation time 57589400 ps
CPU time 13.47 seconds
Started Aug 07 07:27:01 PM PDT 24
Finished Aug 07 07:27:15 PM PDT 24
Peak memory 261796 kb
Host smart-b8b10c63-b2ce-4032-9152-5fb02cae916c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236043054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1236043054
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3865711664
Short name T1211
Test name
Test status
Simulation time 19717600 ps
CPU time 13.59 seconds
Started Aug 07 07:27:01 PM PDT 24
Finished Aug 07 07:27:15 PM PDT 24
Peak memory 261840 kb
Host smart-81aa0039-2917-43bf-b931-f203cd6fb3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865711664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3865711664
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.991102714
Short name T1179
Test name
Test status
Simulation time 97294400 ps
CPU time 18.14 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:26:09 PM PDT 24
Peak memory 274688 kb
Host smart-472186c6-1a36-4f32-b355-3f6b75310263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991102714 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.991102714
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1467963444
Short name T1186
Test name
Test status
Simulation time 501579800 ps
CPU time 15.14 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:26:06 PM PDT 24
Peak memory 264236 kb
Host smart-b411a816-4f2d-4bec-baec-2415665be23a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467963444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1467963444
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1475909864
Short name T1132
Test name
Test status
Simulation time 17438700 ps
CPU time 13.54 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:26:04 PM PDT 24
Peak memory 261768 kb
Host smart-fa6b6420-e258-49a2-aa4d-3cf56f70f9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475909864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.1
475909864
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.398055506
Short name T299
Test name
Test status
Simulation time 217065600 ps
CPU time 21.7 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:26:11 PM PDT 24
Peak memory 264316 kb
Host smart-db982ef1-d597-4faf-bc4a-82dfdfe09968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398055506 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.398055506
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3730170316
Short name T1116
Test name
Test status
Simulation time 16603500 ps
CPU time 13.48 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:04 PM PDT 24
Peak memory 253592 kb
Host smart-3a5eacd2-c9d3-45e5-86ce-e2fa0ee40674
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730170316 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3730170316
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3533270983
Short name T1135
Test name
Test status
Simulation time 15812600 ps
CPU time 15.85 seconds
Started Aug 07 07:25:52 PM PDT 24
Finished Aug 07 07:26:08 PM PDT 24
Peak memory 253684 kb
Host smart-76819386-8453-403e-83d0-d429cda858fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533270983 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3533270983
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1596983957
Short name T256
Test name
Test status
Simulation time 1314980400 ps
CPU time 755.22 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:38:27 PM PDT 24
Peak memory 264328 kb
Host smart-f095723b-d7ac-454b-8427-64a7c3495e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596983957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.1596983957
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1876753643
Short name T1228
Test name
Test status
Simulation time 164966900 ps
CPU time 19 seconds
Started Aug 07 07:25:52 PM PDT 24
Finished Aug 07 07:26:11 PM PDT 24
Peak memory 272544 kb
Host smart-8f438905-592b-4ac0-9b44-802ccf037166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876753643 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1876753643
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2220554408
Short name T1221
Test name
Test status
Simulation time 57172200 ps
CPU time 17.23 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:08 PM PDT 24
Peak memory 264268 kb
Host smart-424937bf-6ff2-4f66-bad1-95a660d545a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220554408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.2220554408
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1456634213
Short name T1199
Test name
Test status
Simulation time 93493300 ps
CPU time 13.57 seconds
Started Aug 07 07:25:53 PM PDT 24
Finished Aug 07 07:26:07 PM PDT 24
Peak memory 261732 kb
Host smart-2ac732f4-ca9c-4d44-a16d-68ff86a315ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456634213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1
456634213
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1444330130
Short name T1154
Test name
Test status
Simulation time 133091800 ps
CPU time 17.96 seconds
Started Aug 07 07:25:53 PM PDT 24
Finished Aug 07 07:26:11 PM PDT 24
Peak memory 261936 kb
Host smart-4dd6b515-ee07-40ac-98c4-6c675f8c5de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444330130 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1444330130
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2773405787
Short name T1232
Test name
Test status
Simulation time 13398900 ps
CPU time 13.13 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:26:04 PM PDT 24
Peak memory 253692 kb
Host smart-b2e38f24-c5de-4dbe-81ae-05c475cfaf7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773405787 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2773405787
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.154452231
Short name T1119
Test name
Test status
Simulation time 23710600 ps
CPU time 16.22 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:07 PM PDT 24
Peak memory 253664 kb
Host smart-00d5bc8e-8a06-4b29-b698-55007594f597
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154452231 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.154452231
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1739922234
Short name T265
Test name
Test status
Simulation time 36081100 ps
CPU time 16.43 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:08 PM PDT 24
Peak memory 264404 kb
Host smart-2f68a345-430c-474c-ab55-bbff78642e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739922234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
739922234
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3060252075
Short name T1252
Test name
Test status
Simulation time 440326800 ps
CPU time 19.2 seconds
Started Aug 07 07:26:02 PM PDT 24
Finished Aug 07 07:26:22 PM PDT 24
Peak memory 272744 kb
Host smart-9ae671df-5c92-4c04-8fc2-252e2f896f5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060252075 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3060252075
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3616217818
Short name T1164
Test name
Test status
Simulation time 31130700 ps
CPU time 16.44 seconds
Started Aug 07 07:26:02 PM PDT 24
Finished Aug 07 07:26:19 PM PDT 24
Peak memory 264240 kb
Host smart-031f75dd-a6f2-4e98-8143-fe306443cf05
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616217818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.3616217818
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2995811114
Short name T1190
Test name
Test status
Simulation time 56451700 ps
CPU time 13.43 seconds
Started Aug 07 07:25:52 PM PDT 24
Finished Aug 07 07:26:06 PM PDT 24
Peak memory 261796 kb
Host smart-5ff5a27b-8aaf-43c0-94e9-47f82cdb32fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995811114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
995811114
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3373081632
Short name T1180
Test name
Test status
Simulation time 68111600 ps
CPU time 17.73 seconds
Started Aug 07 07:26:06 PM PDT 24
Finished Aug 07 07:26:24 PM PDT 24
Peak memory 261996 kb
Host smart-84e3aeb4-eecf-4bc3-a39a-7fa76134e8b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373081632 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3373081632
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2312823625
Short name T1226
Test name
Test status
Simulation time 42500600 ps
CPU time 13.31 seconds
Started Aug 07 07:25:51 PM PDT 24
Finished Aug 07 07:26:04 PM PDT 24
Peak memory 253708 kb
Host smart-21b43f0c-55c4-4e79-97eb-8c82c0a85b38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312823625 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2312823625
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1650428779
Short name T1126
Test name
Test status
Simulation time 22243900 ps
CPU time 15.59 seconds
Started Aug 07 07:25:53 PM PDT 24
Finished Aug 07 07:26:09 PM PDT 24
Peak memory 253616 kb
Host smart-320ad184-37a6-42de-8eae-3a36a3a2b399
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650428779 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1650428779
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2699016685
Short name T268
Test name
Test status
Simulation time 34323900 ps
CPU time 16.56 seconds
Started Aug 07 07:25:52 PM PDT 24
Finished Aug 07 07:26:09 PM PDT 24
Peak memory 264416 kb
Host smart-9732de32-bb33-42f7-895d-3a06b683e264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699016685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
699016685
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3044913885
Short name T1231
Test name
Test status
Simulation time 647471100 ps
CPU time 387.62 seconds
Started Aug 07 07:25:50 PM PDT 24
Finished Aug 07 07:32:18 PM PDT 24
Peak memory 264320 kb
Host smart-ede49df0-2e51-4d13-84e9-72ddcc288611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044913885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.3044913885
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3209346336
Short name T273
Test name
Test status
Simulation time 165945600 ps
CPU time 20.77 seconds
Started Aug 07 07:26:04 PM PDT 24
Finished Aug 07 07:26:25 PM PDT 24
Peak memory 279452 kb
Host smart-17f6ed08-41ab-48f1-a032-87805018d86b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209346336 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.3209346336
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2183147268
Short name T246
Test name
Test status
Simulation time 32533200 ps
CPU time 16.38 seconds
Started Aug 07 07:26:04 PM PDT 24
Finished Aug 07 07:26:21 PM PDT 24
Peak memory 261876 kb
Host smart-b2110e7b-3265-4c17-845c-1393d0f3f99c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183147268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2183147268
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4110664352
Short name T1174
Test name
Test status
Simulation time 49760300 ps
CPU time 13.67 seconds
Started Aug 07 07:26:04 PM PDT 24
Finished Aug 07 07:26:18 PM PDT 24
Peak memory 261836 kb
Host smart-140bb883-9e15-42d3-9836-7604b88f8ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110664352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.4
110664352
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2110349323
Short name T294
Test name
Test status
Simulation time 178426300 ps
CPU time 19.86 seconds
Started Aug 07 07:26:03 PM PDT 24
Finished Aug 07 07:26:23 PM PDT 24
Peak memory 263160 kb
Host smart-a6cc402d-afc0-4bff-91c3-3ed6dd142135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110349323 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2110349323
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1740813236
Short name T1163
Test name
Test status
Simulation time 12823000 ps
CPU time 15.56 seconds
Started Aug 07 07:26:06 PM PDT 24
Finished Aug 07 07:26:21 PM PDT 24
Peak memory 253712 kb
Host smart-47fc8bb7-580b-43aa-8d50-b490918f565c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740813236 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1740813236
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3876514449
Short name T1139
Test name
Test status
Simulation time 24902600 ps
CPU time 15.73 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:26:20 PM PDT 24
Peak memory 253748 kb
Host smart-58a35965-19ae-4c46-bc34-253444ded571
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876514449 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.3876514449
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1052185192
Short name T1204
Test name
Test status
Simulation time 75803700 ps
CPU time 16.83 seconds
Started Aug 07 07:26:02 PM PDT 24
Finished Aug 07 07:26:19 PM PDT 24
Peak memory 263496 kb
Host smart-8d695932-5e6d-4fa6-85a2-4415e5e9470a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052185192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
052185192
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3654891201
Short name T232
Test name
Test status
Simulation time 73248200 ps
CPU time 17.52 seconds
Started Aug 07 07:26:04 PM PDT 24
Finished Aug 07 07:26:22 PM PDT 24
Peak memory 279980 kb
Host smart-41436fae-727f-4350-afb2-eb10c9b0efb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654891201 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3654891201
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4293114366
Short name T1165
Test name
Test status
Simulation time 118427700 ps
CPU time 16.67 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:26:22 PM PDT 24
Peak memory 263768 kb
Host smart-4f85d66b-3ae7-44f9-809c-86fe5266d55e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293114366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.4293114366
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1050447913
Short name T1194
Test name
Test status
Simulation time 14848200 ps
CPU time 13.5 seconds
Started Aug 07 07:26:06 PM PDT 24
Finished Aug 07 07:26:19 PM PDT 24
Peak memory 261864 kb
Host smart-fea5ee2b-1e1e-4362-a2f4-daf314b897d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050447913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
050447913
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.182515483
Short name T1184
Test name
Test status
Simulation time 92512100 ps
CPU time 15.14 seconds
Started Aug 07 07:26:02 PM PDT 24
Finished Aug 07 07:26:18 PM PDT 24
Peak memory 261944 kb
Host smart-ca172b28-8a7d-44eb-8f7a-32259c653547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182515483 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.182515483
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4039401779
Short name T1120
Test name
Test status
Simulation time 14983800 ps
CPU time 13.34 seconds
Started Aug 07 07:26:02 PM PDT 24
Finished Aug 07 07:26:15 PM PDT 24
Peak memory 253752 kb
Host smart-0ea1a722-208c-480e-8960-2fbbf2edaca7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039401779 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.4039401779
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2873803893
Short name T1191
Test name
Test status
Simulation time 22991200 ps
CPU time 15.83 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:26:21 PM PDT 24
Peak memory 253724 kb
Host smart-4c5dcc1f-26cb-4e71-ba19-544f304dc51d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873803893 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2873803893
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4000015087
Short name T271
Test name
Test status
Simulation time 88871400 ps
CPU time 19.68 seconds
Started Aug 07 07:26:03 PM PDT 24
Finished Aug 07 07:26:23 PM PDT 24
Peak memory 264344 kb
Host smart-65bc86aa-5fac-42af-b342-5de738b390f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000015087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.4
000015087
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1329453379
Short name T106
Test name
Test status
Simulation time 6587913200 ps
CPU time 906.9 seconds
Started Aug 07 07:26:05 PM PDT 24
Finished Aug 07 07:41:12 PM PDT 24
Peak memory 264388 kb
Host smart-e2d32658-1ca4-4e94-8202-e065d32ee919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329453379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1329453379
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3796705837
Short name T21
Test name
Test status
Simulation time 13854300 ps
CPU time 13.75 seconds
Started Aug 07 07:32:06 PM PDT 24
Finished Aug 07 07:32:20 PM PDT 24
Peak memory 265708 kb
Host smart-1cbe6d11-11c4-4dbf-9409-6f7d8effc33e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796705837 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3796705837
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2963140921
Short name T694
Test name
Test status
Simulation time 65867900 ps
CPU time 13.48 seconds
Started Aug 07 07:32:01 PM PDT 24
Finished Aug 07 07:32:14 PM PDT 24
Peak memory 283232 kb
Host smart-8b4b8d38-e593-49d5-a181-57cdacb29439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963140921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2963140921
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.548572224
Short name T983
Test name
Test status
Simulation time 846959200 ps
CPU time 191.26 seconds
Started Aug 07 07:31:52 PM PDT 24
Finished Aug 07 07:35:03 PM PDT 24
Peak memory 281544 kb
Host smart-5a8f89bd-f30f-4e6f-9037-e79cc032f075
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548572224 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.548572224
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2649374289
Short name T845
Test name
Test status
Simulation time 5569845400 ps
CPU time 392.25 seconds
Started Aug 07 07:31:55 PM PDT 24
Finished Aug 07 07:38:28 PM PDT 24
Peak memory 263620 kb
Host smart-8a4d59c2-b85d-4e01-b914-99a70b39541d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649374289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2649374289
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.2793786672
Short name T900
Test name
Test status
Simulation time 1151678700 ps
CPU time 1028.17 seconds
Started Aug 07 07:31:53 PM PDT 24
Finished Aug 07 07:49:01 PM PDT 24
Peak memory 273584 kb
Host smart-a7257636-8329-4e2b-aa9a-b8e1717587fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793786672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.2793786672
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.1285955216
Short name T959
Test name
Test status
Simulation time 1544544100 ps
CPU time 40.12 seconds
Started Aug 07 07:32:08 PM PDT 24
Finished Aug 07 07:32:49 PM PDT 24
Peak memory 263308 kb
Host smart-3ba7b41a-a80d-4277-8d4d-e7eb4c017480
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285955216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.1285955216
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.4064446408
Short name T129
Test name
Test status
Simulation time 919100306900 ps
CPU time 3506.61 seconds
Started Aug 07 07:31:54 PM PDT 24
Finished Aug 07 08:30:21 PM PDT 24
Peak memory 264072 kb
Host smart-ec79eea8-9b26-4c2a-bafd-b8e55d6a12b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064446408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.4064446408
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_addr_infection.2880008910
Short name T617
Test name
Test status
Simulation time 35464100 ps
CPU time 30.81 seconds
Started Aug 07 07:32:12 PM PDT 24
Finished Aug 07 07:32:43 PM PDT 24
Peak memory 267540 kb
Host smart-d36ca027-d6c5-4865-9228-1766dc24aaf9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880008910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.2880008910
Directory /workspace/0.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.497870740
Short name T776
Test name
Test status
Simulation time 340557926400 ps
CPU time 1986.15 seconds
Started Aug 07 07:31:53 PM PDT 24
Finished Aug 07 08:05:00 PM PDT 24
Peak memory 260316 kb
Host smart-e26a47ce-92af-4896-a2b7-a4f4d83a5c97
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497870740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.497870740
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.128721423
Short name T721
Test name
Test status
Simulation time 120159463100 ps
CPU time 857.55 seconds
Started Aug 07 07:31:53 PM PDT 24
Finished Aug 07 07:46:11 PM PDT 24
Peak memory 265172 kb
Host smart-ad2900a3-2ef8-4be7-a3a6-18c0d0871e54
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128721423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.128721423
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2118902056
Short name T1020
Test name
Test status
Simulation time 3494015800 ps
CPU time 130.07 seconds
Started Aug 07 07:31:57 PM PDT 24
Finished Aug 07 07:34:07 PM PDT 24
Peak memory 261060 kb
Host smart-b5b06184-be39-4b35-b895-b3df5bd22942
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118902056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2118902056
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.1569746729
Short name T993
Test name
Test status
Simulation time 3352645200 ps
CPU time 644.92 seconds
Started Aug 07 07:32:01 PM PDT 24
Finished Aug 07 07:42:46 PM PDT 24
Peak memory 329620 kb
Host smart-9c40a831-e0c9-42bf-8b87-119445fa5fa4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569746729 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.1569746729
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1259273272
Short name T35
Test name
Test status
Simulation time 13316282000 ps
CPU time 267.84 seconds
Started Aug 07 07:32:03 PM PDT 24
Finished Aug 07 07:36:31 PM PDT 24
Peak memory 290180 kb
Host smart-33e2481f-ea8a-45b0-8c85-d225f1b7441d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259273272 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1259273272
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1866443441
Short name T663
Test name
Test status
Simulation time 44061918400 ps
CPU time 216.37 seconds
Started Aug 07 07:32:01 PM PDT 24
Finished Aug 07 07:35:37 PM PDT 24
Peak memory 260752 kb
Host smart-0605138f-2d18-465c-b95f-886b0659d014
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186
6443441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1866443441
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.2321719699
Short name T929
Test name
Test status
Simulation time 2140754300 ps
CPU time 73.07 seconds
Started Aug 07 07:31:52 PM PDT 24
Finished Aug 07 07:33:05 PM PDT 24
Peak memory 263820 kb
Host smart-addb01e3-c1e0-41ce-875b-b6e2a260f2c4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321719699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2321719699
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1741201613
Short name T884
Test name
Test status
Simulation time 211523500 ps
CPU time 13.47 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:32:26 PM PDT 24
Peak memory 261284 kb
Host smart-8debce92-39ca-498a-8858-eadcfc385ee4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741201613 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1741201613
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.3134752154
Short name T146
Test name
Test status
Simulation time 10547385800 ps
CPU time 664.81 seconds
Started Aug 07 07:31:50 PM PDT 24
Finished Aug 07 07:42:55 PM PDT 24
Peak memory 275196 kb
Host smart-4907fcc0-eac1-4fdb-9ecb-63025136d37e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134752154 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.3134752154
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2457884628
Short name T424
Test name
Test status
Simulation time 40119800 ps
CPU time 134.9 seconds
Started Aug 07 07:31:52 PM PDT 24
Finished Aug 07 07:34:07 PM PDT 24
Peak memory 261288 kb
Host smart-dceaa999-6867-4c4b-a959-7e7dc4828f21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457884628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2457884628
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.2180815251
Short name T954
Test name
Test status
Simulation time 3482392900 ps
CPU time 224.44 seconds
Started Aug 07 07:32:02 PM PDT 24
Finished Aug 07 07:35:47 PM PDT 24
Peak memory 290328 kb
Host smart-60914705-203a-4ec7-89fa-68a154d4f69c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180815251 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2180815251
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.163451298
Short name T199
Test name
Test status
Simulation time 15960900 ps
CPU time 14.21 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:32:28 PM PDT 24
Peak memory 261608 kb
Host smart-13159a69-648f-418c-8264-5457b5913ff1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=163451298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.163451298
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.1121045799
Short name T1034
Test name
Test status
Simulation time 2888317900 ps
CPU time 419.67 seconds
Started Aug 07 07:31:54 PM PDT 24
Finished Aug 07 07:38:54 PM PDT 24
Peak memory 263476 kb
Host smart-e61f30ff-a463-484e-8fa7-cb6138cec1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121045799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1121045799
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1558376584
Short name T161
Test name
Test status
Simulation time 43854200 ps
CPU time 14.53 seconds
Started Aug 07 07:32:03 PM PDT 24
Finished Aug 07 07:32:18 PM PDT 24
Peak memory 263252 kb
Host smart-245abc3f-8827-49a6-8295-f03e3704d337
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558376584 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1558376584
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.2928298028
Short name T792
Test name
Test status
Simulation time 15654257300 ps
CPU time 183.93 seconds
Started Aug 07 07:32:02 PM PDT 24
Finished Aug 07 07:35:06 PM PDT 24
Peak memory 260232 kb
Host smart-f67fa383-d9d8-441e-bc5d-0e7bd12f7ced
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928298028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.flash_ctrl_prog_reset.2928298028
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3031272113
Short name T844
Test name
Test status
Simulation time 99012700 ps
CPU time 494.01 seconds
Started Aug 07 07:31:45 PM PDT 24
Finished Aug 07 07:39:59 PM PDT 24
Peak memory 283992 kb
Host smart-620aec48-b08d-4613-914b-ac282c228f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031272113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3031272113
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3951170224
Short name T599
Test name
Test status
Simulation time 211409700 ps
CPU time 104.24 seconds
Started Aug 07 07:31:52 PM PDT 24
Finished Aug 07 07:33:36 PM PDT 24
Peak memory 263124 kb
Host smart-c3d0f66a-b410-42c6-9efb-4b274b0816ec
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3951170224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3951170224
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.369590448
Short name T203
Test name
Test status
Simulation time 69293700 ps
CPU time 32.18 seconds
Started Aug 07 07:32:08 PM PDT 24
Finished Aug 07 07:32:40 PM PDT 24
Peak memory 275884 kb
Host smart-8b02154e-b083-461d-b708-82650485a54d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369590448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rd_intg.369590448
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1868676076
Short name T496
Test name
Test status
Simulation time 154147600 ps
CPU time 44.81 seconds
Started Aug 07 07:32:12 PM PDT 24
Finished Aug 07 07:32:57 PM PDT 24
Peak memory 273924 kb
Host smart-4eddfef7-954f-4aea-82c2-c2aa7e426fa7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868676076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1868676076
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3183822844
Short name T817
Test name
Test status
Simulation time 59207700 ps
CPU time 15.26 seconds
Started Aug 07 07:31:54 PM PDT 24
Finished Aug 07 07:32:09 PM PDT 24
Peak memory 265464 kb
Host smart-0a2edef4-7a2c-495f-bc22-63f9e8802ea8
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3183822844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3183822844
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.952239961
Short name T432
Test name
Test status
Simulation time 19028700 ps
CPU time 23.33 seconds
Started Aug 07 07:31:51 PM PDT 24
Finished Aug 07 07:32:15 PM PDT 24
Peak memory 265168 kb
Host smart-f2c7d28c-4925-4556-a1d6-e7559f2c5246
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952239961 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.952239961
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2048364805
Short name T682
Test name
Test status
Simulation time 41688200 ps
CPU time 22.94 seconds
Started Aug 07 07:31:55 PM PDT 24
Finished Aug 07 07:32:18 PM PDT 24
Peak memory 265584 kb
Host smart-ed14118a-28fa-47ef-8de3-38e959744d34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048364805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2048364805
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.3081791347
Short name T991
Test name
Test status
Simulation time 889120600 ps
CPU time 112.48 seconds
Started Aug 07 07:31:50 PM PDT 24
Finished Aug 07 07:33:43 PM PDT 24
Peak memory 281996 kb
Host smart-296b3d36-d966-4598-a8e1-899650005bda
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081791347 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.3081791347
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.680677282
Short name T58
Test name
Test status
Simulation time 1255119900 ps
CPU time 182.48 seconds
Started Aug 07 07:31:51 PM PDT 24
Finished Aug 07 07:34:54 PM PDT 24
Peak memory 282112 kb
Host smart-2488679c-aef4-444c-9589-791cec4ec9dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
680677282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.680677282
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.2465693520
Short name T38
Test name
Test status
Simulation time 5728501000 ps
CPU time 161.63 seconds
Started Aug 07 07:31:51 PM PDT 24
Finished Aug 07 07:34:33 PM PDT 24
Peak memory 293308 kb
Host smart-51d8e379-13f0-4ed5-8f1d-165feee05c03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465693520 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2465693520
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.372900780
Short name T647
Test name
Test status
Simulation time 1444004400 ps
CPU time 220.47 seconds
Started Aug 07 07:31:52 PM PDT 24
Finished Aug 07 07:35:33 PM PDT 24
Peak memory 282108 kb
Host smart-143bc405-9022-4ec6-8d8a-afbdeb1a08f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372900780 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_derr.372900780
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.1879506963
Short name T1028
Test name
Test status
Simulation time 37772600 ps
CPU time 31.38 seconds
Started Aug 07 07:32:03 PM PDT 24
Finished Aug 07 07:32:34 PM PDT 24
Peak memory 273868 kb
Host smart-d42ece91-fe36-4141-b1f5-c1e99947028b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879506963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.1879506963
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.3820091283
Short name T1102
Test name
Test status
Simulation time 9593863700 ps
CPU time 232.47 seconds
Started Aug 07 07:31:52 PM PDT 24
Finished Aug 07 07:35:45 PM PDT 24
Peak memory 295396 kb
Host smart-c8aa7467-8801-42df-9f45-449b853e1e4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820091283 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.flash_ctrl_rw_serr.3820091283
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.293911834
Short name T43
Test name
Test status
Simulation time 3966734500 ps
CPU time 4912.81 seconds
Started Aug 07 07:32:02 PM PDT 24
Finished Aug 07 08:53:55 PM PDT 24
Peak memory 287628 kb
Host smart-0629c933-526f-4743-b8c0-ec04fec1fa9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293911834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.293911834
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.3631634077
Short name T887
Test name
Test status
Simulation time 744251700 ps
CPU time 67.67 seconds
Started Aug 07 07:31:54 PM PDT 24
Finished Aug 07 07:33:01 PM PDT 24
Peak memory 265672 kb
Host smart-7cec527a-ad21-4a46-9dcb-afd7cac8c6b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631634077 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.3631634077
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.391885599
Short name T1002
Test name
Test status
Simulation time 436464200 ps
CPU time 55.53 seconds
Started Aug 07 07:31:55 PM PDT 24
Finished Aug 07 07:32:50 PM PDT 24
Peak memory 273912 kb
Host smart-5654aae1-b62e-49f0-ab99-bc67b1de8a0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391885599 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_counter.391885599
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3391141218
Short name T531
Test name
Test status
Simulation time 137478100 ps
CPU time 54.72 seconds
Started Aug 07 07:31:49 PM PDT 24
Finished Aug 07 07:32:44 PM PDT 24
Peak memory 271444 kb
Host smart-ca7ccfcd-3b5a-4c31-a21b-6575f0834abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391141218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3391141218
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2543265421
Short name T222
Test name
Test status
Simulation time 23333000 ps
CPU time 26.41 seconds
Started Aug 07 07:31:43 PM PDT 24
Finished Aug 07 07:32:09 PM PDT 24
Peak memory 259972 kb
Host smart-c5b05d81-dc60-436d-8a0d-a08bc4eca762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543265421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2543265421
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.1193814341
Short name T228
Test name
Test status
Simulation time 1930928600 ps
CPU time 1423.25 seconds
Started Aug 07 07:32:00 PM PDT 24
Finished Aug 07 07:55:44 PM PDT 24
Peak memory 289068 kb
Host smart-de30807a-ae41-415a-ac52-84e5e54cc039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193814341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.1193814341
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.2122901337
Short name T827
Test name
Test status
Simulation time 52358200 ps
CPU time 25 seconds
Started Aug 07 07:31:50 PM PDT 24
Finished Aug 07 07:32:15 PM PDT 24
Peak memory 262796 kb
Host smart-089aebd2-b0d5-4ae6-9b2a-4bf54e4a2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122901337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2122901337
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.2305687656
Short name T136
Test name
Test status
Simulation time 7193259800 ps
CPU time 138.17 seconds
Started Aug 07 07:31:51 PM PDT 24
Finished Aug 07 07:34:10 PM PDT 24
Peak memory 260192 kb
Host smart-a4e65040-3597-4ead-8e24-ea4133117703
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305687656 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.2305687656
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2850605198
Short name T1112
Test name
Test status
Simulation time 77268300 ps
CPU time 15.45 seconds
Started Aug 07 07:31:53 PM PDT 24
Finished Aug 07 07:32:09 PM PDT 24
Peak memory 258936 kb
Host smart-9ee9f1a6-0ff5-4a43-bff1-534c0b66353b
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2850605198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.2850605198
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.1054420802
Short name T976
Test name
Test status
Simulation time 207840000 ps
CPU time 13.64 seconds
Started Aug 07 07:32:43 PM PDT 24
Finished Aug 07 07:32:57 PM PDT 24
Peak memory 258316 kb
Host smart-e149e568-0297-434f-b65c-117859e63362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054420802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1
054420802
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.1933968312
Short name T1053
Test name
Test status
Simulation time 32926800 ps
CPU time 14.37 seconds
Started Aug 07 07:32:44 PM PDT 24
Finished Aug 07 07:32:59 PM PDT 24
Peak memory 265396 kb
Host smart-bbdd3202-d12e-4c1e-811d-34010e87c3e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933968312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.1933968312
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.2373015360
Short name T544
Test name
Test status
Simulation time 36075600 ps
CPU time 16.23 seconds
Started Aug 07 07:32:34 PM PDT 24
Finished Aug 07 07:32:50 PM PDT 24
Peak memory 284624 kb
Host smart-1154386d-c8af-47ea-b7a0-972d9ca6448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373015360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2373015360
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.4145713623
Short name T722
Test name
Test status
Simulation time 20277300 ps
CPU time 22.79 seconds
Started Aug 07 07:32:36 PM PDT 24
Finished Aug 07 07:32:59 PM PDT 24
Peak memory 273908 kb
Host smart-23a71215-a473-40c7-b2a8-ca7e036fd259
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145713623 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.4145713623
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.3118770711
Short name T162
Test name
Test status
Simulation time 1510373100 ps
CPU time 309.03 seconds
Started Aug 07 07:32:22 PM PDT 24
Finished Aug 07 07:37:31 PM PDT 24
Peak memory 263564 kb
Host smart-b2c4bc16-db15-4bf5-8e1e-ce1288b6ddbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3118770711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3118770711
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.2973160156
Short name T68
Test name
Test status
Simulation time 13431796500 ps
CPU time 2344.81 seconds
Started Aug 07 07:32:22 PM PDT 24
Finished Aug 07 08:11:27 PM PDT 24
Peak memory 265452 kb
Host smart-b975f491-c37c-42b0-96d4-f7125f9d5b85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2973160156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2973160156
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.3226200870
Short name T946
Test name
Test status
Simulation time 1547375500 ps
CPU time 2023.96 seconds
Started Aug 07 07:32:21 PM PDT 24
Finished Aug 07 08:06:06 PM PDT 24
Peak memory 262552 kb
Host smart-f2ca7019-2003-4473-98a1-ac5c4071fd6f
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226200870 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3226200870
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.1573589417
Short name T1046
Test name
Test status
Simulation time 4686837500 ps
CPU time 1236.45 seconds
Started Aug 07 07:32:23 PM PDT 24
Finished Aug 07 07:52:59 PM PDT 24
Peak memory 273604 kb
Host smart-893848c9-fa59-4d3e-9373-dc0a02b15109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573589417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1573589417
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.1411712829
Short name T1113
Test name
Test status
Simulation time 640658400 ps
CPU time 26.54 seconds
Started Aug 07 07:32:21 PM PDT 24
Finished Aug 07 07:32:48 PM PDT 24
Peak memory 263848 kb
Host smart-8c91f53a-f46f-4006-a30e-0a011f5944d8
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411712829 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_fetch_code.1411712829
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.304366945
Short name T783
Test name
Test status
Simulation time 317854800 ps
CPU time 39.02 seconds
Started Aug 07 07:32:51 PM PDT 24
Finished Aug 07 07:33:30 PM PDT 24
Peak memory 265568 kb
Host smart-537cdfc7-3ab0-42a9-8205-58715a4c649b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304366945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_fs_sup.304366945
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1186207417
Short name T652
Test name
Test status
Simulation time 50870359700 ps
CPU time 4261.71 seconds
Started Aug 07 07:32:23 PM PDT 24
Finished Aug 07 08:43:25 PM PDT 24
Peak memory 263944 kb
Host smart-5fcc0f09-bb3b-4ec9-8ffe-015caac88533
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186207417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1186207417
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_addr_infection.3565678221
Short name T547
Test name
Test status
Simulation time 28039800 ps
CPU time 27.6 seconds
Started Aug 07 07:32:47 PM PDT 24
Finished Aug 07 07:33:15 PM PDT 24
Peak memory 273748 kb
Host smart-0f8b5acd-025a-46dc-84c0-8d98ce080a25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565678221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.3565678221
Directory /workspace/1.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.1825500530
Short name T279
Test name
Test status
Simulation time 476474000 ps
CPU time 94.45 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:33:48 PM PDT 24
Peak memory 265532 kb
Host smart-c3ebacc7-b4bc-4e35-a7e2-1f2ba5fcd4e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825500530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.1825500530
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.439341937
Short name T174
Test name
Test status
Simulation time 10012217000 ps
CPU time 328.54 seconds
Started Aug 07 07:32:45 PM PDT 24
Finished Aug 07 07:38:13 PM PDT 24
Peak memory 325300 kb
Host smart-28176536-7392-4b7e-b57e-bd684b765c0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439341937 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.439341937
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1247589867
Short name T111
Test name
Test status
Simulation time 149168308700 ps
CPU time 1945 seconds
Started Aug 07 07:32:24 PM PDT 24
Finished Aug 07 08:04:49 PM PDT 24
Peak memory 260084 kb
Host smart-ff20ef61-ff78-4e80-aa29-f2784aa33f21
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247589867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1247589867
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2510647721
Short name T1003
Test name
Test status
Simulation time 80143363200 ps
CPU time 908.23 seconds
Started Aug 07 07:32:24 PM PDT 24
Finished Aug 07 07:47:33 PM PDT 24
Peak memory 265228 kb
Host smart-33d3de46-19f9-4b6e-9b20-8c2183d642c7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510647721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2510647721
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.329779468
Short name T809
Test name
Test status
Simulation time 1673050300 ps
CPU time 117.6 seconds
Started Aug 07 07:32:14 PM PDT 24
Finished Aug 07 07:34:11 PM PDT 24
Peak memory 261032 kb
Host smart-1d0d5764-ee5c-4c1f-9eea-8a99f9d65a12
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329779468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.329779468
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.3965998428
Short name T556
Test name
Test status
Simulation time 21451707000 ps
CPU time 585.86 seconds
Started Aug 07 07:32:38 PM PDT 24
Finished Aug 07 07:42:24 PM PDT 24
Peak memory 329596 kb
Host smart-84effc29-632f-4772-b254-d4203f17dbdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965998428 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.3965998428
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.2279185625
Short name T592
Test name
Test status
Simulation time 3479390100 ps
CPU time 234.83 seconds
Started Aug 07 07:32:37 PM PDT 24
Finished Aug 07 07:36:32 PM PDT 24
Peak memory 285316 kb
Host smart-50c69864-b689-473d-bc60-bd601ea5ed94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279185625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.2279185625
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2997949659
Short name T1072
Test name
Test status
Simulation time 6283050300 ps
CPU time 138.71 seconds
Started Aug 07 07:32:34 PM PDT 24
Finished Aug 07 07:34:53 PM PDT 24
Peak memory 285568 kb
Host smart-bcdb110d-b363-469b-8aa7-50a18553b560
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997949659 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2997949659
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.248927201
Short name T27
Test name
Test status
Simulation time 8071722100 ps
CPU time 74.31 seconds
Started Aug 07 07:32:37 PM PDT 24
Finished Aug 07 07:33:51 PM PDT 24
Peak memory 260200 kb
Host smart-36dd4965-6429-4285-8806-8329ffb7ff92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248927201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_intr_wr.248927201
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3415134944
Short name T490
Test name
Test status
Simulation time 20364310200 ps
CPU time 176.59 seconds
Started Aug 07 07:32:35 PM PDT 24
Finished Aug 07 07:35:31 PM PDT 24
Peak memory 259980 kb
Host smart-5440907b-ad54-45ef-bbea-12bec461233d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341
5134944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3415134944
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.2317495208
Short name T535
Test name
Test status
Simulation time 6035464000 ps
CPU time 79.51 seconds
Started Aug 07 07:32:31 PM PDT 24
Finished Aug 07 07:33:51 PM PDT 24
Peak memory 263688 kb
Host smart-eb584025-62fe-4115-96b1-719e701bc673
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317495208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2317495208
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3535178934
Short name T716
Test name
Test status
Simulation time 15159200 ps
CPU time 13.62 seconds
Started Aug 07 07:32:52 PM PDT 24
Finished Aug 07 07:33:05 PM PDT 24
Peak memory 260448 kb
Host smart-7c867b8d-8543-4788-af59-231dd8aa60e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535178934 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3535178934
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3919184401
Short name T744
Test name
Test status
Simulation time 1929513000 ps
CPU time 154.78 seconds
Started Aug 07 07:32:21 PM PDT 24
Finished Aug 07 07:34:56 PM PDT 24
Peak memory 265400 kb
Host smart-909587a8-fb1a-4c67-9bc6-fe59703b7e60
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919184401 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.3919184401
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.714393365
Short name T745
Test name
Test status
Simulation time 65414200 ps
CPU time 112.53 seconds
Started Aug 07 07:32:25 PM PDT 24
Finished Aug 07 07:34:17 PM PDT 24
Peak memory 261196 kb
Host smart-42afac16-6cdb-401f-8cc0-e58c162da72b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714393365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp
_reset.714393365
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3383299593
Short name T49
Test name
Test status
Simulation time 2707073900 ps
CPU time 245.12 seconds
Started Aug 07 07:32:34 PM PDT 24
Finished Aug 07 07:36:39 PM PDT 24
Peak memory 282100 kb
Host smart-606c8dd4-f60c-4a14-9c6b-733ab5003682
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383299593 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3383299593
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3655829182
Short name T766
Test name
Test status
Simulation time 799182300 ps
CPU time 464.39 seconds
Started Aug 07 07:32:14 PM PDT 24
Finished Aug 07 07:39:58 PM PDT 24
Peak memory 263272 kb
Host smart-9b3f754c-0aef-4684-a819-40b3266df9bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655829182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3655829182
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1391515842
Short name T197
Test name
Test status
Simulation time 24581400 ps
CPU time 14.1 seconds
Started Aug 07 07:32:51 PM PDT 24
Finished Aug 07 07:33:05 PM PDT 24
Peak memory 263004 kb
Host smart-fda0797b-c5a7-40a1-9605-f6cbb711512f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391515842 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1391515842
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.2554137769
Short name T729
Test name
Test status
Simulation time 36060164600 ps
CPU time 235.53 seconds
Started Aug 07 07:32:36 PM PDT 24
Finished Aug 07 07:36:32 PM PDT 24
Peak memory 265328 kb
Host smart-46e48520-76b3-4d72-8f48-52ff8583bfa6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554137769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.flash_ctrl_prog_reset.2554137769
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.332989440
Short name T138
Test name
Test status
Simulation time 254668800 ps
CPU time 990.78 seconds
Started Aug 07 07:32:11 PM PDT 24
Finished Aug 07 07:48:42 PM PDT 24
Peak memory 286164 kb
Host smart-eca97775-b2f4-4309-944d-da265f0d5faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332989440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.332989440
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3249536805
Short name T769
Test name
Test status
Simulation time 322623900 ps
CPU time 100.24 seconds
Started Aug 07 07:32:11 PM PDT 24
Finished Aug 07 07:33:51 PM PDT 24
Peak memory 262948 kb
Host smart-eddba51c-dde2-4e4f-8e00-b416765014a0
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3249536805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3249536805
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.3734394175
Short name T497
Test name
Test status
Simulation time 65077900 ps
CPU time 32.93 seconds
Started Aug 07 07:32:49 PM PDT 24
Finished Aug 07 07:33:22 PM PDT 24
Peak memory 276020 kb
Host smart-e17dfea9-df99-4475-8ed8-831bd97f8d4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734394175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.3734394175
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.3560705153
Short name T739
Test name
Test status
Simulation time 217573200 ps
CPU time 37.13 seconds
Started Aug 07 07:32:34 PM PDT 24
Finished Aug 07 07:33:12 PM PDT 24
Peak memory 277788 kb
Host smart-80da9c62-ec89-4752-a5e6-95bbed00cff9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560705153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.3560705153
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.2308462441
Short name T1005
Test name
Test status
Simulation time 86690800 ps
CPU time 22.49 seconds
Started Aug 07 07:32:23 PM PDT 24
Finished Aug 07 07:32:46 PM PDT 24
Peak memory 265412 kb
Host smart-f9efede2-9721-4368-ab9e-bd44992ab45b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308462441 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.2308462441
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1655312692
Short name T584
Test name
Test status
Simulation time 24367100 ps
CPU time 22.94 seconds
Started Aug 07 07:32:23 PM PDT 24
Finished Aug 07 07:32:46 PM PDT 24
Peak memory 265604 kb
Host smart-b0410c8f-30e3-4780-9f40-d57a2b5abb5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655312692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1655312692
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.3809967010
Short name T186
Test name
Test status
Simulation time 165693360300 ps
CPU time 1004.41 seconds
Started Aug 07 07:32:48 PM PDT 24
Finished Aug 07 07:49:33 PM PDT 24
Peak memory 261704 kb
Host smart-817725f2-8f8f-4531-8746-05989413d299
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809967010 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.3809967010
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2579837020
Short name T748
Test name
Test status
Simulation time 1231319900 ps
CPU time 113.43 seconds
Started Aug 07 07:32:31 PM PDT 24
Finished Aug 07 07:34:25 PM PDT 24
Peak memory 282036 kb
Host smart-b2f65fff-268b-4dd6-9cf2-a12ffb73eaea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579837020 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.2579837020
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1793242846
Short name T835
Test name
Test status
Simulation time 607874500 ps
CPU time 156.55 seconds
Started Aug 07 07:32:26 PM PDT 24
Finished Aug 07 07:35:03 PM PDT 24
Peak memory 282116 kb
Host smart-da496cf6-0ea7-4cda-aa70-dda0b72ea78b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1793242846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1793242846
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.4152593658
Short name T698
Test name
Test status
Simulation time 578684200 ps
CPU time 146.07 seconds
Started Aug 07 07:32:24 PM PDT 24
Finished Aug 07 07:34:50 PM PDT 24
Peak memory 282096 kb
Host smart-dd8a134f-eb3e-4c75-85d4-50f2ddd5e1a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152593658 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.4152593658
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.4070196135
Short name T1085
Test name
Test status
Simulation time 14641616400 ps
CPU time 443.52 seconds
Started Aug 07 07:32:31 PM PDT 24
Finished Aug 07 07:39:55 PM PDT 24
Peak memory 314520 kb
Host smart-04278fdb-d35f-41a2-828a-0c7f3e0dab4b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070196135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.4070196135
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.339870
Short name T251
Test name
Test status
Simulation time 3232016600 ps
CPU time 233.44 seconds
Started Aug 07 07:32:23 PM PDT 24
Finished Aug 07 07:36:17 PM PDT 24
Peak memory 292076 kb
Host smart-4f4c0a20-6e51-4ccb-b149-e98656fc97f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339870 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_derr.339870
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.364113947
Short name T902
Test name
Test status
Simulation time 4894973400 ps
CPU time 178.84 seconds
Started Aug 07 07:32:21 PM PDT 24
Finished Aug 07 07:35:20 PM PDT 24
Peak memory 295768 kb
Host smart-a443ab0a-98c5-4564-ae38-18d8a80a23be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364113947 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rw_serr.364113947
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.2239930009
Short name T229
Test name
Test status
Simulation time 3493580400 ps
CPU time 64.15 seconds
Started Aug 07 07:32:37 PM PDT 24
Finished Aug 07 07:33:42 PM PDT 24
Peak memory 263892 kb
Host smart-90772047-5fc6-4887-ba1c-cdac8fc090ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239930009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2239930009
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.405931446
Short name T428
Test name
Test status
Simulation time 5298119800 ps
CPU time 67.65 seconds
Started Aug 07 07:32:25 PM PDT 24
Finished Aug 07 07:33:32 PM PDT 24
Peak memory 273892 kb
Host smart-bd01e1cc-402a-49b6-a069-f1c73914d98a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405931446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_serr_address.405931446
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.3315549310
Short name T961
Test name
Test status
Simulation time 1526283400 ps
CPU time 71.63 seconds
Started Aug 07 07:32:24 PM PDT 24
Finished Aug 07 07:33:36 PM PDT 24
Peak memory 274772 kb
Host smart-553e2a34-2e7e-4d4d-ad96-5666f92fd49e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315549310 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.3315549310
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3782380986
Short name T1041
Test name
Test status
Simulation time 47495000 ps
CPU time 77.99 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:33:31 PM PDT 24
Peak memory 275884 kb
Host smart-52dfa0f2-767b-481a-8239-5bc3d7315ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782380986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3782380986
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.3227647192
Short name T794
Test name
Test status
Simulation time 15701600 ps
CPU time 26.58 seconds
Started Aug 07 07:32:13 PM PDT 24
Finished Aug 07 07:32:40 PM PDT 24
Peak memory 259868 kb
Host smart-ce5847f3-1def-42d9-bffa-5140773b58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227647192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3227647192
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.3581849423
Short name T828
Test name
Test status
Simulation time 479092000 ps
CPU time 1357.87 seconds
Started Aug 07 07:32:35 PM PDT 24
Finished Aug 07 07:55:13 PM PDT 24
Peak memory 290008 kb
Host smart-559e2688-0a30-46b3-a08b-bdc4b88b6803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581849423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.3581849423
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2451344996
Short name T597
Test name
Test status
Simulation time 26112900 ps
CPU time 26.83 seconds
Started Aug 07 07:32:12 PM PDT 24
Finished Aug 07 07:32:39 PM PDT 24
Peak memory 259848 kb
Host smart-7ce82534-b348-4f07-bc8d-f9dba9877cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451344996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2451344996
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.1652158468
Short name T446
Test name
Test status
Simulation time 11377453300 ps
CPU time 234.43 seconds
Started Aug 07 07:32:24 PM PDT 24
Finished Aug 07 07:36:18 PM PDT 24
Peak memory 260260 kb
Host smart-a2cc30b6-e1e1-4f6c-9e98-0b4e9b6cbb71
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652158468 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.1652158468
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.3282051517
Short name T20
Test name
Test status
Simulation time 166571300 ps
CPU time 15.18 seconds
Started Aug 07 07:32:42 PM PDT 24
Finished Aug 07 07:32:57 PM PDT 24
Peak memory 260884 kb
Host smart-668da3e1-c231-4fc4-8667-e56b913eac25
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282051517 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3282051517
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.1679592935
Short name T422
Test name
Test status
Simulation time 367952400 ps
CPU time 13.77 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:37:32 PM PDT 24
Peak memory 265316 kb
Host smart-9318ea38-1034-44d6-82f0-6fa5d55cfc7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679592935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
1679592935
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.518506074
Short name T830
Test name
Test status
Simulation time 31536400 ps
CPU time 22.07 seconds
Started Aug 07 07:37:17 PM PDT 24
Finished Aug 07 07:37:39 PM PDT 24
Peak memory 273840 kb
Host smart-4b4674b1-a502-454f-ab72-8bfceeedb180
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518506074 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.518506074
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.4220687475
Short name T717
Test name
Test status
Simulation time 60358800 ps
CPU time 13.82 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:37:33 PM PDT 24
Peak memory 265084 kb
Host smart-da73ee2e-3db5-4b4a-af98-115325cf4736
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220687475 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.4220687475
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2134647263
Short name T172
Test name
Test status
Simulation time 80141583500 ps
CPU time 891.6 seconds
Started Aug 07 07:37:11 PM PDT 24
Finished Aug 07 07:52:03 PM PDT 24
Peak memory 264672 kb
Host smart-3d8d0eb3-2eee-4d9d-a670-d05929ac19f6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134647263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.2134647263
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.4021962100
Short name T468
Test name
Test status
Simulation time 31567470800 ps
CPU time 170.46 seconds
Started Aug 07 07:37:09 PM PDT 24
Finished Aug 07 07:40:00 PM PDT 24
Peak memory 260744 kb
Host smart-9d1abb5b-91b0-49c6-ac66-f75fc99f0ad6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021962100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.4021962100
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.990444456
Short name T503
Test name
Test status
Simulation time 28347109500 ps
CPU time 185.62 seconds
Started Aug 07 07:37:17 PM PDT 24
Finished Aug 07 07:40:23 PM PDT 24
Peak memory 293164 kb
Host smart-14d40b49-3de1-426e-a1c0-b711d1f54a46
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990444456 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.990444456
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.591831132
Short name T1100
Test name
Test status
Simulation time 2682500100 ps
CPU time 61.37 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:38:20 PM PDT 24
Peak memory 263112 kb
Host smart-714565ed-f542-4d10-93fe-637afa66c892
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591831132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.591831132
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3545821964
Short name T168
Test name
Test status
Simulation time 15085800 ps
CPU time 13.99 seconds
Started Aug 07 07:37:21 PM PDT 24
Finished Aug 07 07:37:35 PM PDT 24
Peak memory 265032 kb
Host smart-b3f5dcd9-90c5-4858-80d8-b3e0180f4fd3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545821964 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3545821964
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.4103461750
Short name T126
Test name
Test status
Simulation time 95853935600 ps
CPU time 899.65 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:52:19 PM PDT 24
Peak memory 274100 kb
Host smart-a627ea01-eb73-4aa6-93e5-da634b615a6f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103461750 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.4103461750
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.2494271140
Short name T107
Test name
Test status
Simulation time 70331400 ps
CPU time 130.94 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:39:30 PM PDT 24
Peak memory 261352 kb
Host smart-8233fbab-ec80-47d6-8a99-c329ea3dfa16
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494271140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.2494271140
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.1941376754
Short name T670
Test name
Test status
Simulation time 105860500 ps
CPU time 70.16 seconds
Started Aug 07 07:37:08 PM PDT 24
Finished Aug 07 07:38:19 PM PDT 24
Peak memory 263456 kb
Host smart-fa7c0710-0555-44f4-9e3b-bf21e8a1ceb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941376754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.1941376754
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.517062621
Short name T800
Test name
Test status
Simulation time 63189400 ps
CPU time 13.5 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:37:31 PM PDT 24
Peak memory 265344 kb
Host smart-7a3b34ec-b82e-4709-a0f5-b6fceb9ebaf1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517062621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.flash_ctrl_prog_reset.517062621
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2956418542
Short name T607
Test name
Test status
Simulation time 32176100 ps
CPU time 77.44 seconds
Started Aug 07 07:37:11 PM PDT 24
Finished Aug 07 07:38:29 PM PDT 24
Peak memory 275748 kb
Host smart-a682efc3-5615-4d0f-ab8d-80e2ead46c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956418542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2956418542
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.2221513110
Short name T1037
Test name
Test status
Simulation time 655972400 ps
CPU time 33.96 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:37:52 PM PDT 24
Peak memory 273916 kb
Host smart-4cebccd1-b88c-4990-a393-4327d816769b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221513110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.2221513110
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.756325706
Short name T669
Test name
Test status
Simulation time 5871403800 ps
CPU time 132.42 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:39:31 PM PDT 24
Peak memory 281400 kb
Host smart-b870470f-287f-4428-b491-c792ec952987
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756325706 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.flash_ctrl_ro.756325706
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1534281194
Short name T613
Test name
Test status
Simulation time 2990783400 ps
CPU time 632.41 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:47:51 PM PDT 24
Peak memory 310524 kb
Host smart-79974cae-2dfc-4930-8092-1c2cae70f9c3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534281194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.1534281194
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1064059467
Short name T343
Test name
Test status
Simulation time 86828500 ps
CPU time 29.52 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:37:48 PM PDT 24
Peak memory 273860 kb
Host smart-49c61d69-023e-4c48-96ea-a8c7794d1e0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064059467 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1064059467
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.70537592
Short name T1103
Test name
Test status
Simulation time 29944200 ps
CPU time 148.05 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:39:39 PM PDT 24
Peak memory 277020 kb
Host smart-91d35bf5-ad4e-4cfb-b34b-ad2e86c67b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70537592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.70537592
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.3260833878
Short name T805
Test name
Test status
Simulation time 2145168100 ps
CPU time 150.72 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:39:50 PM PDT 24
Peak memory 259624 kb
Host smart-89598921-cbd4-491e-9f76-f12b7474fd6c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260833878 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.3260833878
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1237179184
Short name T586
Test name
Test status
Simulation time 28956200 ps
CPU time 13.74 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:37:42 PM PDT 24
Peak memory 258416 kb
Host smart-000832f8-17cb-4fe3-b875-9ec8c50b6cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237179184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1237179184
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.3974174511
Short name T894
Test name
Test status
Simulation time 25572200 ps
CPU time 13.47 seconds
Started Aug 07 07:37:29 PM PDT 24
Finished Aug 07 07:37:42 PM PDT 24
Peak memory 283364 kb
Host smart-0ff427fc-8af7-4a2f-8dfe-253d7496e8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974174511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3974174511
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1405534981
Short name T108
Test name
Test status
Simulation time 10031230100 ps
CPU time 66.04 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:38:33 PM PDT 24
Peak memory 293352 kb
Host smart-80b2486f-0255-4d60-b1a3-5b22a1c9e46f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405534981 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1405534981
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3818069845
Short name T932
Test name
Test status
Simulation time 24769200 ps
CPU time 13.38 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:37:39 PM PDT 24
Peak memory 265028 kb
Host smart-e05830ca-2837-4d51-89cd-da9706729902
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818069845 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3818069845
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3467986491
Short name T997
Test name
Test status
Simulation time 160174711600 ps
CPU time 905.43 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:52:24 PM PDT 24
Peak memory 264548 kb
Host smart-99a410b2-4cba-4b23-840f-8910ac0140e3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467986491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3467986491
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2421414666
Short name T815
Test name
Test status
Simulation time 16017584200 ps
CPU time 113.54 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:39:11 PM PDT 24
Peak memory 263472 kb
Host smart-1583e59c-a5a7-4577-97ee-aa3c47e90d8f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421414666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.2421414666
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.585695379
Short name T1019
Test name
Test status
Simulation time 3349133000 ps
CPU time 172.82 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:40:12 PM PDT 24
Peak memory 294516 kb
Host smart-6dcc8ce4-c954-4362-bcc5-9a9a83fcb9a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585695379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas
h_ctrl_intr_rd.585695379
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.607240283
Short name T863
Test name
Test status
Simulation time 206549650600 ps
CPU time 513.18 seconds
Started Aug 07 07:37:20 PM PDT 24
Finished Aug 07 07:45:53 PM PDT 24
Peak memory 290112 kb
Host smart-04d63bba-162f-478f-b41f-8ff03ba5ff11
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607240283 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.607240283
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.3147311338
Short name T139
Test name
Test status
Simulation time 9009055900 ps
CPU time 82.14 seconds
Started Aug 07 07:37:21 PM PDT 24
Finished Aug 07 07:38:43 PM PDT 24
Peak memory 260808 kb
Host smart-d3d93e04-f733-46ce-8cd7-386e88d3776d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147311338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3
147311338
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1082139056
Short name T763
Test name
Test status
Simulation time 25013500 ps
CPU time 13.55 seconds
Started Aug 07 07:37:25 PM PDT 24
Finished Aug 07 07:37:39 PM PDT 24
Peak memory 265036 kb
Host smart-7f204846-f83a-409a-a1cd-6560dd2e7b72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082139056 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1082139056
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.1325312750
Short name T899
Test name
Test status
Simulation time 3597707700 ps
CPU time 127.23 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:39:27 PM PDT 24
Peak memory 265400 kb
Host smart-6fa5fa2a-5ea2-46dc-acb0-09651305cce6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325312750 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.1325312750
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1088251868
Short name T471
Test name
Test status
Simulation time 611018400 ps
CPU time 194.84 seconds
Started Aug 07 07:37:18 PM PDT 24
Finished Aug 07 07:40:33 PM PDT 24
Peak memory 263396 kb
Host smart-109854ab-7002-4667-abc3-c9d619b9ecc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088251868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1088251868
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2502748041
Short name T992
Test name
Test status
Simulation time 175623700 ps
CPU time 26.19 seconds
Started Aug 07 07:37:30 PM PDT 24
Finished Aug 07 07:37:56 PM PDT 24
Peak memory 265496 kb
Host smart-df637040-c3ee-4ad2-b96a-53a619e05cfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502748041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.flash_ctrl_prog_reset.2502748041
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.1712300035
Short name T569
Test name
Test status
Simulation time 813334500 ps
CPU time 741.71 seconds
Started Aug 07 07:37:20 PM PDT 24
Finished Aug 07 07:49:42 PM PDT 24
Peak memory 284348 kb
Host smart-973ca410-da71-49d0-81b4-c2c4c605edd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712300035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1712300035
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.1314449215
Short name T1011
Test name
Test status
Simulation time 433211800 ps
CPU time 33.58 seconds
Started Aug 07 07:37:25 PM PDT 24
Finished Aug 07 07:37:59 PM PDT 24
Peak memory 278016 kb
Host smart-e2ad9905-b1dc-4a09-b906-dd3fd78f35c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314449215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.1314449215
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.967061828
Short name T542
Test name
Test status
Simulation time 2139368100 ps
CPU time 145.83 seconds
Started Aug 07 07:37:20 PM PDT 24
Finished Aug 07 07:39:46 PM PDT 24
Peak memory 291508 kb
Host smart-e02529f4-b1b6-4bee-ab7c-d261ed14dbaa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967061828 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.flash_ctrl_ro.967061828
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.2806758144
Short name T1032
Test name
Test status
Simulation time 20797470100 ps
CPU time 682.01 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:48:41 PM PDT 24
Peak memory 309908 kb
Host smart-a731f9d5-56c7-44c0-b6c6-cd4072cf3563
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806758144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.2806758144
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.3133107793
Short name T709
Test name
Test status
Simulation time 29052700 ps
CPU time 30.03 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:37:58 PM PDT 24
Peak memory 273896 kb
Host smart-e34c85a0-a7b3-44fe-b0e1-a9657b2955fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133107793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.3133107793
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2123162655
Short name T40
Test name
Test status
Simulation time 31236300 ps
CPU time 31.51 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:37:57 PM PDT 24
Peak memory 273888 kb
Host smart-5f38e536-5368-4aa4-b270-393a6489c0c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123162655 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2123162655
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3396396082
Short name T655
Test name
Test status
Simulation time 3142424900 ps
CPU time 69.2 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:38:37 PM PDT 24
Peak memory 263960 kb
Host smart-648b24e5-ea8d-4c72-8000-6a25cdc18d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396396082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3396396082
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.4288761676
Short name T989
Test name
Test status
Simulation time 25499100 ps
CPU time 96.97 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:38:56 PM PDT 24
Peak memory 275784 kb
Host smart-2a076be1-7386-4650-b2b8-fead26fe8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288761676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.4288761676
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3663129712
Short name T447
Test name
Test status
Simulation time 8207845100 ps
CPU time 176.92 seconds
Started Aug 07 07:37:19 PM PDT 24
Finished Aug 07 07:40:16 PM PDT 24
Peak memory 265468 kb
Host smart-8e885ca0-7225-4cc8-a485-20e3a64f0bc4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663129712 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.3663129712
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1380627817
Short name T699
Test name
Test status
Simulation time 46814000 ps
CPU time 13.41 seconds
Started Aug 07 07:37:48 PM PDT 24
Finished Aug 07 07:38:02 PM PDT 24
Peak memory 258572 kb
Host smart-1c891930-41d7-4d79-b940-fea21f464f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380627817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1380627817
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.619033869
Short name T931
Test name
Test status
Simulation time 22498400 ps
CPU time 15.77 seconds
Started Aug 07 07:37:49 PM PDT 24
Finished Aug 07 07:38:05 PM PDT 24
Peak memory 283432 kb
Host smart-4faf0830-af93-41b0-9375-27075a0b1a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619033869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.619033869
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.4206021037
Short name T795
Test name
Test status
Simulation time 11625000 ps
CPU time 21.92 seconds
Started Aug 07 07:37:38 PM PDT 24
Finished Aug 07 07:38:00 PM PDT 24
Peak memory 273840 kb
Host smart-a8c9e4b4-36bb-45a5-a879-ace47fa4ff3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206021037 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.4206021037
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2283488490
Short name T781
Test name
Test status
Simulation time 47320100 ps
CPU time 13.42 seconds
Started Aug 07 07:37:49 PM PDT 24
Finished Aug 07 07:38:03 PM PDT 24
Peak memory 264936 kb
Host smart-6dfdcf01-89d8-4814-9083-db12ed4a7ac5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283488490 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2283488490
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2881260826
Short name T868
Test name
Test status
Simulation time 80149267000 ps
CPU time 894.53 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:52:23 PM PDT 24
Peak memory 260996 kb
Host smart-547c6525-2755-4265-b8dd-d7489f304b79
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881260826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.2881260826
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3810768682
Short name T814
Test name
Test status
Simulation time 4068686500 ps
CPU time 104.96 seconds
Started Aug 07 07:37:24 PM PDT 24
Finished Aug 07 07:39:09 PM PDT 24
Peak memory 260816 kb
Host smart-3779d1a8-eec4-45af-b8be-fdfa18fdf373
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810768682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.3810768682
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.1324411540
Short name T765
Test name
Test status
Simulation time 1872531400 ps
CPU time 168.06 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:40:14 PM PDT 24
Peak memory 294476 kb
Host smart-c2369480-da2b-4fa2-9811-e3411b983e89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324411540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.1324411540
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.269910139
Short name T318
Test name
Test status
Simulation time 49777081300 ps
CPU time 504.33 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:45:51 PM PDT 24
Peak memory 285428 kb
Host smart-b62ae656-a706-4da6-98c0-1a31ca4d126c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269910139 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.269910139
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2762083464
Short name T897
Test name
Test status
Simulation time 6493373800 ps
CPU time 68.38 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:38:36 PM PDT 24
Peak memory 260820 kb
Host smart-227cdef3-a6c3-43c0-a1fd-de038dd88b99
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762083464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
762083464
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.714157002
Short name T714
Test name
Test status
Simulation time 11030277400 ps
CPU time 273.84 seconds
Started Aug 07 07:37:27 PM PDT 24
Finished Aug 07 07:42:01 PM PDT 24
Peak memory 275400 kb
Host smart-0bae38f4-0d55-4158-b0b9-1cf819613b29
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714157002 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.714157002
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1633417553
Short name T1079
Test name
Test status
Simulation time 75940200 ps
CPU time 111.13 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:39:17 PM PDT 24
Peak memory 264352 kb
Host smart-96f44650-1ffa-49cd-96d3-4932c6d12512
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633417553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1633417553
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1832892997
Short name T564
Test name
Test status
Simulation time 61442200 ps
CPU time 66.87 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:38:35 PM PDT 24
Peak memory 263536 kb
Host smart-c54c1f56-6e71-4baf-aad4-87c84212373d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832892997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1832892997
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3722691524
Short name T408
Test name
Test status
Simulation time 117856600 ps
CPU time 17.09 seconds
Started Aug 07 07:37:38 PM PDT 24
Finished Aug 07 07:37:55 PM PDT 24
Peak memory 260180 kb
Host smart-53db1ccb-2e59-43d4-8202-c4f30b39f93b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722691524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.flash_ctrl_prog_reset.3722691524
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.3089128953
Short name T132
Test name
Test status
Simulation time 8306729300 ps
CPU time 1327.68 seconds
Started Aug 07 07:37:29 PM PDT 24
Finished Aug 07 07:59:37 PM PDT 24
Peak memory 300136 kb
Host smart-585b1ac2-c288-4dde-aefd-4eb83f13119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089128953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3089128953
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.3874046342
Short name T24
Test name
Test status
Simulation time 122990700 ps
CPU time 35.3 seconds
Started Aug 07 07:37:37 PM PDT 24
Finished Aug 07 07:38:12 PM PDT 24
Peak memory 276224 kb
Host smart-61c209e9-42dc-4b7f-90c1-bf947fc50e29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874046342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.3874046342
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.399767861
Short name T807
Test name
Test status
Simulation time 2135419000 ps
CPU time 117.36 seconds
Started Aug 07 07:37:28 PM PDT 24
Finished Aug 07 07:39:25 PM PDT 24
Peak memory 282032 kb
Host smart-6b78ed05-4902-444d-b728-df4b6ed32823
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399767861 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.flash_ctrl_ro.399767861
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2108924064
Short name T650
Test name
Test status
Simulation time 13456255200 ps
CPU time 627.48 seconds
Started Aug 07 07:37:25 PM PDT 24
Finished Aug 07 07:47:53 PM PDT 24
Peak memory 314592 kb
Host smart-e27e237d-4fed-4e49-b2f3-684ebddd5420
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108924064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.2108924064
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1576080497
Short name T572
Test name
Test status
Simulation time 49148500 ps
CPU time 32.37 seconds
Started Aug 07 07:37:37 PM PDT 24
Finished Aug 07 07:38:10 PM PDT 24
Peak memory 275888 kb
Host smart-087965ff-2731-48be-b607-b498553b9f88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576080497 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1576080497
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2784406737
Short name T387
Test name
Test status
Simulation time 4598197100 ps
CPU time 78.93 seconds
Started Aug 07 07:37:51 PM PDT 24
Finished Aug 07 07:39:10 PM PDT 24
Peak memory 262884 kb
Host smart-cfe8a375-d30d-4ba9-91cc-ce04873ac733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784406737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2784406737
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2829035840
Short name T224
Test name
Test status
Simulation time 30393800 ps
CPU time 98.82 seconds
Started Aug 07 07:37:26 PM PDT 24
Finished Aug 07 07:39:05 PM PDT 24
Peak memory 276324 kb
Host smart-52a3db1f-d158-4edd-bbe5-c8c0c39cbc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829035840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2829035840
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.2260240395
Short name T1076
Test name
Test status
Simulation time 1608589200 ps
CPU time 118.06 seconds
Started Aug 07 07:37:27 PM PDT 24
Finished Aug 07 07:39:25 PM PDT 24
Peak memory 259608 kb
Host smart-fc702f08-cbc6-4bb8-b769-00e693c64969
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260240395 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.2260240395
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.1719248954
Short name T645
Test name
Test status
Simulation time 42618000 ps
CPU time 13.87 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:38:26 PM PDT 24
Peak memory 258420 kb
Host smart-48563bc5-def5-4304-991f-c601f7700a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719248954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
1719248954
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.3151046918
Short name T799
Test name
Test status
Simulation time 14836200 ps
CPU time 16.2 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:38:28 PM PDT 24
Peak memory 284660 kb
Host smart-62554cb3-197b-4137-9507-9d6dc7f4429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151046918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.3151046918
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3460510341
Short name T832
Test name
Test status
Simulation time 26319100 ps
CPU time 21.93 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:38:34 PM PDT 24
Peak memory 273832 kb
Host smart-23bea9c9-4ab6-40fa-be28-073aa5698c0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460510341 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3460510341
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.680204375
Short name T495
Test name
Test status
Simulation time 10019801500 ps
CPU time 87.26 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:39:39 PM PDT 24
Peak memory 293324 kb
Host smart-33660a8d-1f56-46d2-bd19-1c2c7371cbda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680204375 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.680204375
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3176294902
Short name T789
Test name
Test status
Simulation time 15373500 ps
CPU time 13.86 seconds
Started Aug 07 07:38:11 PM PDT 24
Finished Aug 07 07:38:25 PM PDT 24
Peak memory 264796 kb
Host smart-b4d6b4d5-3920-43a2-a5a4-620ddb3ab256
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176294902 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3176294902
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2984818489
Short name T171
Test name
Test status
Simulation time 130170900800 ps
CPU time 910.06 seconds
Started Aug 07 07:38:01 PM PDT 24
Finished Aug 07 07:53:11 PM PDT 24
Peak memory 264580 kb
Host smart-40e0496e-9d22-4234-bc3f-16bc25d81b62
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984818489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2984818489
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.750900691
Short name T810
Test name
Test status
Simulation time 8893412700 ps
CPU time 96.9 seconds
Started Aug 07 07:37:50 PM PDT 24
Finished Aug 07 07:39:27 PM PDT 24
Peak memory 263048 kb
Host smart-bd0d6eb0-8264-4092-b395-cea913e6e3b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750900691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_h
w_sec_otp.750900691
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.433099382
Short name T879
Test name
Test status
Simulation time 1617798400 ps
CPU time 258.77 seconds
Started Aug 07 07:38:00 PM PDT 24
Finished Aug 07 07:42:19 PM PDT 24
Peak memory 285484 kb
Host smart-e3b3d919-2419-4ec3-a5eb-872bb9bfa0a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433099382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flas
h_ctrl_intr_rd.433099382
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1998854629
Short name T324
Test name
Test status
Simulation time 20206560400 ps
CPU time 175.17 seconds
Started Aug 07 07:38:00 PM PDT 24
Finished Aug 07 07:40:55 PM PDT 24
Peak memory 295548 kb
Host smart-4e2e5d4c-dc0e-4adc-be27-7b132ce6737b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998854629 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.1998854629
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.1469585914
Short name T1059
Test name
Test status
Simulation time 974732400 ps
CPU time 91.36 seconds
Started Aug 07 07:38:00 PM PDT 24
Finished Aug 07 07:39:31 PM PDT 24
Peak memory 263840 kb
Host smart-1042fd39-8885-4d64-8a31-90b857ab0f12
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469585914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1
469585914
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2165229741
Short name T782
Test name
Test status
Simulation time 24979500 ps
CPU time 13.74 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:38:26 PM PDT 24
Peak memory 264992 kb
Host smart-ddbeb530-5300-44f6-a41b-7b7efd271afb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165229741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2165229741
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.906875954
Short name T142
Test name
Test status
Simulation time 8913375000 ps
CPU time 715.13 seconds
Started Aug 07 07:37:59 PM PDT 24
Finished Aug 07 07:49:55 PM PDT 24
Peak memory 274912 kb
Host smart-632024b2-7667-47f9-b1c7-1313b0af8e8c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906875954 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.906875954
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.3465588998
Short name T73
Test name
Test status
Simulation time 39707400 ps
CPU time 111.38 seconds
Started Aug 07 07:38:02 PM PDT 24
Finished Aug 07 07:39:54 PM PDT 24
Peak memory 260268 kb
Host smart-fe3fc5c4-69a8-4875-b9bb-c4b3e404583e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465588998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.3465588998
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.3853978125
Short name T223
Test name
Test status
Simulation time 248671000 ps
CPU time 281.83 seconds
Started Aug 07 07:37:49 PM PDT 24
Finished Aug 07 07:42:31 PM PDT 24
Peak memory 263340 kb
Host smart-03c8598c-43c8-4527-915f-04e89f67723f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3853978125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3853978125
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.4229005638
Short name T861
Test name
Test status
Simulation time 124700500 ps
CPU time 13.94 seconds
Started Aug 07 07:38:03 PM PDT 24
Finished Aug 07 07:38:17 PM PDT 24
Peak memory 265320 kb
Host smart-eab9639b-4c5d-48ff-b7a2-1578643a1ee4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229005638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.flash_ctrl_prog_reset.4229005638
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.528024626
Short name T1023
Test name
Test status
Simulation time 123310100 ps
CPU time 553.33 seconds
Started Aug 07 07:37:49 PM PDT 24
Finished Aug 07 07:47:03 PM PDT 24
Peak memory 282636 kb
Host smart-ccf9b252-e030-49e8-9e94-dd19fbe7a3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528024626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.528024626
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.1960007364
Short name T278
Test name
Test status
Simulation time 1920004300 ps
CPU time 106.98 seconds
Started Aug 07 07:38:00 PM PDT 24
Finished Aug 07 07:39:47 PM PDT 24
Peak memory 282092 kb
Host smart-d2366f21-9d9a-4b79-8a8d-853c53716b0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960007364 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.1960007364
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.86176908
Short name T352
Test name
Test status
Simulation time 29392800 ps
CPU time 31.25 seconds
Started Aug 07 07:38:00 PM PDT 24
Finished Aug 07 07:38:31 PM PDT 24
Peak memory 273880 kb
Host smart-a06b2447-9818-485b-b596-df81b68f7445
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86176908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flas
h_ctrl_rw_evict.86176908
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.2112663484
Short name T811
Test name
Test status
Simulation time 46870400 ps
CPU time 31.07 seconds
Started Aug 07 07:38:13 PM PDT 24
Finished Aug 07 07:38:44 PM PDT 24
Peak memory 273860 kb
Host smart-7291334e-fcd5-4bf2-af6d-0746265e1aa3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112663484 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.2112663484
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.1792756269
Short name T425
Test name
Test status
Simulation time 561295400 ps
CPU time 61.01 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:39:13 PM PDT 24
Peak memory 264368 kb
Host smart-aba3cbed-8f1e-46cc-a434-2d7a0a099c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792756269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.1792756269
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.4250360266
Short name T1033
Test name
Test status
Simulation time 25729700 ps
CPU time 153.38 seconds
Started Aug 07 07:37:49 PM PDT 24
Finished Aug 07 07:40:23 PM PDT 24
Peak memory 270200 kb
Host smart-e5123102-89b2-4416-9dd8-95d4d2c83cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250360266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.4250360266
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.2471931659
Short name T1078
Test name
Test status
Simulation time 6564379000 ps
CPU time 125.16 seconds
Started Aug 07 07:38:01 PM PDT 24
Finished Aug 07 07:40:06 PM PDT 24
Peak memory 260176 kb
Host smart-91e0dcbd-3267-4ec7-adac-7b7581daf887
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471931659 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.2471931659
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3773504650
Short name T1088
Test name
Test status
Simulation time 26179100 ps
CPU time 13.57 seconds
Started Aug 07 07:38:22 PM PDT 24
Finished Aug 07 07:38:35 PM PDT 24
Peak memory 258288 kb
Host smart-9adf3a78-1af8-46e8-857e-fd36017e8b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773504650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3773504650
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.805888865
Short name T479
Test name
Test status
Simulation time 22227100 ps
CPU time 13.88 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:38:37 PM PDT 24
Peak memory 283440 kb
Host smart-6a9cf6e2-84f5-4014-8670-8957527540bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805888865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.805888865
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1676932690
Short name T764
Test name
Test status
Simulation time 10011619100 ps
CPU time 147.85 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:40:51 PM PDT 24
Peak memory 374820 kb
Host smart-7f0c9acc-c2ac-4b47-9157-76701c2c6ec5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676932690 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1676932690
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.310217530
Short name T283
Test name
Test status
Simulation time 40910700 ps
CPU time 13.63 seconds
Started Aug 07 07:38:25 PM PDT 24
Finished Aug 07 07:38:38 PM PDT 24
Peak memory 265048 kb
Host smart-97ae3936-6a42-485b-808d-21b2513b8e7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310217530 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.310217530
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2052926320
Short name T190
Test name
Test status
Simulation time 80139632100 ps
CPU time 926.79 seconds
Started Aug 07 07:38:12 PM PDT 24
Finished Aug 07 07:53:39 PM PDT 24
Peak memory 261168 kb
Host smart-b53a445d-c316-45d3-9b94-5945f5bb4f9d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052926320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.2052926320
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2131906256
Short name T625
Test name
Test status
Simulation time 4042553900 ps
CPU time 70.47 seconds
Started Aug 07 07:38:08 PM PDT 24
Finished Aug 07 07:39:18 PM PDT 24
Peak memory 263428 kb
Host smart-4f78fdac-59eb-4f0c-b9fa-deca1cd7b4bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131906256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2131906256
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.1134469607
Short name T723
Test name
Test status
Simulation time 1647542900 ps
CPU time 190.98 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:41:34 PM PDT 24
Peak memory 291208 kb
Host smart-5375b4d5-163a-496a-9f40-d43fcaa62f6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134469607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.1134469607
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1414314488
Short name T656
Test name
Test status
Simulation time 12449397800 ps
CPU time 266.33 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:42:50 PM PDT 24
Peak memory 285452 kb
Host smart-387af8a6-185c-46d7-a065-0f6d9d2872b5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414314488 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1414314488
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1558125776
Short name T978
Test name
Test status
Simulation time 26215600 ps
CPU time 13.52 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:38:37 PM PDT 24
Peak memory 260408 kb
Host smart-ec3fb8c6-e0c0-42b7-b929-a7f66bbd4cd8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558125776 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.1558125776
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2246207513
Short name T974
Test name
Test status
Simulation time 173132993300 ps
CPU time 423.85 seconds
Started Aug 07 07:38:11 PM PDT 24
Finished Aug 07 07:45:15 PM PDT 24
Peak memory 275404 kb
Host smart-5c4bdf76-84f7-4067-a5f6-16cd698796d7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246207513 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2246207513
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.557745752
Short name T419
Test name
Test status
Simulation time 38184700 ps
CPU time 135.05 seconds
Started Aug 07 07:38:11 PM PDT 24
Finished Aug 07 07:40:26 PM PDT 24
Peak memory 260272 kb
Host smart-4cbeb3a4-1296-4053-a1b3-4ea38417701a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557745752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ot
p_reset.557745752
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.2465588763
Short name T912
Test name
Test status
Simulation time 860877600 ps
CPU time 461.41 seconds
Started Aug 07 07:38:13 PM PDT 24
Finished Aug 07 07:45:54 PM PDT 24
Peak memory 263548 kb
Host smart-652fbabf-6009-4304-9ebf-b95fd036ea48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465588763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2465588763
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.355411042
Short name T641
Test name
Test status
Simulation time 8228500000 ps
CPU time 185.73 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:41:29 PM PDT 24
Peak memory 260792 kb
Host smart-00d78b44-7536-4776-a0f8-e429bde4c241
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355411042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.flash_ctrl_prog_reset.355411042
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.2018349954
Short name T687
Test name
Test status
Simulation time 373218200 ps
CPU time 1039.85 seconds
Started Aug 07 07:38:11 PM PDT 24
Finished Aug 07 07:55:32 PM PDT 24
Peak memory 285564 kb
Host smart-6926d0c6-b7fa-47b2-9c83-0d16a226254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018349954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2018349954
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.2457145279
Short name T1024
Test name
Test status
Simulation time 60216100 ps
CPU time 34.24 seconds
Started Aug 07 07:38:22 PM PDT 24
Finished Aug 07 07:38:57 PM PDT 24
Peak memory 276216 kb
Host smart-06ab80fd-1400-48a1-ae7c-516a075b0e0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457145279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.2457145279
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3872210909
Short name T872
Test name
Test status
Simulation time 8553028500 ps
CPU time 135.4 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:40:39 PM PDT 24
Peak memory 289600 kb
Host smart-814fab6c-4283-49b2-83f4-dd52b3ad8b73
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872210909 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.3872210909
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1244495524
Short name T532
Test name
Test status
Simulation time 7644530000 ps
CPU time 653.47 seconds
Started Aug 07 07:38:22 PM PDT 24
Finished Aug 07 07:49:16 PM PDT 24
Peak memory 314576 kb
Host smart-759e85dc-61ea-4969-8170-a8f26a77c494
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244495524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1244495524
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2409127876
Short name T351
Test name
Test status
Simulation time 29056800 ps
CPU time 27.95 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:38:52 PM PDT 24
Peak memory 273908 kb
Host smart-daa98a48-1fcf-48c6-b163-cf90119cefff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409127876 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.2409127876
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.1990342195
Short name T1054
Test name
Test status
Simulation time 23849600 ps
CPU time 149.84 seconds
Started Aug 07 07:38:13 PM PDT 24
Finished Aug 07 07:40:43 PM PDT 24
Peak memory 277904 kb
Host smart-a5995cfa-94c5-427c-a55a-361cdd89e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990342195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1990342195
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1107381070
Short name T964
Test name
Test status
Simulation time 3705067200 ps
CPU time 160.03 seconds
Started Aug 07 07:38:25 PM PDT 24
Finished Aug 07 07:41:05 PM PDT 24
Peak memory 265440 kb
Host smart-2137032d-81fa-4963-977a-b2210abc392f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107381070 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.1107381070
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.4064317298
Short name T426
Test name
Test status
Simulation time 60998900 ps
CPU time 13.89 seconds
Started Aug 07 07:38:49 PM PDT 24
Finished Aug 07 07:39:03 PM PDT 24
Peak memory 258440 kb
Host smart-968bb3b2-b7a6-4070-8cdb-4ca272bc19eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064317298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
4064317298
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.73010911
Short name T735
Test name
Test status
Simulation time 100724200 ps
CPU time 16.35 seconds
Started Aug 07 07:38:37 PM PDT 24
Finished Aug 07 07:38:53 PM PDT 24
Peak memory 283476 kb
Host smart-11461250-e7de-41eb-b556-4d7676f909d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73010911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.73010911
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2780419729
Short name T365
Test name
Test status
Simulation time 17309500 ps
CPU time 21.7 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:38:56 PM PDT 24
Peak memory 273836 kb
Host smart-9413f05f-f070-4635-93c4-bb72dc7391dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780419729 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2780419729
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1041216943
Short name T996
Test name
Test status
Simulation time 10018969700 ps
CPU time 185.49 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:41:53 PM PDT 24
Peak memory 293600 kb
Host smart-9fcf4c2b-dda9-4bd2-a0cf-eb91b6530b85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041216943 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.1041216943
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2762085132
Short name T331
Test name
Test status
Simulation time 214639600 ps
CPU time 13.41 seconds
Started Aug 07 07:38:37 PM PDT 24
Finished Aug 07 07:38:50 PM PDT 24
Peak memory 260352 kb
Host smart-75e38c52-8649-43c5-b06e-369ebe7cee79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762085132 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2762085132
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.1134676111
Short name T191
Test name
Test status
Simulation time 40126600300 ps
CPU time 878.95 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:53:03 PM PDT 24
Peak memory 264608 kb
Host smart-624d705e-0d71-497d-ae82-4a1ffd01f390
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134676111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.1134676111
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2438124994
Short name T1075
Test name
Test status
Simulation time 12103760000 ps
CPU time 165.43 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:41:09 PM PDT 24
Peak memory 263340 kb
Host smart-ad4f112f-c3d7-4753-8ffb-52e871df03b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438124994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2438124994
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.1423359705
Short name T322
Test name
Test status
Simulation time 1749412200 ps
CPU time 239.7 seconds
Started Aug 07 07:38:33 PM PDT 24
Finished Aug 07 07:42:33 PM PDT 24
Peak memory 285416 kb
Host smart-1858e88e-b7f8-41c5-9571-e9f2fbe2d77a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423359705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.1423359705
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2590808744
Short name T595
Test name
Test status
Simulation time 16240119500 ps
CPU time 167.76 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:41:22 PM PDT 24
Peak memory 293012 kb
Host smart-85ae3a62-8936-4e08-9b85-88ab20361571
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590808744 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2590808744
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.7211975
Short name T401
Test name
Test status
Simulation time 2030980800 ps
CPU time 76.17 seconds
Started Aug 07 07:38:36 PM PDT 24
Finished Aug 07 07:39:52 PM PDT 24
Peak memory 261112 kb
Host smart-26509cf8-b1b5-485c-a013-fd60ce168756
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7211975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.7211975
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2462461216
Short name T167
Test name
Test status
Simulation time 24524900 ps
CPU time 13.55 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:38:48 PM PDT 24
Peak memory 260348 kb
Host smart-a216eb64-ebfd-440c-8127-a10a316d5717
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462461216 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.2462461216
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3853002106
Short name T130
Test name
Test status
Simulation time 14242479300 ps
CPU time 423.02 seconds
Started Aug 07 07:38:22 PM PDT 24
Finished Aug 07 07:45:25 PM PDT 24
Peak memory 274556 kb
Host smart-59140cbc-5727-4867-a8fb-3f24e5bdc434
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853002106 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.3853002106
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.4277966312
Short name T530
Test name
Test status
Simulation time 117826800 ps
CPU time 132.52 seconds
Started Aug 07 07:38:22 PM PDT 24
Finished Aug 07 07:40:35 PM PDT 24
Peak memory 260388 kb
Host smart-84e31cce-53cf-42ee-a096-a392b533ed70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277966312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.4277966312
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2068671491
Short name T882
Test name
Test status
Simulation time 50196500 ps
CPU time 66.87 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:39:30 PM PDT 24
Peak memory 263536 kb
Host smart-372ade14-4cf3-40dd-bf9a-0aeaa0a79e38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068671491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2068671491
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.3233259434
Short name T1018
Test name
Test status
Simulation time 68254100 ps
CPU time 13.69 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:38:48 PM PDT 24
Peak memory 259168 kb
Host smart-850ba922-a5cd-4387-9de9-08bb30a17470
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233259434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.flash_ctrl_prog_reset.3233259434
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.410880994
Short name T824
Test name
Test status
Simulation time 419002800 ps
CPU time 834.15 seconds
Started Aug 07 07:38:23 PM PDT 24
Finished Aug 07 07:52:18 PM PDT 24
Peak memory 283780 kb
Host smart-565d2f09-dc8d-43d0-b13d-c44191d9d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410880994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.410880994
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.4220339628
Short name T774
Test name
Test status
Simulation time 237094100 ps
CPU time 34.28 seconds
Started Aug 07 07:38:36 PM PDT 24
Finished Aug 07 07:39:10 PM PDT 24
Peak memory 276152 kb
Host smart-e15cc324-e263-468a-99a6-b74069ed1885
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220339628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.4220339628
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.97148535
Short name T930
Test name
Test status
Simulation time 5104493500 ps
CPU time 113.08 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:40:27 PM PDT 24
Peak memory 281452 kb
Host smart-37989bf1-590e-4508-a4e1-b1991dce5319
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97148535 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.flash_ctrl_ro.97148535
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.2354063592
Short name T443
Test name
Test status
Simulation time 27801303000 ps
CPU time 603.27 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:48:37 PM PDT 24
Peak memory 314756 kb
Host smart-8ffe583c-9d3d-4c53-a180-d6d022f7b067
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354063592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.2354063592
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.456408881
Short name T622
Test name
Test status
Simulation time 43303500 ps
CPU time 31.66 seconds
Started Aug 07 07:38:35 PM PDT 24
Finished Aug 07 07:39:06 PM PDT 24
Peak memory 275908 kb
Host smart-0eaba937-44aa-46c0-bd19-bc2b6a0e30c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456408881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_rw_evict.456408881
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3550909984
Short name T482
Test name
Test status
Simulation time 93169800 ps
CPU time 29.03 seconds
Started Aug 07 07:38:32 PM PDT 24
Finished Aug 07 07:39:01 PM PDT 24
Peak memory 275912 kb
Host smart-86b6e016-e73d-4416-86bd-5150f835e027
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550909984 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.3550909984
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1265244878
Short name T457
Test name
Test status
Simulation time 55898500 ps
CPU time 122.9 seconds
Started Aug 07 07:38:24 PM PDT 24
Finished Aug 07 07:40:27 PM PDT 24
Peak memory 276832 kb
Host smart-b3ea6ad2-7b7e-462c-a074-981d1da3dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265244878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1265244878
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.4107824676
Short name T988
Test name
Test status
Simulation time 2664805400 ps
CPU time 148.36 seconds
Started Aug 07 07:38:34 PM PDT 24
Finished Aug 07 07:41:03 PM PDT 24
Peak memory 265508 kb
Host smart-4ca97f14-af6c-416a-95a7-5bc8264c24fa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107824676 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.4107824676
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.4063262986
Short name T935
Test name
Test status
Simulation time 28298800 ps
CPU time 13.89 seconds
Started Aug 07 07:39:06 PM PDT 24
Finished Aug 07 07:39:20 PM PDT 24
Peak memory 258260 kb
Host smart-1cdd62d3-48b6-409a-be19-77d32a7fc2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063262986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
4063262986
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.1359534776
Short name T1067
Test name
Test status
Simulation time 38752500 ps
CPU time 15.83 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:39:03 PM PDT 24
Peak memory 284660 kb
Host smart-a5b9af4b-d681-4e95-97a8-90a38bddccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359534776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1359534776
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3406858573
Short name T785
Test name
Test status
Simulation time 10019400400 ps
CPU time 65.12 seconds
Started Aug 07 07:39:09 PM PDT 24
Finished Aug 07 07:40:14 PM PDT 24
Peak memory 282540 kb
Host smart-27ca20f0-8a67-4700-b942-da51a3597cda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406858573 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3406858573
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.344464636
Short name T775
Test name
Test status
Simulation time 25058300 ps
CPU time 13.64 seconds
Started Aug 07 07:39:07 PM PDT 24
Finished Aug 07 07:39:21 PM PDT 24
Peak memory 265032 kb
Host smart-7838c5d8-6cb8-4461-a0fc-16af884967a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344464636 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.344464636
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1130641725
Short name T114
Test name
Test status
Simulation time 80152798000 ps
CPU time 857.12 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:53:05 PM PDT 24
Peak memory 264640 kb
Host smart-ff9b2c67-c385-4081-a940-dab88997c87e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130641725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1130641725
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2798647625
Short name T985
Test name
Test status
Simulation time 7252031600 ps
CPU time 115.97 seconds
Started Aug 07 07:38:49 PM PDT 24
Finished Aug 07 07:40:45 PM PDT 24
Peak memory 260752 kb
Host smart-13f4805a-5671-4fb2-82a3-a4806f7e003d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798647625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2798647625
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.2979441259
Short name T304
Test name
Test status
Simulation time 1790864900 ps
CPU time 224.33 seconds
Started Aug 07 07:38:50 PM PDT 24
Finished Aug 07 07:42:34 PM PDT 24
Peak memory 291808 kb
Host smart-e7e83088-dca7-462c-b8ad-cf17c1fbc5b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979441259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.2979441259
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1782354877
Short name T88
Test name
Test status
Simulation time 12300384600 ps
CPU time 272.97 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:43:20 PM PDT 24
Peak memory 293504 kb
Host smart-a7448350-014a-426e-b79c-8dd8e8d5faee
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782354877 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.1782354877
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3032954417
Short name T400
Test name
Test status
Simulation time 2523954400 ps
CPU time 67.58 seconds
Started Aug 07 07:38:49 PM PDT 24
Finished Aug 07 07:39:57 PM PDT 24
Peak memory 260908 kb
Host smart-a0ae8a56-7f88-43c4-8fe0-682e538b0ec7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032954417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
032954417
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1365201665
Short name T995
Test name
Test status
Simulation time 8796390300 ps
CPU time 743.79 seconds
Started Aug 07 07:38:49 PM PDT 24
Finished Aug 07 07:51:13 PM PDT 24
Peak memory 274616 kb
Host smart-b2f531ff-2054-4eb3-964a-9e5fbb134ffd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365201665 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1365201665
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.3147907327
Short name T880
Test name
Test status
Simulation time 1676714600 ps
CPU time 346.35 seconds
Started Aug 07 07:38:51 PM PDT 24
Finished Aug 07 07:44:37 PM PDT 24
Peak memory 263552 kb
Host smart-b32e7148-3728-4bde-96c5-f2b9aa888cbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147907327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3147907327
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3615856818
Short name T435
Test name
Test status
Simulation time 83730600 ps
CPU time 13.47 seconds
Started Aug 07 07:38:48 PM PDT 24
Finished Aug 07 07:39:01 PM PDT 24
Peak memory 259180 kb
Host smart-6d3747c4-10e7-478a-8120-4c3443f0261a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615856818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.flash_ctrl_prog_reset.3615856818
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2260351434
Short name T571
Test name
Test status
Simulation time 24609000 ps
CPU time 98.97 seconds
Started Aug 07 07:38:48 PM PDT 24
Finished Aug 07 07:40:27 PM PDT 24
Peak memory 276072 kb
Host smart-97acc1fc-a495-46fa-81ba-47562a849fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260351434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2260351434
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.622691443
Short name T336
Test name
Test status
Simulation time 230913300 ps
CPU time 34.79 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:39:22 PM PDT 24
Peak memory 275256 kb
Host smart-204580c0-95a3-46cd-a0c4-e0c0c062d62f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622691443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.622691443
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1612059264
Short name T64
Test name
Test status
Simulation time 564347900 ps
CPU time 150.89 seconds
Started Aug 07 07:38:49 PM PDT 24
Finished Aug 07 07:41:20 PM PDT 24
Peak memory 282048 kb
Host smart-36e62218-5d30-4c8c-84e2-fd4657e8cdf6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612059264 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.1612059264
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.2409878341
Short name T812
Test name
Test status
Simulation time 32291800 ps
CPU time 31.38 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:39:19 PM PDT 24
Peak memory 273896 kb
Host smart-8899f8fd-2346-459d-a950-ff3fd0510021
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409878341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.2409878341
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3641444291
Short name T347
Test name
Test status
Simulation time 33840000 ps
CPU time 31.86 seconds
Started Aug 07 07:38:47 PM PDT 24
Finished Aug 07 07:39:19 PM PDT 24
Peak memory 267720 kb
Host smart-bd9cbe3d-8380-45b6-a446-db8c6ba90723
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641444291 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3641444291
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3899071778
Short name T793
Test name
Test status
Simulation time 327100100 ps
CPU time 55.45 seconds
Started Aug 07 07:38:50 PM PDT 24
Finished Aug 07 07:39:46 PM PDT 24
Peak memory 265476 kb
Host smart-3037335b-71df-45be-b7e4-a004af7d7d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899071778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3899071778
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1144503539
Short name T924
Test name
Test status
Simulation time 62165200 ps
CPU time 122.36 seconds
Started Aug 07 07:38:50 PM PDT 24
Finished Aug 07 07:40:53 PM PDT 24
Peak memory 277608 kb
Host smart-3c64d7d5-2e3b-4cbf-a77d-d7c002700859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144503539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1144503539
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.3203907707
Short name T873
Test name
Test status
Simulation time 7756249700 ps
CPU time 200 seconds
Started Aug 07 07:38:50 PM PDT 24
Finished Aug 07 07:42:10 PM PDT 24
Peak memory 265508 kb
Host smart-d0859e0a-e5f5-4dce-b7ee-aa6c2dce63f2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203907707 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.3203907707
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.1216619927
Short name T865
Test name
Test status
Simulation time 73806300 ps
CPU time 13.8 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:39:37 PM PDT 24
Peak memory 258444 kb
Host smart-1c5f901f-a487-4d32-a736-6ef8e421f27d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216619927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
1216619927
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1843948854
Short name T460
Test name
Test status
Simulation time 24478600 ps
CPU time 15.91 seconds
Started Aug 07 07:39:26 PM PDT 24
Finished Aug 07 07:39:42 PM PDT 24
Peak memory 283384 kb
Host smart-3f07e374-44ac-475d-a8a4-215f346481ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843948854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1843948854
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.3158696086
Short name T99
Test name
Test status
Simulation time 25888200 ps
CPU time 21 seconds
Started Aug 07 07:39:26 PM PDT 24
Finished Aug 07 07:39:47 PM PDT 24
Peak memory 273804 kb
Host smart-cc387fc4-27e9-4567-b546-e51a088ed2a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158696086 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.3158696086
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1809974123
Short name T194
Test name
Test status
Simulation time 10059011400 ps
CPU time 41.51 seconds
Started Aug 07 07:39:26 PM PDT 24
Finished Aug 07 07:40:07 PM PDT 24
Peak memory 271356 kb
Host smart-926d01e6-ad3a-4c44-b8d7-2573f2822835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809974123 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1809974123
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3329691763
Short name T1013
Test name
Test status
Simulation time 26379600 ps
CPU time 13.54 seconds
Started Aug 07 07:39:25 PM PDT 24
Finished Aug 07 07:39:38 PM PDT 24
Peak memory 260308 kb
Host smart-b60b733a-1a16-4770-907b-a8c74097f194
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329691763 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3329691763
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.1673328378
Short name T188
Test name
Test status
Simulation time 80145879700 ps
CPU time 895.17 seconds
Started Aug 07 07:39:07 PM PDT 24
Finished Aug 07 07:54:02 PM PDT 24
Peak memory 262388 kb
Host smart-d5359023-7f01-453f-aef7-6191a2cc8ef3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673328378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.1673328378
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3882863160
Short name T307
Test name
Test status
Simulation time 5032842800 ps
CPU time 149.95 seconds
Started Aug 07 07:39:06 PM PDT 24
Finished Aug 07 07:41:36 PM PDT 24
Peak memory 263376 kb
Host smart-54ec7aa4-b507-4442-a20a-eb7919f91063
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882863160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.3882863160
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2080755027
Short name T813
Test name
Test status
Simulation time 2948814100 ps
CPU time 165.17 seconds
Started Aug 07 07:39:29 PM PDT 24
Finished Aug 07 07:42:14 PM PDT 24
Peak memory 295692 kb
Host smart-b1db8e4a-6974-40ad-9613-1967f6d549a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080755027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2080755027
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2357106800
Short name T155
Test name
Test status
Simulation time 5866366800 ps
CPU time 130.77 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:41:33 PM PDT 24
Peak memory 293140 kb
Host smart-bf23800f-5e02-4980-821f-1c27e3f6c5a0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357106800 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2357106800
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.679413914
Short name T919
Test name
Test status
Simulation time 1675530600 ps
CPU time 72.14 seconds
Started Aug 07 07:39:08 PM PDT 24
Finished Aug 07 07:40:21 PM PDT 24
Peak memory 263388 kb
Host smart-7d3b7ba3-ea2c-49d3-8712-9de1e7dc9e23
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679413914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.679413914
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1685276848
Short name T288
Test name
Test status
Simulation time 46409900 ps
CPU time 14.36 seconds
Started Aug 07 07:39:25 PM PDT 24
Finished Aug 07 07:39:39 PM PDT 24
Peak memory 261284 kb
Host smart-55efb1a5-fdc7-4596-8df0-52abf0ca205f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685276848 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1685276848
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.4164141974
Short name T860
Test name
Test status
Simulation time 3783116300 ps
CPU time 183.15 seconds
Started Aug 07 07:39:06 PM PDT 24
Finished Aug 07 07:42:10 PM PDT 24
Peak memory 264084 kb
Host smart-df468f38-4cce-4a47-903c-a46a3dd7d6ce
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164141974 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.4164141974
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.183208053
Short name T1068
Test name
Test status
Simulation time 599709200 ps
CPU time 110.72 seconds
Started Aug 07 07:39:06 PM PDT 24
Finished Aug 07 07:40:57 PM PDT 24
Peak memory 264680 kb
Host smart-64773e59-7cda-43e0-8993-98e5a918f780
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183208053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot
p_reset.183208053
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1805945285
Short name T405
Test name
Test status
Simulation time 142859900 ps
CPU time 408.27 seconds
Started Aug 07 07:39:07 PM PDT 24
Finished Aug 07 07:45:56 PM PDT 24
Peak memory 263528 kb
Host smart-351f0897-e99e-46b3-997e-4857a6234fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805945285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1805945285
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.3322908631
Short name T440
Test name
Test status
Simulation time 2387604900 ps
CPU time 205.17 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:42:50 PM PDT 24
Peak memory 260800 kb
Host smart-55e23b74-4b7d-4b63-93dc-f3d7dd3b36f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322908631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.flash_ctrl_prog_reset.3322908631
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.165479184
Short name T591
Test name
Test status
Simulation time 1833061200 ps
CPU time 1222.32 seconds
Started Aug 07 07:39:09 PM PDT 24
Finished Aug 07 07:59:31 PM PDT 24
Peak memory 286936 kb
Host smart-ed5374fe-32eb-45de-97e1-c89f5d2b53f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165479184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.165479184
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.898631135
Short name T603
Test name
Test status
Simulation time 66578900 ps
CPU time 35.71 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:40:00 PM PDT 24
Peak memory 278736 kb
Host smart-91fc15a8-6f46-4cdd-b6fa-c2036771ab23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898631135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_re_evict.898631135
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.2564945387
Short name T994
Test name
Test status
Simulation time 513295800 ps
CPU time 136.69 seconds
Started Aug 07 07:39:27 PM PDT 24
Finished Aug 07 07:41:44 PM PDT 24
Peak memory 291788 kb
Host smart-ef98f33c-6893-4359-875e-0248c4e3b938
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564945387 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.2564945387
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.2360869710
Short name T134
Test name
Test status
Simulation time 14238476300 ps
CPU time 513.97 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:47:57 PM PDT 24
Peak memory 310260 kb
Host smart-6bb85971-d1cb-4a96-9492-110920bafa5a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360869710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.2360869710
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.1887234990
Short name T349
Test name
Test status
Simulation time 51981300 ps
CPU time 31.51 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:39:54 PM PDT 24
Peak memory 273896 kb
Host smart-b3951d15-c53b-43dd-acce-b34bf90f7d1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887234990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.1887234990
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1286404616
Short name T853
Test name
Test status
Simulation time 1777817800 ps
CPU time 76.21 seconds
Started Aug 07 07:39:29 PM PDT 24
Finished Aug 07 07:40:45 PM PDT 24
Peak memory 263908 kb
Host smart-b762d8d9-810f-4405-bd7b-e802780cfd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286404616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1286404616
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.2208247034
Short name T1087
Test name
Test status
Simulation time 29808500 ps
CPU time 173.21 seconds
Started Aug 07 07:39:06 PM PDT 24
Finished Aug 07 07:41:59 PM PDT 24
Peak memory 279492 kb
Host smart-25479df7-6fb2-43d8-bba5-bae16d2c1fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208247034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2208247034
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.792983634
Short name T489
Test name
Test status
Simulation time 3408414400 ps
CPU time 161.68 seconds
Started Aug 07 07:39:07 PM PDT 24
Finished Aug 07 07:41:49 PM PDT 24
Peak memory 265556 kb
Host smart-90499f16-40c7-4d49-a665-f1eb5302b5d1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792983634 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.flash_ctrl_wo.792983634
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3252187426
Short name T909
Test name
Test status
Simulation time 60398800 ps
CPU time 13.62 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:39:49 PM PDT 24
Peak memory 258392 kb
Host smart-b2a77bf9-ac90-4a4b-90fc-a8acd099d0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252187426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3252187426
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2695980516
Short name T437
Test name
Test status
Simulation time 30346600 ps
CPU time 16.24 seconds
Started Aug 07 07:39:34 PM PDT 24
Finished Aug 07 07:39:51 PM PDT 24
Peak memory 275260 kb
Host smart-6413f93c-f266-46f4-9d22-da21d7f0a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695980516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2695980516
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.3915704507
Short name T372
Test name
Test status
Simulation time 11215000 ps
CPU time 21.03 seconds
Started Aug 07 07:39:26 PM PDT 24
Finished Aug 07 07:39:47 PM PDT 24
Peak memory 273804 kb
Host smart-ed5b881c-55ab-4414-8190-f5a1c23f61ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915704507 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.3915704507
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3493007797
Short name T1030
Test name
Test status
Simulation time 10124496200 ps
CPU time 39.43 seconds
Started Aug 07 07:39:37 PM PDT 24
Finished Aug 07 07:40:16 PM PDT 24
Peak memory 265512 kb
Host smart-b1e06d67-c535-4661-a574-3d0858c6544e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493007797 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3493007797
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2203654093
Short name T1044
Test name
Test status
Simulation time 15922500 ps
CPU time 13.65 seconds
Started Aug 07 07:39:37 PM PDT 24
Finished Aug 07 07:39:51 PM PDT 24
Peak memory 258656 kb
Host smart-c6bbde3c-b87f-4c04-b236-7e1e0a7c0daf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203654093 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.2203654093
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3695937100
Short name T189
Test name
Test status
Simulation time 40126557200 ps
CPU time 921.78 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:54:45 PM PDT 24
Peak memory 264440 kb
Host smart-27658450-3a1f-4b51-9bf1-009d60d6a211
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695937100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.3695937100
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2015638130
Short name T594
Test name
Test status
Simulation time 15654711500 ps
CPU time 235.09 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:43:18 PM PDT 24
Peak memory 261160 kb
Host smart-9b0adb19-e610-4477-932e-fddac28cb709
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015638130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2015638130
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.1960353946
Short name T327
Test name
Test status
Simulation time 11079011000 ps
CPU time 158.56 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:42:03 PM PDT 24
Peak memory 294388 kb
Host smart-a9150eb7-f7e3-4495-887d-1d1c75d2e484
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960353946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.1960353946
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.4261110233
Short name T492
Test name
Test status
Simulation time 25721543000 ps
CPU time 159.33 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:42:04 PM PDT 24
Peak memory 293180 kb
Host smart-fbfdf16d-a55d-4622-98cb-5fe4e286c883
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261110233 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.4261110233
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3006323269
Short name T612
Test name
Test status
Simulation time 15143400 ps
CPU time 13.66 seconds
Started Aug 07 07:39:34 PM PDT 24
Finished Aug 07 07:39:48 PM PDT 24
Peak memory 265028 kb
Host smart-e2df65b7-547e-47d8-8872-417df717816a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006323269 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3006323269
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.2623804807
Short name T147
Test name
Test status
Simulation time 21653992600 ps
CPU time 371.84 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:45:36 PM PDT 24
Peak memory 275784 kb
Host smart-9d7b756d-d9c8-4d54-ae27-dc0f4840bb71
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623804807 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.2623804807
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.3845461852
Short name T720
Test name
Test status
Simulation time 72978700 ps
CPU time 133.26 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:41:37 PM PDT 24
Peak memory 260480 kb
Host smart-c1c5e858-13c7-43a2-a293-7cff6b533e82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845461852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.3845461852
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.763636885
Short name T743
Test name
Test status
Simulation time 13746953100 ps
CPU time 256.18 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:43:40 PM PDT 24
Peak memory 263444 kb
Host smart-33773610-b56b-4fb2-a78b-efead3f220a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763636885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.763636885
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.2885502599
Short name T712
Test name
Test status
Simulation time 8850514000 ps
CPU time 186.1 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:42:29 PM PDT 24
Peak memory 265312 kb
Host smart-f6fe1f30-350b-4bb9-9a73-833c968101a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885502599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.flash_ctrl_prog_reset.2885502599
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1527513262
Short name T125
Test name
Test status
Simulation time 3140501300 ps
CPU time 970.09 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:55:34 PM PDT 24
Peak memory 284252 kb
Host smart-7ea15dfc-60b8-421b-a2ec-e8e681ceb93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527513262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1527513262
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.993490746
Short name T140
Test name
Test status
Simulation time 94721200 ps
CPU time 36.42 seconds
Started Aug 07 07:39:22 PM PDT 24
Finished Aug 07 07:39:59 PM PDT 24
Peak memory 277980 kb
Host smart-0572bcda-6257-4aca-8f34-493dd160cc11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993490746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.993490746
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.3627000855
Short name T718
Test name
Test status
Simulation time 2554938000 ps
CPU time 134.39 seconds
Started Aug 07 07:39:26 PM PDT 24
Finished Aug 07 07:41:40 PM PDT 24
Peak memory 282028 kb
Host smart-28043098-fd4e-412f-a92c-3f69c0127d28
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627000855 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.3627000855
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2376929564
Short name T123
Test name
Test status
Simulation time 15320672300 ps
CPU time 594.29 seconds
Started Aug 07 07:39:24 PM PDT 24
Finished Aug 07 07:49:18 PM PDT 24
Peak memory 314856 kb
Host smart-ece35a82-7d79-487e-911b-25fe4e7e8884
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376929564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.2376929564
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.72865784
Short name T282
Test name
Test status
Simulation time 50735600 ps
CPU time 31.73 seconds
Started Aug 07 07:39:27 PM PDT 24
Finished Aug 07 07:39:59 PM PDT 24
Peak memory 275924 kb
Host smart-0e3fd3e1-34e9-477b-ac57-70fd1c5c3195
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72865784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flas
h_ctrl_rw_evict.72865784
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.1788848462
Short name T340
Test name
Test status
Simulation time 94694800 ps
CPU time 31.55 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:39:55 PM PDT 24
Peak memory 273856 kb
Host smart-fa8d9cf5-9211-4344-989c-d580b60aed51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788848462 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.1788848462
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.2008413554
Short name T806
Test name
Test status
Simulation time 38135200 ps
CPU time 146.59 seconds
Started Aug 07 07:39:23 PM PDT 24
Finished Aug 07 07:41:49 PM PDT 24
Peak memory 277044 kb
Host smart-700de76e-93ac-43b9-bfdb-f91c483f8157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008413554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2008413554
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1627441577
Short name T704
Test name
Test status
Simulation time 7278948600 ps
CPU time 126.64 seconds
Started Aug 07 07:39:25 PM PDT 24
Finished Aug 07 07:41:32 PM PDT 24
Peak memory 260148 kb
Host smart-982ad68a-a663-4ed4-8fd5-5ec3a6e460d7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627441577 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1627441577
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.3350725086
Short name T990
Test name
Test status
Simulation time 101171600 ps
CPU time 13.82 seconds
Started Aug 07 07:39:52 PM PDT 24
Finished Aug 07 07:40:06 PM PDT 24
Peak memory 258456 kb
Host smart-87d2ed72-bfe8-4ad7-942a-33eeb155ca88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350725086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
3350725086
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.605540146
Short name T118
Test name
Test status
Simulation time 14160000 ps
CPU time 13.47 seconds
Started Aug 07 07:39:52 PM PDT 24
Finished Aug 07 07:40:05 PM PDT 24
Peak memory 283476 kb
Host smart-f3617faa-f7fd-4acf-b7b1-8eb15b751524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605540146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.605540146
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.144201692
Short name T522
Test name
Test status
Simulation time 22000200 ps
CPU time 22.46 seconds
Started Aug 07 07:39:52 PM PDT 24
Finished Aug 07 07:40:14 PM PDT 24
Peak memory 273720 kb
Host smart-5c88a1a5-142a-46e1-8924-a452a7a4be84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144201692 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.144201692
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3182627057
Short name T833
Test name
Test status
Simulation time 10012332600 ps
CPU time 118.87 seconds
Started Aug 07 07:39:46 PM PDT 24
Finished Aug 07 07:41:45 PM PDT 24
Peak memory 342484 kb
Host smart-c3d959b5-c450-48ef-bcae-f04969595f7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182627057 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3182627057
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2564427311
Short name T1045
Test name
Test status
Simulation time 72697700 ps
CPU time 13.57 seconds
Started Aug 07 07:39:46 PM PDT 24
Finished Aug 07 07:40:00 PM PDT 24
Peak memory 260220 kb
Host smart-53c6802b-5272-4815-bed8-03d39dc6a23f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564427311 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2564427311
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.782136573
Short name T773
Test name
Test status
Simulation time 40128689500 ps
CPU time 939.79 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:55:15 PM PDT 24
Peak memory 264080 kb
Host smart-b60d278d-ead5-4920-b3f7-99674202cbb7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782136573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.flash_ctrl_hw_rma_reset.782136573
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2079384445
Short name T302
Test name
Test status
Simulation time 82447025000 ps
CPU time 201.51 seconds
Started Aug 07 07:39:38 PM PDT 24
Finished Aug 07 07:43:00 PM PDT 24
Peak memory 263024 kb
Host smart-ea1dde35-137e-4c81-b41e-6d2da3c30dca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079384445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.2079384445
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.2116689179
Short name T328
Test name
Test status
Simulation time 1274958700 ps
CPU time 136.72 seconds
Started Aug 07 07:39:36 PM PDT 24
Finished Aug 07 07:41:53 PM PDT 24
Peak memory 291240 kb
Host smart-058605e5-b441-4c60-ac7e-e2447abb9c3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116689179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.2116689179
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2483879443
Short name T553
Test name
Test status
Simulation time 35936601000 ps
CPU time 362.5 seconds
Started Aug 07 07:39:36 PM PDT 24
Finished Aug 07 07:45:39 PM PDT 24
Peak memory 291332 kb
Host smart-cb8ac2b9-10f2-4a34-b8b1-60d66a8b6278
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483879443 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.2483879443
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2098276114
Short name T494
Test name
Test status
Simulation time 2604479600 ps
CPU time 90.7 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:41:06 PM PDT 24
Peak memory 260832 kb
Host smart-a6fc5979-cdcf-47ef-a8a7-919909afd684
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098276114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
098276114
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2318226010
Short name T1111
Test name
Test status
Simulation time 48382900 ps
CPU time 13.77 seconds
Started Aug 07 07:39:48 PM PDT 24
Finished Aug 07 07:40:02 PM PDT 24
Peak memory 260428 kb
Host smart-3d0fff6e-fdfe-485e-a83c-08635629ac22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318226010 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2318226010
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.2558911629
Short name T941
Test name
Test status
Simulation time 37814700 ps
CPU time 133.35 seconds
Started Aug 07 07:39:38 PM PDT 24
Finished Aug 07 07:41:51 PM PDT 24
Peak memory 260556 kb
Host smart-18eb9c59-668d-457c-ab45-7808f728b50c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558911629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.2558911629
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1153927346
Short name T791
Test name
Test status
Simulation time 386859900 ps
CPU time 345.4 seconds
Started Aug 07 07:39:34 PM PDT 24
Finished Aug 07 07:45:20 PM PDT 24
Peak memory 263288 kb
Host smart-dd2f92fa-c987-4d97-8cdc-e948d5176bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153927346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1153927346
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.1035088032
Short name T923
Test name
Test status
Simulation time 61040800 ps
CPU time 13.55 seconds
Started Aug 07 07:39:45 PM PDT 24
Finished Aug 07 07:39:59 PM PDT 24
Peak memory 259156 kb
Host smart-9200557c-2507-430a-a5e4-6da92001a948
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035088032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.flash_ctrl_prog_reset.1035088032
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1973074253
Short name T150
Test name
Test status
Simulation time 957952200 ps
CPU time 1160.52 seconds
Started Aug 07 07:39:36 PM PDT 24
Finished Aug 07 07:58:57 PM PDT 24
Peak memory 286680 kb
Host smart-37957c90-13d0-4013-9160-00bce8076d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973074253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1973074253
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2806465322
Short name T217
Test name
Test status
Simulation time 202599600 ps
CPU time 34.52 seconds
Started Aug 07 07:39:49 PM PDT 24
Finished Aug 07 07:40:24 PM PDT 24
Peak memory 273900 kb
Host smart-28d2f9b1-2f45-47e2-b37f-86c9042e1fad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806465322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2806465322
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2980298481
Short name T838
Test name
Test status
Simulation time 8334045500 ps
CPU time 141.08 seconds
Started Aug 07 07:39:36 PM PDT 24
Finished Aug 07 07:41:57 PM PDT 24
Peak memory 290184 kb
Host smart-8951de56-66dc-42b4-a683-f7698098f826
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980298481 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.2980298481
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.2259676044
Short name T543
Test name
Test status
Simulation time 11152812900 ps
CPU time 669.14 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:50:44 PM PDT 24
Peak memory 310300 kb
Host smart-b5bc29ca-8963-43c5-bd12-95e4e96e069e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259676044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.2259676044
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1187431841
Short name T1039
Test name
Test status
Simulation time 27960100 ps
CPU time 31.12 seconds
Started Aug 07 07:39:48 PM PDT 24
Finished Aug 07 07:40:19 PM PDT 24
Peak memory 275936 kb
Host smart-70e61fcb-f327-4b77-b372-fe7c359ee3d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187431841 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1187431841
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3977620147
Short name T445
Test name
Test status
Simulation time 218377500 ps
CPU time 172.95 seconds
Started Aug 07 07:39:35 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 277196 kb
Host smart-c87de20c-7259-4a1d-abdf-da6a79eb1a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977620147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3977620147
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.4091432997
Short name T121
Test name
Test status
Simulation time 6231809300 ps
CPU time 273.18 seconds
Started Aug 07 07:39:36 PM PDT 24
Finished Aug 07 07:44:10 PM PDT 24
Peak memory 265508 kb
Host smart-c2cfc993-2cab-4498-a3a8-7a97e73980d3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091432997 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.4091432997
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.136237889
Short name T51
Test name
Test status
Simulation time 13424300 ps
CPU time 13.94 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:33:17 PM PDT 24
Peak memory 261680 kb
Host smart-65970a29-6236-4c2c-bc5d-37423c06a42f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136237889 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.136237889
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.3302418058
Short name T1007
Test name
Test status
Simulation time 20887600 ps
CPU time 13.43 seconds
Started Aug 07 07:33:05 PM PDT 24
Finished Aug 07 07:33:18 PM PDT 24
Peak memory 258396 kb
Host smart-8af005c0-a3ff-47c3-bec5-8f430a617b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302418058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3
302418058
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.2570058068
Short name T253
Test name
Test status
Simulation time 69438300 ps
CPU time 13.98 seconds
Started Aug 07 07:33:02 PM PDT 24
Finished Aug 07 07:33:17 PM PDT 24
Peak memory 265032 kb
Host smart-e8d7c916-5a95-4373-97d7-cc7c5151592a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570058068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.2570058068
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3934399779
Short name T840
Test name
Test status
Simulation time 15578400 ps
CPU time 15.84 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:33:20 PM PDT 24
Peak memory 283512 kb
Host smart-094e5eac-f60c-40e6-993b-d378c8fc8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934399779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3934399779
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.972028212
Short name T757
Test name
Test status
Simulation time 1558763400 ps
CPU time 194.97 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:36:18 PM PDT 24
Peak memory 278252 kb
Host smart-b2cc2bca-b9ab-47b0-a0c7-cfcdea733b8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972028212 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.972028212
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.1513333375
Short name T48
Test name
Test status
Simulation time 46220400 ps
CPU time 21.97 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:33:27 PM PDT 24
Peak memory 266764 kb
Host smart-99d18b0d-4529-47a2-8191-0848305bec3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513333375 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.1513333375
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1151813833
Short name T947
Test name
Test status
Simulation time 2581719200 ps
CPU time 422.86 seconds
Started Aug 07 07:32:52 PM PDT 24
Finished Aug 07 07:39:55 PM PDT 24
Peak memory 263544 kb
Host smart-fbd1a1bc-7562-4eb0-9b9d-0df2f093fe88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151813833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1151813833
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1888022453
Short name T226
Test name
Test status
Simulation time 3658583200 ps
CPU time 2486.06 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 08:14:20 PM PDT 24
Peak memory 263020 kb
Host smart-90204527-486a-4803-b84c-8fcf5354200f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1888022453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1888022453
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.3193723263
Short name T87
Test name
Test status
Simulation time 2899730000 ps
CPU time 1901.82 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 08:04:36 PM PDT 24
Peak memory 265488 kb
Host smart-e1627ce3-047f-4354-bbab-b2e2450ceb82
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193723263 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3193723263
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.1358343978
Short name T818
Test name
Test status
Simulation time 989014900 ps
CPU time 26.58 seconds
Started Aug 07 07:32:56 PM PDT 24
Finished Aug 07 07:33:23 PM PDT 24
Peak memory 262848 kb
Host smart-e06eb306-b61e-4096-98eb-081caf671723
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358343978 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_fetch_code.1358343978
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.959945500
Short name T216
Test name
Test status
Simulation time 195646153300 ps
CPU time 4389.35 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 08:46:04 PM PDT 24
Peak memory 265324 kb
Host smart-d63f02e0-1ad3-4e38-8222-cf5ed4e62473
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959945500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_full_mem_access.959945500
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_addr_infection.858920314
Short name T706
Test name
Test status
Simulation time 29244200 ps
CPU time 30.6 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:33:35 PM PDT 24
Peak memory 273644 kb
Host smart-6842d6af-4783-42fc-ac72-8985756061f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858920314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_host_addr_infection.858920314
Directory /workspace/2.flash_ctrl_host_addr_infection/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3095237417
Short name T206
Test name
Test status
Simulation time 273360904000 ps
CPU time 3146.38 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 08:25:21 PM PDT 24
Peak memory 264400 kb
Host smart-3ac89e14-e9ff-4508-b316-9c793033e1ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095237417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3095237417
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.867355630
Short name T485
Test name
Test status
Simulation time 80671900 ps
CPU time 26.71 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:33:20 PM PDT 24
Peak memory 262976 kb
Host smart-66388f30-4b8d-4b59-896c-ce87c0413c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867355630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.867355630
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.37066759
Short name T285
Test name
Test status
Simulation time 10034582300 ps
CPU time 47.15 seconds
Started Aug 07 07:33:06 PM PDT 24
Finished Aug 07 07:33:53 PM PDT 24
Peak memory 265536 kb
Host smart-f88c891a-d72a-4f38-9be0-f0f38a32ed37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37066759 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.37066759
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1170541888
Short name T874
Test name
Test status
Simulation time 49587800 ps
CPU time 14.08 seconds
Started Aug 07 07:33:02 PM PDT 24
Finished Aug 07 07:33:16 PM PDT 24
Peak memory 260208 kb
Host smart-722722bb-1019-4a12-9c4d-0764163a4a41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170541888 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1170541888
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3761082599
Short name T1035
Test name
Test status
Simulation time 1014600505000 ps
CPU time 2847.65 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 08:20:22 PM PDT 24
Peak memory 265240 kb
Host smart-97f6fe58-f81c-45f5-92fa-a0bdf50fc111
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761082599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3761082599
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3126742916
Short name T823
Test name
Test status
Simulation time 80146624700 ps
CPU time 861.13 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:47:15 PM PDT 24
Peak memory 261036 kb
Host smart-74437056-97fc-4bd6-ac4b-b17ea2ec7a9a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126742916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.3126742916
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.3918129329
Short name T52
Test name
Test status
Simulation time 2863104100 ps
CPU time 103.4 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 07:34:38 PM PDT 24
Peak memory 263076 kb
Host smart-94121c21-e5b9-4a4a-acd3-ab513852977b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918129329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.3918129329
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.911225286
Short name T980
Test name
Test status
Simulation time 3520360900 ps
CPU time 642.95 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:43:47 PM PDT 24
Peak memory 322500 kb
Host smart-e7bbfde0-9d92-4b5d-9abb-480a88f7ed9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911225286 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_integrity.911225286
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2529994417
Short name T1043
Test name
Test status
Simulation time 41687601600 ps
CPU time 177.12 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:36:01 PM PDT 24
Peak memory 294504 kb
Host smart-550d92f6-2a05-48ba-b78b-2401896c1051
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529994417 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.2529994417
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.49901599
Short name T604
Test name
Test status
Simulation time 4302121100 ps
CPU time 64.41 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:34:07 PM PDT 24
Peak memory 260848 kb
Host smart-c0055b8d-cffd-4160-9f39-86d7bfebaac6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49901599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_intr_wr.49901599
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3346139839
Short name T850
Test name
Test status
Simulation time 47508004200 ps
CPU time 226.01 seconds
Started Aug 07 07:33:02 PM PDT 24
Finished Aug 07 07:36:48 PM PDT 24
Peak memory 260556 kb
Host smart-86609a42-1061-4887-b441-0c07ee1d11d2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334
6139839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3346139839
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.293324028
Short name T403
Test name
Test status
Simulation time 4200415500 ps
CPU time 85.29 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 07:34:20 PM PDT 24
Peak memory 260940 kb
Host smart-85a90bbb-09cb-48a9-b69b-3f8ac324549f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293324028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.293324028
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.945960232
Short name T821
Test name
Test status
Simulation time 52921400 ps
CPU time 13.71 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:33:18 PM PDT 24
Peak memory 260332 kb
Host smart-af1cfee0-2576-478a-ba51-27b5bc0c3dae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945960232 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.945960232
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.4276336825
Short name T975
Test name
Test status
Simulation time 17932625700 ps
CPU time 85.85 seconds
Started Aug 07 07:32:56 PM PDT 24
Finished Aug 07 07:34:23 PM PDT 24
Peak memory 260820 kb
Host smart-57d6cbaf-ca9e-4742-9f06-9b5889f8a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276336825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.4276336825
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.1074423808
Short name T819
Test name
Test status
Simulation time 16467680900 ps
CPU time 165.51 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 07:35:40 PM PDT 24
Peak memory 263676 kb
Host smart-3b978528-cb52-4913-8158-03cdc313c77c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074423808 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.1074423808
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.643045877
Short name T1086
Test name
Test status
Simulation time 201428900 ps
CPU time 112.2 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 07:34:47 PM PDT 24
Peak memory 261180 kb
Host smart-6d864690-1d71-447c-8eaa-a3ebef9cbb14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643045877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp
_reset.643045877
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.1145741176
Short name T888
Test name
Test status
Simulation time 1014553300 ps
CPU time 204.37 seconds
Started Aug 07 07:33:06 PM PDT 24
Finished Aug 07 07:36:30 PM PDT 24
Peak memory 295688 kb
Host smart-59cdb045-5578-4a06-a110-5e999f17c299
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145741176 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.1145741176
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.4181069973
Short name T526
Test name
Test status
Simulation time 730556300 ps
CPU time 247.9 seconds
Started Aug 07 07:32:52 PM PDT 24
Finished Aug 07 07:37:01 PM PDT 24
Peak memory 263460 kb
Host smart-4c49ce33-84b7-4376-adce-02d7a45bbfc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181069973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4181069973
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2421344575
Short name T689
Test name
Test status
Simulation time 25735300 ps
CPU time 14.08 seconds
Started Aug 07 07:33:06 PM PDT 24
Finished Aug 07 07:33:20 PM PDT 24
Peak memory 265872 kb
Host smart-35e840e3-7174-4a22-b5a2-d4bcf68a502c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421344575 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2421344575
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3246256626
Short name T467
Test name
Test status
Simulation time 3323582000 ps
CPU time 157.18 seconds
Started Aug 07 07:33:06 PM PDT 24
Finished Aug 07 07:35:43 PM PDT 24
Peak memory 260176 kb
Host smart-426361f5-8886-465a-b7cc-1dd21c2b9030
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246256626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.flash_ctrl_prog_reset.3246256626
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.11339145
Short name T1051
Test name
Test status
Simulation time 160284900 ps
CPU time 398.7 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:39:31 PM PDT 24
Peak memory 281704 kb
Host smart-192e303b-8a43-4b5c-ac99-258a12445feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11339145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.11339145
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.960017367
Short name T276
Test name
Test status
Simulation time 2926803800 ps
CPU time 141.3 seconds
Started Aug 07 07:32:55 PM PDT 24
Finished Aug 07 07:35:16 PM PDT 24
Peak memory 263092 kb
Host smart-3f5ba3f7-d3f0-42d1-9cab-768bf601edca
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=960017367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.960017367
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.4030630384
Short name T148
Test name
Test status
Simulation time 119215600 ps
CPU time 32.3 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:33:36 PM PDT 24
Peak memory 273868 kb
Host smart-de31c5c7-7cae-4c84-9352-0215326ad098
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030630384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.4030630384
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.3886033327
Short name T449
Test name
Test status
Simulation time 59178100 ps
CPU time 23.1 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:33:26 PM PDT 24
Peak memory 265276 kb
Host smart-be6cf92d-e7d9-44fc-8c66-e3985c9f4362
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886033327 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.3886033327
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.1848098585
Short name T681
Test name
Test status
Simulation time 25454400 ps
CPU time 22.69 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 07:33:17 PM PDT 24
Peak memory 265104 kb
Host smart-92e7cd3a-c521-4ea5-8044-35d8fa5b8f12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848098585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.1848098585
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.647400351
Short name T185
Test name
Test status
Simulation time 163838230700 ps
CPU time 969.6 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:49:14 PM PDT 24
Peak memory 263788 kb
Host smart-f913736b-bd15-49be-8bbd-6794d2b0772a
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647400351 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.647400351
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.834053594
Short name T488
Test name
Test status
Simulation time 1864951400 ps
CPU time 130.07 seconds
Started Aug 07 07:32:54 PM PDT 24
Finished Aug 07 07:35:04 PM PDT 24
Peak memory 289412 kb
Host smart-a542c2a1-7456-43a4-a923-f02484b7b317
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834053594 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_ro.834053594
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.3501449964
Short name T895
Test name
Test status
Simulation time 2604305100 ps
CPU time 196.71 seconds
Started Aug 07 07:33:02 PM PDT 24
Finished Aug 07 07:36:19 PM PDT 24
Peak memory 282156 kb
Host smart-55fc77b6-402b-4de5-a2c6-f8ca466a34ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3501449964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3501449964
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.249691137
Short name T728
Test name
Test status
Simulation time 3039369700 ps
CPU time 177.21 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:35:51 PM PDT 24
Peak memory 295660 kb
Host smart-8becafec-e1e4-4f1e-a157-350131c22a97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249691137 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.249691137
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.75512232
Short name T154
Test name
Test status
Simulation time 1272870000 ps
CPU time 184.99 seconds
Started Aug 07 07:33:03 PM PDT 24
Finished Aug 07 07:36:08 PM PDT 24
Peak memory 283424 kb
Host smart-fae8467d-f705-48a0-b8f8-906ff3ad4e56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75512232 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_derr.75512232
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.1828547744
Short name T462
Test name
Test status
Simulation time 28958200 ps
CPU time 32.27 seconds
Started Aug 07 07:33:06 PM PDT 24
Finished Aug 07 07:33:39 PM PDT 24
Peak memory 275912 kb
Host smart-121a64a3-4ef0-475c-9d3b-c6bbf7bc9044
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828547744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.1828547744
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2378264748
Short name T616
Test name
Test status
Simulation time 53394000 ps
CPU time 31.61 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:33:35 PM PDT 24
Peak memory 275928 kb
Host smart-859f64ce-6522-44f8-b3b0-31996e1811c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378264748 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2378264748
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.2680434951
Short name T487
Test name
Test status
Simulation time 37753638000 ps
CPU time 286.85 seconds
Started Aug 07 07:33:02 PM PDT 24
Finished Aug 07 07:37:49 PM PDT 24
Peak memory 290904 kb
Host smart-74cb7681-f887-488c-8906-f21885914d8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680434951 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.flash_ctrl_rw_serr.2680434951
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3375231677
Short name T601
Test name
Test status
Simulation time 1459967300 ps
CPU time 76.23 seconds
Started Aug 07 07:33:05 PM PDT 24
Finished Aug 07 07:34:21 PM PDT 24
Peak memory 265672 kb
Host smart-1756fd58-8d55-43fb-bd06-9d141069b922
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375231677 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3375231677
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.4256467036
Short name T1015
Test name
Test status
Simulation time 8272221700 ps
CPU time 109.89 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:34:54 PM PDT 24
Peak memory 274528 kb
Host smart-e06675eb-0081-4530-9165-6bd2a4ac7af0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256467036 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.4256467036
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.1238457333
Short name T548
Test name
Test status
Simulation time 109694000 ps
CPU time 99.45 seconds
Started Aug 07 07:32:48 PM PDT 24
Finished Aug 07 07:34:28 PM PDT 24
Peak memory 276548 kb
Host smart-6d36076c-4adf-40bc-bdc8-11bdfb3bc964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238457333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.1238457333
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1605705221
Short name T518
Test name
Test status
Simulation time 58957300 ps
CPU time 26.79 seconds
Started Aug 07 07:32:44 PM PDT 24
Finished Aug 07 07:33:11 PM PDT 24
Peak memory 259952 kb
Host smart-badcb717-0eef-48b6-b695-c5ef6dff00ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605705221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1605705221
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.3239771817
Short name T6
Test name
Test status
Simulation time 83186100 ps
CPU time 41.57 seconds
Started Aug 07 07:33:01 PM PDT 24
Finished Aug 07 07:33:43 PM PDT 24
Peak memory 260980 kb
Host smart-4c98ef46-3557-4380-ac54-e86188f50819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239771817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.3239771817
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.2893229045
Short name T19
Test name
Test status
Simulation time 52371100 ps
CPU time 24.1 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:33:18 PM PDT 24
Peak memory 259848 kb
Host smart-2aa9a38a-6b42-48ce-b41e-831466231d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893229045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2893229045
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.635014831
Short name T1107
Test name
Test status
Simulation time 2053852700 ps
CPU time 181.95 seconds
Started Aug 07 07:32:53 PM PDT 24
Finished Aug 07 07:35:55 PM PDT 24
Peak memory 265372 kb
Host smart-779ef2e0-2a14-412f-a74c-4d1068ce92d2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635014831 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_wo.635014831
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.2678312468
Short name T546
Test name
Test status
Simulation time 31568000 ps
CPU time 13.74 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:40:17 PM PDT 24
Peak memory 258364 kb
Host smart-60138842-c618-4c11-8536-7fec0dd050ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678312468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
2678312468
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.3560285265
Short name T116
Test name
Test status
Simulation time 18760000 ps
CPU time 16.01 seconds
Started Aug 07 07:39:46 PM PDT 24
Finished Aug 07 07:40:02 PM PDT 24
Peak memory 275276 kb
Host smart-7c67bdfa-a3b2-4630-b2e0-de4badc541c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560285265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3560285265
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2442888613
Short name T697
Test name
Test status
Simulation time 37259100 ps
CPU time 21.92 seconds
Started Aug 07 07:39:49 PM PDT 24
Finished Aug 07 07:40:11 PM PDT 24
Peak memory 266636 kb
Host smart-60aeba65-bef4-4d3f-be4a-48a962382ed5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442888613 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2442888613
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.1485256667
Short name T677
Test name
Test status
Simulation time 3677951300 ps
CPU time 43.85 seconds
Started Aug 07 07:39:49 PM PDT 24
Finished Aug 07 07:40:33 PM PDT 24
Peak memory 263044 kb
Host smart-4bdd70a1-aa2a-4fa5-96e1-8a25294d0abf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485256667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.1485256667
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.4063523663
Short name T871
Test name
Test status
Simulation time 26744056000 ps
CPU time 230.88 seconds
Started Aug 07 07:39:47 PM PDT 24
Finished Aug 07 07:43:38 PM PDT 24
Peak memory 285276 kb
Host smart-f8a38079-6d2c-45df-ab8e-37c1fe29ca85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063523663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.4063523663
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1097719216
Short name T875
Test name
Test status
Simulation time 22872562800 ps
CPU time 133.67 seconds
Started Aug 07 07:39:48 PM PDT 24
Finished Aug 07 07:42:02 PM PDT 24
Peak memory 293148 kb
Host smart-3734c694-7653-4d30-bcd5-eac3414ffe1a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097719216 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1097719216
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2949069926
Short name T537
Test name
Test status
Simulation time 87694700 ps
CPU time 132.94 seconds
Started Aug 07 07:39:49 PM PDT 24
Finished Aug 07 07:42:02 PM PDT 24
Peak memory 260228 kb
Host smart-b95286a6-0157-4f65-bb20-bbd9f3c0b41b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949069926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2949069926
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.2972647391
Short name T193
Test name
Test status
Simulation time 267763200 ps
CPU time 23.25 seconds
Started Aug 07 07:39:47 PM PDT 24
Finished Aug 07 07:40:10 PM PDT 24
Peak memory 265464 kb
Host smart-9f684430-2349-4904-bd13-6c61fdc93bad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972647391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.flash_ctrl_prog_reset.2972647391
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.3433763970
Short name T606
Test name
Test status
Simulation time 42068300 ps
CPU time 31.61 seconds
Started Aug 07 07:39:49 PM PDT 24
Finished Aug 07 07:40:21 PM PDT 24
Peak memory 273860 kb
Host smart-8525457f-fcfb-403c-8bb8-1deacf93038c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433763970 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3433763970
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.985393811
Short name T469
Test name
Test status
Simulation time 3236660300 ps
CPU time 74.97 seconds
Started Aug 07 07:39:46 PM PDT 24
Finished Aug 07 07:41:01 PM PDT 24
Peak memory 263892 kb
Host smart-f6884619-56bb-470c-b6e0-925d783aafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985393811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.985393811
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.4179976652
Short name T675
Test name
Test status
Simulation time 60042900 ps
CPU time 52.31 seconds
Started Aug 07 07:39:45 PM PDT 24
Finished Aug 07 07:40:38 PM PDT 24
Peak memory 271388 kb
Host smart-5d3a43a6-7952-42bf-80e7-f9ad6cff240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179976652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.4179976652
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2817217281
Short name T576
Test name
Test status
Simulation time 35729400 ps
CPU time 14.08 seconds
Started Aug 07 07:40:01 PM PDT 24
Finished Aug 07 07:40:16 PM PDT 24
Peak memory 258372 kb
Host smart-dc83bd0c-b59d-40a3-afc9-2a9e8565576d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817217281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2817217281
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.189462615
Short name T519
Test name
Test status
Simulation time 135773300 ps
CPU time 16.24 seconds
Started Aug 07 07:40:02 PM PDT 24
Finished Aug 07 07:40:18 PM PDT 24
Peak memory 284800 kb
Host smart-6639827b-0757-4526-8363-e43d0ace3936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189462615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.189462615
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1497223862
Short name T374
Test name
Test status
Simulation time 13303400 ps
CPU time 22.12 seconds
Started Aug 07 07:40:02 PM PDT 24
Finished Aug 07 07:40:25 PM PDT 24
Peak memory 266584 kb
Host smart-c82f2982-8a27-4a8e-b609-e270f34a3545
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497223862 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1497223862
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.433853201
Short name T97
Test name
Test status
Simulation time 4562396200 ps
CPU time 110.05 seconds
Started Aug 07 07:40:04 PM PDT 24
Finished Aug 07 07:41:54 PM PDT 24
Peak memory 261124 kb
Host smart-eb8ca291-8c35-4587-8403-adb8ef3a1f17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433853201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_h
w_sec_otp.433853201
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1011378299
Short name T762
Test name
Test status
Simulation time 7366658200 ps
CPU time 210.72 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:43:34 PM PDT 24
Peak memory 285172 kb
Host smart-9d7c324c-e431-4acc-92d6-7854ec4ac25a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011378299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1011378299
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.510873603
Short name T918
Test name
Test status
Simulation time 15526908200 ps
CPU time 304.8 seconds
Started Aug 07 07:40:01 PM PDT 24
Finished Aug 07 07:45:06 PM PDT 24
Peak memory 292312 kb
Host smart-0b2fa80a-774f-400f-a4b4-338e5ccfa6c0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510873603 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.510873603
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.433476463
Short name T567
Test name
Test status
Simulation time 90399900 ps
CPU time 134.4 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:42:17 PM PDT 24
Peak memory 260176 kb
Host smart-a34a1eeb-bdce-45c8-ad1b-0a0dd40aa68e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433476463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot
p_reset.433476463
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.1484066415
Short name T431
Test name
Test status
Simulation time 3805184100 ps
CPU time 142.56 seconds
Started Aug 07 07:40:05 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 260828 kb
Host smart-2091b64a-0725-4000-9932-5c3aad3e38bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484066415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.flash_ctrl_prog_reset.1484066415
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.558891310
Short name T406
Test name
Test status
Simulation time 66912500 ps
CPU time 31.55 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:40:34 PM PDT 24
Peak memory 274044 kb
Host smart-3db8ab0b-83a4-4a2b-855d-433004d2459b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558891310 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.558891310
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3675025564
Short name T511
Test name
Test status
Simulation time 371536700 ps
CPU time 53.03 seconds
Started Aug 07 07:40:04 PM PDT 24
Finished Aug 07 07:40:57 PM PDT 24
Peak memory 263404 kb
Host smart-36c143e3-f54f-401d-a673-39a999473e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675025564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3675025564
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.1635897622
Short name T502
Test name
Test status
Simulation time 485578800 ps
CPU time 149.11 seconds
Started Aug 07 07:40:08 PM PDT 24
Finished Aug 07 07:42:37 PM PDT 24
Peak memory 269036 kb
Host smart-83c8d497-423e-4e53-abe0-77108220c18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635897622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1635897622
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.1515774644
Short name T904
Test name
Test status
Simulation time 77823200 ps
CPU time 14.08 seconds
Started Aug 07 07:40:06 PM PDT 24
Finished Aug 07 07:40:20 PM PDT 24
Peak memory 258460 kb
Host smart-e4552f1d-4e85-40e5-8a26-ed808fd79317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515774644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
1515774644
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3720609623
Short name T119
Test name
Test status
Simulation time 51939000 ps
CPU time 13.43 seconds
Started Aug 07 07:40:07 PM PDT 24
Finished Aug 07 07:40:20 PM PDT 24
Peak memory 283360 kb
Host smart-d7b4bfde-ef16-4501-9618-4cfd5e7b3787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720609623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3720609623
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.1010350109
Short name T674
Test name
Test status
Simulation time 39392600 ps
CPU time 22.68 seconds
Started Aug 07 07:40:04 PM PDT 24
Finished Aug 07 07:40:27 PM PDT 24
Peak memory 273876 kb
Host smart-69e46d5c-7ff4-4acf-ae37-7372c470e569
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010350109 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.1010350109
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3440263769
Short name T671
Test name
Test status
Simulation time 7563131800 ps
CPU time 147.56 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:42:31 PM PDT 24
Peak memory 260816 kb
Host smart-5f52d69b-082a-4b71-8190-6e835df6f547
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440263769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.3440263769
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3734576077
Short name T1077
Test name
Test status
Simulation time 909257800 ps
CPU time 150.23 seconds
Started Aug 07 07:40:06 PM PDT 24
Finished Aug 07 07:42:36 PM PDT 24
Peak memory 293576 kb
Host smart-bf49441f-ac19-4e3c-bb0f-4dffee9fe76c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734576077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3734576077
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2416969330
Short name T398
Test name
Test status
Simulation time 22794833900 ps
CPU time 155.1 seconds
Started Aug 07 07:40:06 PM PDT 24
Finished Aug 07 07:42:41 PM PDT 24
Peak memory 293324 kb
Host smart-b48b982e-7a2e-4cf3-84b6-6911e667c09a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416969330 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2416969330
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.4093009348
Short name T950
Test name
Test status
Simulation time 38635100 ps
CPU time 132.02 seconds
Started Aug 07 07:40:04 PM PDT 24
Finished Aug 07 07:42:16 PM PDT 24
Peak memory 265340 kb
Host smart-f23bcfb6-b3a0-44ff-b528-99ed54d16ddf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093009348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.4093009348
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.1587823142
Short name T499
Test name
Test status
Simulation time 46801300 ps
CPU time 14.04 seconds
Started Aug 07 07:40:07 PM PDT 24
Finished Aug 07 07:40:21 PM PDT 24
Peak memory 260116 kb
Host smart-3febc630-7248-4e48-9773-f1bb88bee519
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587823142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.flash_ctrl_prog_reset.1587823142
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.3863039619
Short name T141
Test name
Test status
Simulation time 48404100 ps
CPU time 28.67 seconds
Started Aug 07 07:40:04 PM PDT 24
Finished Aug 07 07:40:33 PM PDT 24
Peak memory 273896 kb
Host smart-0431f033-3340-4013-87ef-f3f5f08617f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863039619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.3863039619
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.236774910
Short name T1000
Test name
Test status
Simulation time 61242700 ps
CPU time 29.01 seconds
Started Aug 07 07:40:08 PM PDT 24
Finished Aug 07 07:40:37 PM PDT 24
Peak memory 273888 kb
Host smart-88c9e407-b096-4839-bbbe-806f0df46cb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236774910 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.236774910
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.257229649
Short name T639
Test name
Test status
Simulation time 3817255700 ps
CPU time 72.34 seconds
Started Aug 07 07:40:06 PM PDT 24
Finished Aug 07 07:41:18 PM PDT 24
Peak memory 263936 kb
Host smart-31af1987-28fd-402e-af30-3bf0efb11aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257229649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.257229649
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.4192873099
Short name T120
Test name
Test status
Simulation time 59604400 ps
CPU time 75.53 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:41:19 PM PDT 24
Peak memory 275960 kb
Host smart-5bb05e53-744a-4a71-b559-74709e3e7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192873099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.4192873099
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1701050515
Short name T644
Test name
Test status
Simulation time 49329900 ps
CPU time 13.7 seconds
Started Aug 07 07:40:14 PM PDT 24
Finished Aug 07 07:40:28 PM PDT 24
Peak memory 258348 kb
Host smart-f260e1e2-c11c-43fe-99de-ce0035ad2da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701050515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1701050515
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.1405924721
Short name T831
Test name
Test status
Simulation time 49500800 ps
CPU time 13.48 seconds
Started Aug 07 07:40:12 PM PDT 24
Finished Aug 07 07:40:26 PM PDT 24
Peak memory 283360 kb
Host smart-5729597c-d342-4b83-ba87-3a8b7a1fec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405924721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1405924721
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.1250455550
Short name T1099
Test name
Test status
Simulation time 12819300 ps
CPU time 20.85 seconds
Started Aug 07 07:40:16 PM PDT 24
Finished Aug 07 07:40:37 PM PDT 24
Peak memory 273752 kb
Host smart-30362e7f-36dd-40e6-b890-2e4051ab6d69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250455550 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.1250455550
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3014847506
Short name T759
Test name
Test status
Simulation time 23293026800 ps
CPU time 279.38 seconds
Started Aug 07 07:40:05 PM PDT 24
Finished Aug 07 07:44:45 PM PDT 24
Peak memory 263020 kb
Host smart-73d19423-67ed-44c7-98c3-c34d4e5a6537
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014847506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.3014847506
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3044322676
Short name T1083
Test name
Test status
Simulation time 15006948700 ps
CPU time 198.74 seconds
Started Aug 07 07:40:03 PM PDT 24
Finished Aug 07 07:43:22 PM PDT 24
Peak memory 285216 kb
Host smart-bbfcc9ed-7441-4068-8bab-f6895d2a786e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044322676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3044322676
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.3720939175
Short name T837
Test name
Test status
Simulation time 38107100 ps
CPU time 112.27 seconds
Started Aug 07 07:40:08 PM PDT 24
Finished Aug 07 07:42:00 PM PDT 24
Peak memory 260184 kb
Host smart-3e4209b3-cff0-441f-883e-241bb18a11d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720939175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.3720939175
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3629104652
Short name T1058
Test name
Test status
Simulation time 5121083100 ps
CPU time 224.98 seconds
Started Aug 07 07:40:13 PM PDT 24
Finished Aug 07 07:43:58 PM PDT 24
Peak memory 260800 kb
Host smart-4a8955fc-f732-4bf8-85b4-fffbc43f6594
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629104652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.flash_ctrl_prog_reset.3629104652
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1342169994
Short name T881
Test name
Test status
Simulation time 15519230700 ps
CPU time 75.14 seconds
Started Aug 07 07:40:14 PM PDT 24
Finished Aug 07 07:41:29 PM PDT 24
Peak memory 263320 kb
Host smart-28e4f5df-75ba-48af-a231-0c630a0e6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342169994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1342169994
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3139661305
Short name T470
Test name
Test status
Simulation time 34886200 ps
CPU time 52.91 seconds
Started Aug 07 07:40:06 PM PDT 24
Finished Aug 07 07:40:59 PM PDT 24
Peak memory 271444 kb
Host smart-2cf22f23-f361-469b-bf4d-009b3c273a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139661305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3139661305
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.3975386531
Short name T1022
Test name
Test status
Simulation time 34871300 ps
CPU time 13.99 seconds
Started Aug 07 07:40:22 PM PDT 24
Finished Aug 07 07:40:36 PM PDT 24
Peak memory 265372 kb
Host smart-bcffc730-49b2-47cb-a0e9-d64744d3c2b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975386531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
3975386531
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2872010019
Short name T803
Test name
Test status
Simulation time 18341500 ps
CPU time 15.85 seconds
Started Aug 07 07:40:23 PM PDT 24
Finished Aug 07 07:40:39 PM PDT 24
Peak memory 284720 kb
Host smart-a92058f9-91b5-4ce9-96c4-28e049fc9d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872010019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2872010019
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.217640023
Short name T1
Test name
Test status
Simulation time 10633100 ps
CPU time 23.06 seconds
Started Aug 07 07:40:21 PM PDT 24
Finished Aug 07 07:40:45 PM PDT 24
Peak memory 265796 kb
Host smart-ab5c0944-f20e-465d-a392-fcd6b5073111
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217640023 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.217640023
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1149893191
Short name T459
Test name
Test status
Simulation time 4836601600 ps
CPU time 80.03 seconds
Started Aug 07 07:40:15 PM PDT 24
Finished Aug 07 07:41:35 PM PDT 24
Peak memory 263432 kb
Host smart-c2aadbd0-3a67-4778-8ed1-555f60ac3d26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149893191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1149893191
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.2091153934
Short name T600
Test name
Test status
Simulation time 1272608800 ps
CPU time 139.57 seconds
Started Aug 07 07:40:22 PM PDT 24
Finished Aug 07 07:42:41 PM PDT 24
Peak memory 291280 kb
Host smart-2a9f2c5f-0520-4c9d-9032-35c050a97d74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091153934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.2091153934
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.167935895
Short name T89
Test name
Test status
Simulation time 13440484300 ps
CPU time 284.96 seconds
Started Aug 07 07:40:25 PM PDT 24
Finished Aug 07 07:45:10 PM PDT 24
Peak memory 293404 kb
Host smart-8ccfbc8b-0776-456d-a741-b761678c8813
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167935895 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.167935895
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.867329788
Short name T898
Test name
Test status
Simulation time 31575816400 ps
CPU time 224.14 seconds
Started Aug 07 07:40:24 PM PDT 24
Finished Aug 07 07:44:08 PM PDT 24
Peak memory 265512 kb
Host smart-0fbba69d-076c-4b77-b5e8-f4b481cc72a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867329788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.flash_ctrl_prog_reset.867329788
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.3234870521
Short name T857
Test name
Test status
Simulation time 42970400 ps
CPU time 31.6 seconds
Started Aug 07 07:40:23 PM PDT 24
Finished Aug 07 07:40:55 PM PDT 24
Peak memory 273888 kb
Host smart-ca9e639a-e685-4922-a093-3f9109beb13d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234870521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.3234870521
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3370550747
Short name T30
Test name
Test status
Simulation time 1621211000 ps
CPU time 62.49 seconds
Started Aug 07 07:40:23 PM PDT 24
Finished Aug 07 07:41:25 PM PDT 24
Peak memory 263928 kb
Host smart-d437cce8-4462-408b-877f-1275b9009986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370550747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3370550747
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3634938168
Short name T1056
Test name
Test status
Simulation time 43668400 ps
CPU time 150.58 seconds
Started Aug 07 07:40:15 PM PDT 24
Finished Aug 07 07:42:46 PM PDT 24
Peak memory 278356 kb
Host smart-6d1c9a05-4e12-4d37-8972-c31372e0f7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634938168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3634938168
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.2257769850
Short name T501
Test name
Test status
Simulation time 34443100 ps
CPU time 14.17 seconds
Started Aug 07 07:40:33 PM PDT 24
Finished Aug 07 07:40:47 PM PDT 24
Peak memory 258308 kb
Host smart-55964ca2-a5e8-4239-961c-99f28d17f8db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257769850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
2257769850
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.511257246
Short name T921
Test name
Test status
Simulation time 14807400 ps
CPU time 15.61 seconds
Started Aug 07 07:40:31 PM PDT 24
Finished Aug 07 07:40:47 PM PDT 24
Peak memory 283432 kb
Host smart-14b6af0b-5e31-48f6-ab23-e488a23c856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511257246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.511257246
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.3658692202
Short name T12
Test name
Test status
Simulation time 45712800 ps
CPU time 21.89 seconds
Started Aug 07 07:40:30 PM PDT 24
Finished Aug 07 07:40:53 PM PDT 24
Peak memory 273832 kb
Host smart-a76aa43f-845e-4b34-9ea7-c6663bee686e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658692202 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.3658692202
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1455007252
Short name T303
Test name
Test status
Simulation time 14471914600 ps
CPU time 92.56 seconds
Started Aug 07 07:40:32 PM PDT 24
Finished Aug 07 07:42:05 PM PDT 24
Peak memory 263444 kb
Host smart-17316779-5838-4ccd-a2d1-5af74b04a9b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455007252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1455007252
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1359082216
Short name T662
Test name
Test status
Simulation time 41007300100 ps
CPU time 206.25 seconds
Started Aug 07 07:40:30 PM PDT 24
Finished Aug 07 07:43:56 PM PDT 24
Peak memory 293300 kb
Host smart-f951350a-65ad-4c00-a26a-2aef7a56b7d3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359082216 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1359082216
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.3874896600
Short name T737
Test name
Test status
Simulation time 147616600 ps
CPU time 111.2 seconds
Started Aug 07 07:40:30 PM PDT 24
Finished Aug 07 07:42:21 PM PDT 24
Peak memory 262592 kb
Host smart-fd78f258-b1a3-4615-8db3-639bbcb54d3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874896600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.3874896600
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.2814241237
Short name T1094
Test name
Test status
Simulation time 59545100 ps
CPU time 13.48 seconds
Started Aug 07 07:40:33 PM PDT 24
Finished Aug 07 07:40:47 PM PDT 24
Peak memory 259280 kb
Host smart-e277c730-731d-46c8-addf-46f9ddbf6a34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814241237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.flash_ctrl_prog_reset.2814241237
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.4126802601
Short name T673
Test name
Test status
Simulation time 77360500 ps
CPU time 29.01 seconds
Started Aug 07 07:40:32 PM PDT 24
Finished Aug 07 07:41:01 PM PDT 24
Peak memory 275992 kb
Host smart-f8653aec-8387-47f5-9e6a-48eda6647c60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126802601 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.4126802601
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1824520480
Short name T772
Test name
Test status
Simulation time 805360200 ps
CPU time 57.47 seconds
Started Aug 07 07:40:30 PM PDT 24
Finished Aug 07 07:41:28 PM PDT 24
Peak memory 263928 kb
Host smart-afa24af1-3387-4fa7-aef7-94c86b3b56f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824520480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1824520480
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3486851274
Short name T885
Test name
Test status
Simulation time 54618600 ps
CPU time 124.83 seconds
Started Aug 07 07:40:24 PM PDT 24
Finished Aug 07 07:42:29 PM PDT 24
Peak memory 276452 kb
Host smart-5803dc6b-8fec-41c7-b1aa-2c61da01ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486851274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3486851274
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1385337939
Short name T1047
Test name
Test status
Simulation time 69000100 ps
CPU time 14.41 seconds
Started Aug 07 07:40:42 PM PDT 24
Finished Aug 07 07:40:56 PM PDT 24
Peak memory 265348 kb
Host smart-652eb9e2-9625-4b3a-adac-06e37ddf75ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385337939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1385337939
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.1714757111
Short name T1071
Test name
Test status
Simulation time 15235100 ps
CPU time 15.98 seconds
Started Aug 07 07:40:43 PM PDT 24
Finished Aug 07 07:40:59 PM PDT 24
Peak memory 283408 kb
Host smart-7a97ce4b-b154-411a-b325-92fe08626f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714757111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1714757111
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3965238608
Short name T1016
Test name
Test status
Simulation time 10868600 ps
CPU time 21.86 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:41:02 PM PDT 24
Peak memory 273880 kb
Host smart-ef436a06-d6fe-45ce-ba15-f40e00ee52ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965238608 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3965238608
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.1870339761
Short name T421
Test name
Test status
Simulation time 5411019700 ps
CPU time 86.46 seconds
Started Aug 07 07:40:32 PM PDT 24
Finished Aug 07 07:41:59 PM PDT 24
Peak memory 263512 kb
Host smart-d32680e5-3555-4715-9aa4-3084b36fa82e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870339761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.1870339761
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.1235676402
Short name T883
Test name
Test status
Simulation time 4332238900 ps
CPU time 154.25 seconds
Started Aug 07 07:40:31 PM PDT 24
Finished Aug 07 07:43:05 PM PDT 24
Peak memory 294364 kb
Host smart-d1576173-cd2c-44c6-baf9-de5cd7b53d7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235676402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.1235676402
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.915678497
Short name T648
Test name
Test status
Simulation time 22608829700 ps
CPU time 252.53 seconds
Started Aug 07 07:40:32 PM PDT 24
Finished Aug 07 07:44:45 PM PDT 24
Peak memory 285380 kb
Host smart-02e08090-edc0-4967-8e41-1ec2dc1ac379
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915678497 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.915678497
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.2692854316
Short name T742
Test name
Test status
Simulation time 43233600 ps
CPU time 110.13 seconds
Started Aug 07 07:40:30 PM PDT 24
Finished Aug 07 07:42:21 PM PDT 24
Peak memory 260228 kb
Host smart-a40137ba-a65e-40da-b9f0-32c494f74312
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692854316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.2692854316
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2744445397
Short name T163
Test name
Test status
Simulation time 28450300 ps
CPU time 13.56 seconds
Started Aug 07 07:40:31 PM PDT 24
Finished Aug 07 07:40:45 PM PDT 24
Peak memory 265352 kb
Host smart-48496449-34a7-4bde-8e8f-674c45ee206f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744445397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.flash_ctrl_prog_reset.2744445397
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.4082055381
Short name T342
Test name
Test status
Simulation time 30695700 ps
CPU time 29.66 seconds
Started Aug 07 07:40:30 PM PDT 24
Finished Aug 07 07:41:00 PM PDT 24
Peak memory 275200 kb
Host smart-a5bf607a-ec33-4bf8-879e-69981b8b57ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082055381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.4082055381
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3093882259
Short name T41
Test name
Test status
Simulation time 130756600 ps
CPU time 32.12 seconds
Started Aug 07 07:40:33 PM PDT 24
Finished Aug 07 07:41:05 PM PDT 24
Peak memory 273852 kb
Host smart-56d012ed-7148-40ed-ab31-f39a5978ee93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093882259 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3093882259
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.43499568
Short name T927
Test name
Test status
Simulation time 1420572500 ps
CPU time 66.19 seconds
Started Aug 07 07:40:39 PM PDT 24
Finished Aug 07 07:41:46 PM PDT 24
Peak memory 263992 kb
Host smart-f2548626-2707-4eeb-a8e4-2de216337c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43499568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.43499568
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3653922429
Short name T1055
Test name
Test status
Simulation time 22695600 ps
CPU time 72.84 seconds
Started Aug 07 07:40:31 PM PDT 24
Finished Aug 07 07:41:43 PM PDT 24
Peak memory 275836 kb
Host smart-1d839307-3dc9-47ac-a8c2-7902891e2cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653922429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3653922429
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.2295010849
Short name T788
Test name
Test status
Simulation time 142351400 ps
CPU time 13.79 seconds
Started Aug 07 07:40:42 PM PDT 24
Finished Aug 07 07:40:56 PM PDT 24
Peak memory 258404 kb
Host smart-53269fc8-0acc-4ad5-8c1c-4ec1aaf26290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295010849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
2295010849
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3587401477
Short name T790
Test name
Test status
Simulation time 15630000 ps
CPU time 15.94 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:40:56 PM PDT 24
Peak memory 283356 kb
Host smart-0d64d474-5a32-485c-a2de-e055d537c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587401477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3587401477
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.629656008
Short name T60
Test name
Test status
Simulation time 11132400 ps
CPU time 22.45 seconds
Started Aug 07 07:40:41 PM PDT 24
Finished Aug 07 07:41:03 PM PDT 24
Peak memory 273932 kb
Host smart-7ab134e9-d893-4621-bb11-2a68896eb85d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629656008 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.629656008
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.2897570242
Short name T507
Test name
Test status
Simulation time 2687644900 ps
CPU time 220.2 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:44:20 PM PDT 24
Peak memory 263320 kb
Host smart-083be05f-1f08-4c81-8dec-ac1b4da2b450
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897570242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.2897570242
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.2506079735
Short name T829
Test name
Test status
Simulation time 5661289800 ps
CPU time 127.85 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:42:48 PM PDT 24
Peak memory 285668 kb
Host smart-4175ff50-a29a-4b76-9331-76d7a3f864c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506079735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.2506079735
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1659563115
Short name T25
Test name
Test status
Simulation time 12916555500 ps
CPU time 271.73 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:45:11 PM PDT 24
Peak memory 290140 kb
Host smart-0f1bd84a-c188-4dd8-b14a-4c419241a028
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659563115 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1659563115
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.447845395
Short name T568
Test name
Test status
Simulation time 73319500 ps
CPU time 134.44 seconds
Started Aug 07 07:40:43 PM PDT 24
Finished Aug 07 07:42:57 PM PDT 24
Peak memory 261244 kb
Host smart-17fdd100-e5c6-4415-9ae1-d9fec409b3eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447845395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.447845395
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.3227842528
Short name T804
Test name
Test status
Simulation time 120553500 ps
CPU time 13.64 seconds
Started Aug 07 07:40:41 PM PDT 24
Finished Aug 07 07:40:55 PM PDT 24
Peak memory 259400 kb
Host smart-6701e816-c0d7-4ae3-87e2-39aa8166ba77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227842528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.flash_ctrl_prog_reset.3227842528
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.4013734342
Short name T971
Test name
Test status
Simulation time 53919700 ps
CPU time 32.03 seconds
Started Aug 07 07:40:41 PM PDT 24
Finished Aug 07 07:41:14 PM PDT 24
Peak memory 273912 kb
Host smart-96b34040-6337-43c7-9e2f-8e3caeb05880
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013734342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.4013734342
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2238569238
Short name T849
Test name
Test status
Simulation time 43269000 ps
CPU time 31.2 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:41:12 PM PDT 24
Peak memory 273852 kb
Host smart-18fcf5ee-e4dc-445b-8079-b47f1b805698
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238569238 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.2238569238
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1579492855
Short name T690
Test name
Test status
Simulation time 814406300 ps
CPU time 53.29 seconds
Started Aug 07 07:40:40 PM PDT 24
Finished Aug 07 07:41:33 PM PDT 24
Peak memory 264032 kb
Host smart-0df54257-7783-42ef-b836-a2120a73b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579492855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1579492855
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.943209322
Short name T643
Test name
Test status
Simulation time 19864000 ps
CPU time 99.5 seconds
Started Aug 07 07:40:42 PM PDT 24
Finished Aug 07 07:42:22 PM PDT 24
Peak memory 277580 kb
Host smart-1b5a3893-23ac-48aa-9987-338da6f261ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943209322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.943209322
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3956916504
Short name T95
Test name
Test status
Simulation time 44064400 ps
CPU time 13.89 seconds
Started Aug 07 07:40:50 PM PDT 24
Finished Aug 07 07:41:04 PM PDT 24
Peak memory 265348 kb
Host smart-92a10f24-9759-4aba-8591-571e8da38510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956916504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3956916504
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.4203807040
Short name T441
Test name
Test status
Simulation time 47476400 ps
CPU time 15.87 seconds
Started Aug 07 07:40:49 PM PDT 24
Finished Aug 07 07:41:05 PM PDT 24
Peak memory 284784 kb
Host smart-59c8791c-a19f-43c6-8fa5-da17c11ecb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203807040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.4203807040
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.632467937
Short name T368
Test name
Test status
Simulation time 25495800 ps
CPU time 22.27 seconds
Started Aug 07 07:40:52 PM PDT 24
Finished Aug 07 07:41:14 PM PDT 24
Peak memory 273828 kb
Host smart-938d6f15-71b2-4c33-a5be-47c5f2429379
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632467937 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.632467937
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1091862333
Short name T509
Test name
Test status
Simulation time 913929500 ps
CPU time 46.34 seconds
Started Aug 07 07:40:50 PM PDT 24
Finished Aug 07 07:41:36 PM PDT 24
Peak memory 263400 kb
Host smart-40454969-0232-43e8-8b89-4852052b6ce7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091862333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.1091862333
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.347574836
Short name T634
Test name
Test status
Simulation time 3360551700 ps
CPU time 162.1 seconds
Started Aug 07 07:40:50 PM PDT 24
Finished Aug 07 07:43:32 PM PDT 24
Peak memory 293476 kb
Host smart-ba647bcc-d13d-4951-b0fa-be29a546571f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347574836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas
h_ctrl_intr_rd.347574836
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3317327738
Short name T1004
Test name
Test status
Simulation time 11881651800 ps
CPU time 308.48 seconds
Started Aug 07 07:40:51 PM PDT 24
Finished Aug 07 07:46:00 PM PDT 24
Peak memory 285372 kb
Host smart-c9b31e51-6f1e-4374-9140-9749442531e5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317327738 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3317327738
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.303284031
Short name T761
Test name
Test status
Simulation time 77168200 ps
CPU time 131.36 seconds
Started Aug 07 07:40:49 PM PDT 24
Finished Aug 07 07:43:01 PM PDT 24
Peak memory 260116 kb
Host smart-b4913a07-9c83-481c-946d-e893acd60aca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303284031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ot
p_reset.303284031
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.301914646
Short name T481
Test name
Test status
Simulation time 98242300 ps
CPU time 13.49 seconds
Started Aug 07 07:40:48 PM PDT 24
Finished Aug 07 07:41:02 PM PDT 24
Peak memory 259212 kb
Host smart-56a12328-2a51-440e-8f01-73e7dbea9f40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301914646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.flash_ctrl_prog_reset.301914646
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.3239029359
Short name T339
Test name
Test status
Simulation time 47500300 ps
CPU time 31.45 seconds
Started Aug 07 07:40:50 PM PDT 24
Finished Aug 07 07:41:22 PM PDT 24
Peak memory 275912 kb
Host smart-4b8de877-3ebc-4d22-9af1-73830e1a7ff7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239029359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.3239029359
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1967697943
Short name T346
Test name
Test status
Simulation time 148669500 ps
CPU time 31.26 seconds
Started Aug 07 07:40:52 PM PDT 24
Finished Aug 07 07:41:23 PM PDT 24
Peak memory 273824 kb
Host smart-5cf32dc9-3e63-454b-84fd-fcfe030643b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967697943 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1967697943
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3441672944
Short name T452
Test name
Test status
Simulation time 4511326400 ps
CPU time 63.72 seconds
Started Aug 07 07:40:52 PM PDT 24
Finished Aug 07 07:41:56 PM PDT 24
Peak memory 264044 kb
Host smart-987da6ce-fdcb-4a28-b730-77695aaece23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441672944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3441672944
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.4236051611
Short name T869
Test name
Test status
Simulation time 59249100 ps
CPU time 78.78 seconds
Started Aug 07 07:40:50 PM PDT 24
Finished Aug 07 07:42:09 PM PDT 24
Peak memory 275060 kb
Host smart-7ba0994a-42b6-4a26-9018-214cc6a389b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236051611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.4236051611
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.553606714
Short name T820
Test name
Test status
Simulation time 102549600 ps
CPU time 13.89 seconds
Started Aug 07 07:41:06 PM PDT 24
Finished Aug 07 07:41:20 PM PDT 24
Peak memory 265348 kb
Host smart-33853ca5-17cb-467c-96d0-6c8aa15a117a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553606714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.553606714
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1016253091
Short name T444
Test name
Test status
Simulation time 40961400 ps
CPU time 15.78 seconds
Started Aug 07 07:41:01 PM PDT 24
Finished Aug 07 07:41:17 PM PDT 24
Peak memory 275320 kb
Host smart-38006d71-c7b4-43ba-b8a6-ca4d77b68875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016253091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1016253091
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2416649542
Short name T536
Test name
Test status
Simulation time 56573600 ps
CPU time 22.17 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:41:25 PM PDT 24
Peak memory 273788 kb
Host smart-8522ef86-68de-43bd-bf02-cc50f57acfd3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416649542 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2416649542
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3572389438
Short name T301
Test name
Test status
Simulation time 7661794100 ps
CPU time 153.48 seconds
Started Aug 07 07:40:52 PM PDT 24
Finished Aug 07 07:43:25 PM PDT 24
Peak memory 263508 kb
Host smart-c05782b8-cff0-4ac9-9ac6-f1985f501ba5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572389438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3572389438
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.4009602612
Short name T320
Test name
Test status
Simulation time 1487733700 ps
CPU time 224.96 seconds
Started Aug 07 07:41:02 PM PDT 24
Finished Aug 07 07:44:47 PM PDT 24
Peak memory 285572 kb
Host smart-6954fa09-9b29-4528-bfb7-badc7dbeb0a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009602612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.4009602612
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2465037020
Short name T649
Test name
Test status
Simulation time 13805418600 ps
CPU time 138.44 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:43:21 PM PDT 24
Peak memory 293240 kb
Host smart-afd661e5-82ed-4c33-be59-f998b70e6755
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465037020 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.2465037020
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.1860777277
Short name T500
Test name
Test status
Simulation time 41701700 ps
CPU time 132.5 seconds
Started Aug 07 07:41:02 PM PDT 24
Finished Aug 07 07:43:14 PM PDT 24
Peak memory 260364 kb
Host smart-9cf1130b-9f58-4d64-91f9-5a5f378cf843
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860777277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.1860777277
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1345094621
Short name T158
Test name
Test status
Simulation time 19222000 ps
CPU time 13.54 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:41:16 PM PDT 24
Peak memory 259124 kb
Host smart-ced16baa-132c-4bf9-ac60-017d306ea3af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345094621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.flash_ctrl_prog_reset.1345094621
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.2139126927
Short name T696
Test name
Test status
Simulation time 125504500 ps
CPU time 31.96 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:41:35 PM PDT 24
Peak memory 273860 kb
Host smart-e719e6b2-51b6-4f26-9f3e-56c5cfa2846d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139126927 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.2139126927
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.1445721539
Short name T377
Test name
Test status
Simulation time 1111534900 ps
CPU time 57.41 seconds
Started Aug 07 07:41:05 PM PDT 24
Finished Aug 07 07:42:02 PM PDT 24
Peak memory 264016 kb
Host smart-540db853-dd12-44fe-bd2d-cf57768c774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445721539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1445721539
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3745641577
Short name T637
Test name
Test status
Simulation time 23643700 ps
CPU time 52.92 seconds
Started Aug 07 07:40:52 PM PDT 24
Finished Aug 07 07:41:45 PM PDT 24
Peak memory 271376 kb
Host smart-fdb3e68d-6e31-4512-aa18-1d8ba9f026b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745641577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3745641577
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.605829162
Short name T93
Test name
Test status
Simulation time 871834600 ps
CPU time 14.19 seconds
Started Aug 07 07:33:46 PM PDT 24
Finished Aug 07 07:34:01 PM PDT 24
Peak memory 258392 kb
Host smart-7ef7515c-06f9-4c12-bfc3-0383ede36834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605829162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.605829162
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.1083905303
Short name T361
Test name
Test status
Simulation time 53789900 ps
CPU time 14.05 seconds
Started Aug 07 07:33:45 PM PDT 24
Finished Aug 07 07:33:59 PM PDT 24
Peak memory 261596 kb
Host smart-5b093c27-4178-41e9-bcb2-de9395cdf6a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083905303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.1083905303
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2885481416
Short name T415
Test name
Test status
Simulation time 109514600 ps
CPU time 15.83 seconds
Started Aug 07 07:33:34 PM PDT 24
Finished Aug 07 07:33:50 PM PDT 24
Peak memory 284704 kb
Host smart-b8a8cb3f-9c58-4921-a067-d4f5fd5d84b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885481416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2885481416
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.2366320259
Short name T250
Test name
Test status
Simulation time 717461900 ps
CPU time 189.42 seconds
Started Aug 07 07:33:22 PM PDT 24
Finished Aug 07 07:36:31 PM PDT 24
Peak memory 278320 kb
Host smart-3cafb837-0a6a-49c6-a2df-bb4f85d10484
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366320259 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.2366320259
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2342918883
Short name T156
Test name
Test status
Simulation time 12035509200 ps
CPU time 442.95 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:40:38 PM PDT 24
Peak memory 263712 kb
Host smart-a8311066-477b-4041-97ba-cb98f024c6aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342918883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2342918883
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2271110548
Short name T855
Test name
Test status
Simulation time 18218572400 ps
CPU time 2390.82 seconds
Started Aug 07 07:33:11 PM PDT 24
Finished Aug 07 08:13:02 PM PDT 24
Peak memory 263044 kb
Host smart-66bf314b-141a-4994-991b-b316fc22c0b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2271110548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.2271110548
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.558431296
Short name T86
Test name
Test status
Simulation time 2120435800 ps
CPU time 1962.98 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 08:05:58 PM PDT 24
Peak memory 264060 kb
Host smart-76b309d0-5c04-47f7-8bf4-130688ec2ca5
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558431296 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.558431296
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.398741480
Short name T291
Test name
Test status
Simulation time 1358503100 ps
CPU time 874.86 seconds
Started Aug 07 07:33:11 PM PDT 24
Finished Aug 07 07:47:46 PM PDT 24
Peak memory 270660 kb
Host smart-0f81e46a-ca2e-45db-8a9c-d7bffd0af564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398741480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.398741480
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2909244200
Short name T747
Test name
Test status
Simulation time 107387800 ps
CPU time 22.56 seconds
Started Aug 07 07:33:13 PM PDT 24
Finished Aug 07 07:33:36 PM PDT 24
Peak memory 263896 kb
Host smart-7ba8b334-0e95-4fc6-8d45-1a3d11d2657e
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909244200 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_fetch_code.2909244200
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.1717768410
Short name T128
Test name
Test status
Simulation time 187397656300 ps
CPU time 2875.32 seconds
Started Aug 07 07:33:12 PM PDT 24
Finished Aug 07 08:21:08 PM PDT 24
Peak memory 265308 kb
Host smart-fd756719-8d22-4162-8caa-dfec399f4a1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717768410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.1717768410
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3458892385
Short name T731
Test name
Test status
Simulation time 46715000 ps
CPU time 37.29 seconds
Started Aug 07 07:33:11 PM PDT 24
Finished Aug 07 07:33:48 PM PDT 24
Peak memory 265520 kb
Host smart-57d577fb-e311-4bae-9a1f-a57c2a339dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458892385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3458892385
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1858405122
Short name T560
Test name
Test status
Simulation time 10019808800 ps
CPU time 75.25 seconds
Started Aug 07 07:33:45 PM PDT 24
Finished Aug 07 07:35:00 PM PDT 24
Peak memory 286612 kb
Host smart-f0933e5f-3ff0-4bbf-8e37-3c0c9a41c734
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858405122 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1858405122
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2584837839
Short name T628
Test name
Test status
Simulation time 26538300 ps
CPU time 13.78 seconds
Started Aug 07 07:33:48 PM PDT 24
Finished Aug 07 07:34:02 PM PDT 24
Peak memory 258528 kb
Host smart-3b6e0fe8-debf-46d1-84b3-a663feb4c538
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584837839 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2584837839
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.361922301
Short name T1104
Test name
Test status
Simulation time 130166018000 ps
CPU time 857.92 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:47:33 PM PDT 24
Peak memory 264568 kb
Host smart-67915b7b-a924-4d48-971c-debfbab13592
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361922301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.361922301
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1996846974
Short name T700
Test name
Test status
Simulation time 1913909700 ps
CPU time 76 seconds
Started Aug 07 07:33:11 PM PDT 24
Finished Aug 07 07:34:28 PM PDT 24
Peak memory 260668 kb
Host smart-8d837b64-7f36-4197-b938-e39b36ff8bc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996846974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1996846974
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.2412929901
Short name T654
Test name
Test status
Simulation time 11509040100 ps
CPU time 728.96 seconds
Started Aug 07 07:33:21 PM PDT 24
Finished Aug 07 07:45:30 PM PDT 24
Peak memory 335928 kb
Host smart-0cc0259c-6d16-4292-a174-5df1537b2c48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412929901 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.2412929901
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2849647501
Short name T846
Test name
Test status
Simulation time 1753945500 ps
CPU time 165.12 seconds
Started Aug 07 07:33:22 PM PDT 24
Finished Aug 07 07:36:07 PM PDT 24
Peak memory 294692 kb
Host smart-80d3da0a-2650-4289-bee2-c889b03f7a0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849647501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2849647501
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3088862675
Short name T968
Test name
Test status
Simulation time 22290905200 ps
CPU time 163.03 seconds
Started Aug 07 07:33:35 PM PDT 24
Finished Aug 07 07:36:18 PM PDT 24
Peak memory 293452 kb
Host smart-a1f743a0-667b-4ecb-979e-840b7cbe89bd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088862675 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3088862675
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.1086342965
Short name T29
Test name
Test status
Simulation time 2054386000 ps
CPU time 64.19 seconds
Started Aug 07 07:33:23 PM PDT 24
Finished Aug 07 07:34:27 PM PDT 24
Peak memory 260664 kb
Host smart-6017b3d6-8b9c-40f9-944e-a6b997a57617
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086342965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.1086342965
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.848194114
Short name T1062
Test name
Test status
Simulation time 406177650600 ps
CPU time 366.25 seconds
Started Aug 07 07:33:34 PM PDT 24
Finished Aug 07 07:39:41 PM PDT 24
Peak memory 265488 kb
Host smart-8f968930-07c9-4ad3-8c78-2f859814d9f7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848
194114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.848194114
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.3246860601
Short name T635
Test name
Test status
Simulation time 4339374600 ps
CPU time 65.59 seconds
Started Aug 07 07:33:11 PM PDT 24
Finished Aug 07 07:34:17 PM PDT 24
Peak memory 260964 kb
Host smart-7b29e1ff-082c-4d67-b54f-083ef3217d6a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246860601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3246860601
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.207085223
Short name T633
Test name
Test status
Simulation time 47535100 ps
CPU time 13.59 seconds
Started Aug 07 07:33:45 PM PDT 24
Finished Aug 07 07:33:59 PM PDT 24
Peak memory 260324 kb
Host smart-5a959518-cdc0-4086-91e1-0fbfd391d187
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207085223 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.207085223
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.694648467
Short name T157
Test name
Test status
Simulation time 4940211200 ps
CPU time 76.26 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:34:31 PM PDT 24
Peak memory 260820 kb
Host smart-ee8d7f4c-9e06-4122-a780-79e56393bcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694648467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.694648467
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.2207046267
Short name T778
Test name
Test status
Simulation time 22619829500 ps
CPU time 289.31 seconds
Started Aug 07 07:33:15 PM PDT 24
Finished Aug 07 07:38:04 PM PDT 24
Peak memory 274384 kb
Host smart-2b93b4fe-35c2-4e0b-b93f-fa5637427110
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207046267 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2207046267
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3392104643
Short name T925
Test name
Test status
Simulation time 36441400 ps
CPU time 134.27 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:35:29 PM PDT 24
Peak memory 260348 kb
Host smart-baf1e0df-31f3-4e4c-9ce9-5d1a6294c5fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392104643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3392104643
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.445398788
Short name T1027
Test name
Test status
Simulation time 2565950300 ps
CPU time 190.96 seconds
Started Aug 07 07:33:21 PM PDT 24
Finished Aug 07 07:36:32 PM PDT 24
Peak memory 290304 kb
Host smart-e17349ea-9fe9-45ab-8c44-5cf33345c1e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445398788 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.445398788
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.2642569107
Short name T1084
Test name
Test status
Simulation time 52723400 ps
CPU time 67.46 seconds
Started Aug 07 07:33:13 PM PDT 24
Finished Aug 07 07:34:21 PM PDT 24
Peak memory 263348 kb
Host smart-e1fbcda8-421b-4296-9d9d-f14aa83fb8fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642569107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2642569107
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.954522496
Short name T75
Test name
Test status
Simulation time 935140000 ps
CPU time 19.94 seconds
Started Aug 07 07:33:34 PM PDT 24
Finished Aug 07 07:33:54 PM PDT 24
Peak memory 265848 kb
Host smart-7b2d0377-485c-47e9-8740-500366240cbd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954522496 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.954522496
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3515209964
Short name T160
Test name
Test status
Simulation time 221801100 ps
CPU time 14.71 seconds
Started Aug 07 07:33:34 PM PDT 24
Finished Aug 07 07:33:49 PM PDT 24
Peak memory 265444 kb
Host smart-f541452c-d9e2-4022-8fe3-8bb107dbbeae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515209964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_prog_reset.3515209964
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.4196618128
Short name T963
Test name
Test status
Simulation time 3589059000 ps
CPU time 936.29 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:48:50 PM PDT 24
Peak memory 285916 kb
Host smart-88b8498d-0ed8-4a63-96de-14177b390808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196618128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.4196618128
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2388651328
Short name T533
Test name
Test status
Simulation time 75931900 ps
CPU time 104.57 seconds
Started Aug 07 07:33:12 PM PDT 24
Finished Aug 07 07:34:56 PM PDT 24
Peak memory 262944 kb
Host smart-77ddc593-a2ca-417a-92c7-7860c67493cd
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2388651328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2388651328
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.2587739404
Short name T350
Test name
Test status
Simulation time 63093600 ps
CPU time 35.15 seconds
Started Aug 07 07:33:35 PM PDT 24
Finished Aug 07 07:34:11 PM PDT 24
Peak memory 275940 kb
Host smart-fc6d3380-4a0f-4cc5-977d-d572716e85a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587739404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.2587739404
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.1298175165
Short name T414
Test name
Test status
Simulation time 18702200 ps
CPU time 23.5 seconds
Started Aug 07 07:33:25 PM PDT 24
Finished Aug 07 07:33:48 PM PDT 24
Peak memory 265572 kb
Host smart-0c0ecf5f-9272-4786-b279-df878c0ae485
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298175165 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.1298175165
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2684059651
Short name T582
Test name
Test status
Simulation time 25397600 ps
CPU time 21.96 seconds
Started Aug 07 07:33:23 PM PDT 24
Finished Aug 07 07:33:45 PM PDT 24
Peak memory 265436 kb
Host smart-7adcfba9-3777-4704-ba7a-165b47dea691
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684059651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2684059651
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.3575614251
Short name T851
Test name
Test status
Simulation time 2052615900 ps
CPU time 127.99 seconds
Started Aug 07 07:33:12 PM PDT 24
Finished Aug 07 07:35:20 PM PDT 24
Peak memory 290256 kb
Host smart-1b69ce5a-7187-46a4-87ee-aa03edf15c9a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575614251 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.3575614251
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2405607956
Short name T914
Test name
Test status
Simulation time 696430900 ps
CPU time 157.72 seconds
Started Aug 07 07:33:25 PM PDT 24
Finished Aug 07 07:36:03 PM PDT 24
Peak memory 282140 kb
Host smart-e459bd9f-3b2b-4d89-849e-69b2be90cc14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2405607956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2405607956
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1269197691
Short name T982
Test name
Test status
Simulation time 1587575900 ps
CPU time 134.76 seconds
Started Aug 07 07:33:25 PM PDT 24
Finished Aug 07 07:35:40 PM PDT 24
Peak memory 295632 kb
Host smart-1a0e8d67-4f70-4732-956f-40f3e9ee2616
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269197691 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1269197691
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.960837485
Short name T573
Test name
Test status
Simulation time 22887773800 ps
CPU time 628.31 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:43:43 PM PDT 24
Peak memory 309852 kb
Host smart-d96762bf-5e25-4784-890d-f68cab750245
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960837485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_rw.960837485
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.675672860
Short name T667
Test name
Test status
Simulation time 71159900 ps
CPU time 32.54 seconds
Started Aug 07 07:33:35 PM PDT 24
Finished Aug 07 07:34:07 PM PDT 24
Peak memory 267752 kb
Host smart-c82f9818-ddcf-4f51-8ab8-0305a4eb286c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675672860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.675672860
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3627528130
Short name T583
Test name
Test status
Simulation time 30080400 ps
CPU time 29.45 seconds
Started Aug 07 07:33:32 PM PDT 24
Finished Aug 07 07:34:02 PM PDT 24
Peak memory 275928 kb
Host smart-5322ee21-c663-4948-8b36-43a0bbe815f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627528130 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3627528130
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.3574769192
Short name T786
Test name
Test status
Simulation time 4099795900 ps
CPU time 255.68 seconds
Started Aug 07 07:33:23 PM PDT 24
Finished Aug 07 07:37:39 PM PDT 24
Peak memory 295288 kb
Host smart-03bf0b0b-05a0-4a4f-a56f-7cb6c6968f14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574769192 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.flash_ctrl_rw_serr.3574769192
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.861434819
Short name T61
Test name
Test status
Simulation time 1912076500 ps
CPU time 4983.15 seconds
Started Aug 07 07:33:41 PM PDT 24
Finished Aug 07 08:56:45 PM PDT 24
Peak memory 286308 kb
Host smart-d0775a89-5b16-467a-8881-59a80af0eb70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861434819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.861434819
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2279486827
Short name T825
Test name
Test status
Simulation time 11594198200 ps
CPU time 108.59 seconds
Started Aug 07 07:33:23 PM PDT 24
Finished Aug 07 07:35:12 PM PDT 24
Peak memory 265600 kb
Host smart-21b5670e-5889-4057-8cf0-02ac09743a9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279486827 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2279486827
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.2041017816
Short name T707
Test name
Test status
Simulation time 635904500 ps
CPU time 66.66 seconds
Started Aug 07 07:33:25 PM PDT 24
Finished Aug 07 07:34:32 PM PDT 24
Peak memory 273912 kb
Host smart-53133c57-8350-4cdf-8dac-9ad917c94866
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041017816 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.2041017816
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.1406058966
Short name T630
Test name
Test status
Simulation time 75450000 ps
CPU time 99.13 seconds
Started Aug 07 07:33:04 PM PDT 24
Finished Aug 07 07:34:44 PM PDT 24
Peak memory 277300 kb
Host smart-06321fa4-0494-4ab2-85b8-2dadf1192405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406058966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1406058966
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.1583201031
Short name T668
Test name
Test status
Simulation time 51880000 ps
CPU time 26.21 seconds
Started Aug 07 07:33:14 PM PDT 24
Finished Aug 07 07:33:40 PM PDT 24
Peak memory 259832 kb
Host smart-f5ae3eee-82ff-43c9-ad1c-75c569d6db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583201031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1583201031
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.681186353
Short name T192
Test name
Test status
Simulation time 22236200 ps
CPU time 26.67 seconds
Started Aug 07 07:33:15 PM PDT 24
Finished Aug 07 07:33:42 PM PDT 24
Peak memory 262632 kb
Host smart-6fda6bf0-bae1-4cda-b9f1-aee61bf2f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681186353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.681186353
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.3282845127
Short name T3
Test name
Test status
Simulation time 4312140800 ps
CPU time 177.3 seconds
Started Aug 07 07:33:15 PM PDT 24
Finished Aug 07 07:36:12 PM PDT 24
Peak memory 260172 kb
Host smart-d32527ef-69ed-4c47-bc19-8861fe6aa16a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282845127 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.3282845127
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.4216158269
Short name T520
Test name
Test status
Simulation time 52773500 ps
CPU time 13.87 seconds
Started Aug 07 07:41:04 PM PDT 24
Finished Aug 07 07:41:18 PM PDT 24
Peak memory 265356 kb
Host smart-005019da-59a4-4394-8983-e0f12bcc1a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216158269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
4216158269
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.4184817020
Short name T565
Test name
Test status
Simulation time 19649400 ps
CPU time 16.19 seconds
Started Aug 07 07:41:06 PM PDT 24
Finished Aug 07 07:41:22 PM PDT 24
Peak memory 284644 kb
Host smart-69b6543d-ffc2-449d-8b0f-133479d1bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184817020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.4184817020
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.1924502624
Short name T911
Test name
Test status
Simulation time 30926700 ps
CPU time 20.83 seconds
Started Aug 07 07:41:02 PM PDT 24
Finished Aug 07 07:41:23 PM PDT 24
Peak memory 274552 kb
Host smart-12205742-8fa2-4b43-bb9a-74d0185d7c6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924502624 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.1924502624
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.7930022
Short name T308
Test name
Test status
Simulation time 3570830600 ps
CPU time 117.57 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:43:01 PM PDT 24
Peak memory 263516 kb
Host smart-f0b72c9a-f91b-4bf9-9847-18c78cfd4734
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7930022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_
sec_otp.7930022
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2965318375
Short name T695
Test name
Test status
Simulation time 5980199600 ps
CPU time 186.22 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:44:09 PM PDT 24
Peak memory 291192 kb
Host smart-40ea5c48-c51d-448f-82da-1b51d1fab714
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965318375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2965318375
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.82972575
Short name T323
Test name
Test status
Simulation time 23444835300 ps
CPU time 179.71 seconds
Started Aug 07 07:41:02 PM PDT 24
Finished Aug 07 07:44:02 PM PDT 24
Peak memory 294668 kb
Host smart-5adb46a0-1157-46d9-88c7-6eb72380282d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82972575 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.82972575
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.2634596115
Short name T629
Test name
Test status
Simulation time 138764200 ps
CPU time 133.52 seconds
Started Aug 07 07:41:03 PM PDT 24
Finished Aug 07 07:43:17 PM PDT 24
Peak memory 261208 kb
Host smart-edf8e461-e125-46a5-a89f-a89acd86c84e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634596115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.2634596115
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.2027318576
Short name T755
Test name
Test status
Simulation time 26713900 ps
CPU time 30.89 seconds
Started Aug 07 07:41:04 PM PDT 24
Finished Aug 07 07:41:34 PM PDT 24
Peak memory 267708 kb
Host smart-6b8d426f-b2b2-4e12-95fb-590f6583e6b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027318576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.2027318576
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3468823077
Short name T1091
Test name
Test status
Simulation time 77407600 ps
CPU time 31.26 seconds
Started Aug 07 07:41:05 PM PDT 24
Finished Aug 07 07:41:37 PM PDT 24
Peak memory 275900 kb
Host smart-e21cd285-6438-4521-a0c1-1841e856ffa8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468823077 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3468823077
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.370928800
Short name T1101
Test name
Test status
Simulation time 1008970200 ps
CPU time 64.29 seconds
Started Aug 07 07:41:04 PM PDT 24
Finished Aug 07 07:42:08 PM PDT 24
Peak memory 264008 kb
Host smart-d108a2a6-c6f5-4b72-bd4a-27a57ca5287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370928800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.370928800
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.1529349192
Short name T484
Test name
Test status
Simulation time 39029400 ps
CPU time 100.93 seconds
Started Aug 07 07:41:05 PM PDT 24
Finished Aug 07 07:42:46 PM PDT 24
Peak memory 276248 kb
Host smart-6d16d57c-2508-4b95-a400-86433f250c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529349192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1529349192
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.1498759559
Short name T493
Test name
Test status
Simulation time 20284700 ps
CPU time 14.46 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:41:31 PM PDT 24
Peak memory 258384 kb
Host smart-c53cb11b-3298-4879-82e1-0826c63bc214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498759559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
1498759559
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.2082082990
Short name T418
Test name
Test status
Simulation time 14455600 ps
CPU time 16.19 seconds
Started Aug 07 07:41:19 PM PDT 24
Finished Aug 07 07:41:35 PM PDT 24
Peak memory 275272 kb
Host smart-8b6d9c56-3933-40b7-8aa1-24b3e2b92b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082082990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2082082990
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.3835657656
Short name T373
Test name
Test status
Simulation time 15193700 ps
CPU time 22.1 seconds
Started Aug 07 07:41:19 PM PDT 24
Finished Aug 07 07:41:41 PM PDT 24
Peak memory 273832 kb
Host smart-bf34236a-1077-4db9-8d70-853925e94417
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835657656 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.3835657656
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3083984413
Short name T399
Test name
Test status
Simulation time 23175144000 ps
CPU time 124.03 seconds
Started Aug 07 07:41:15 PM PDT 24
Finished Aug 07 07:43:19 PM PDT 24
Peak memory 293136 kb
Host smart-13757596-1339-4a3a-91fd-06fc661675ea
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083984413 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3083984413
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2240569252
Short name T515
Test name
Test status
Simulation time 42810800 ps
CPU time 133.75 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:43:29 PM PDT 24
Peak memory 261292 kb
Host smart-a3403636-340d-4c06-ba9c-c5b0c4b74853
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240569252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2240569252
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.3186860742
Short name T281
Test name
Test status
Simulation time 75329100 ps
CPU time 31.54 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:41:48 PM PDT 24
Peak memory 273932 kb
Host smart-8fbb9cd4-d7e0-4611-a779-d0c93a5ef375
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186860742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.3186860742
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.4262852268
Short name T917
Test name
Test status
Simulation time 210441800 ps
CPU time 31.28 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:41:47 PM PDT 24
Peak memory 273888 kb
Host smart-8362f341-2d36-4ec1-923f-80b282700ca5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262852268 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.4262852268
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1772388839
Short name T945
Test name
Test status
Simulation time 83526900 ps
CPU time 123.12 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:43:19 PM PDT 24
Peak memory 277752 kb
Host smart-fe6b5098-b29b-48aa-b441-36705987ea8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772388839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1772388839
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.607494948
Short name T949
Test name
Test status
Simulation time 60776000 ps
CPU time 13.82 seconds
Started Aug 07 07:41:17 PM PDT 24
Finished Aug 07 07:41:31 PM PDT 24
Peak memory 259372 kb
Host smart-5248ce72-7951-42e1-8f7c-629990a4ba6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607494948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.607494948
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3165877257
Short name T433
Test name
Test status
Simulation time 50665100 ps
CPU time 13.95 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:41:30 PM PDT 24
Peak memory 284704 kb
Host smart-aff32dc4-018b-40dd-946c-88580b2a2e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165877257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3165877257
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3597719112
Short name T486
Test name
Test status
Simulation time 10484500 ps
CPU time 20.72 seconds
Started Aug 07 07:41:17 PM PDT 24
Finished Aug 07 07:41:38 PM PDT 24
Peak memory 266612 kb
Host smart-b0a1c833-cac8-4e5e-b7e4-8972a80cd2e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597719112 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3597719112
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.151491956
Short name T473
Test name
Test status
Simulation time 3089359000 ps
CPU time 263.16 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:45:40 PM PDT 24
Peak memory 263328 kb
Host smart-f27a914a-4cb4-4420-89d3-85bc2bcd1493
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151491956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.151491956
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2287352142
Short name T317
Test name
Test status
Simulation time 3400632000 ps
CPU time 290.11 seconds
Started Aug 07 07:41:17 PM PDT 24
Finished Aug 07 07:46:07 PM PDT 24
Peak memory 285496 kb
Host smart-2ac67a73-d3a8-488b-81ec-b3c50fb199cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287352142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2287352142
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2764987760
Short name T1082
Test name
Test status
Simulation time 32481719500 ps
CPU time 322.38 seconds
Started Aug 07 07:41:18 PM PDT 24
Finished Aug 07 07:46:40 PM PDT 24
Peak memory 294720 kb
Host smart-904cd316-5d46-4ccf-b2c6-606e8732817e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764987760 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2764987760
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1789782632
Short name T826
Test name
Test status
Simulation time 72905900 ps
CPU time 131.21 seconds
Started Aug 07 07:41:17 PM PDT 24
Finished Aug 07 07:43:28 PM PDT 24
Peak memory 260088 kb
Host smart-79634d52-2fd5-4d92-8eeb-310665300c3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789782632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1789782632
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.184593193
Short name T26
Test name
Test status
Simulation time 68183700 ps
CPU time 31.37 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:41:48 PM PDT 24
Peak memory 273848 kb
Host smart-4267fa3c-c634-4498-ad85-a933d50dad53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184593193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.184593193
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1904011486
Short name T280
Test name
Test status
Simulation time 73163300 ps
CPU time 31.17 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:41:47 PM PDT 24
Peak memory 274076 kb
Host smart-3d020735-e8d5-4ed3-bcb3-b46abe425ac1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904011486 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1904011486
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.620211841
Short name T236
Test name
Test status
Simulation time 1739460000 ps
CPU time 74.61 seconds
Started Aug 07 07:41:19 PM PDT 24
Finished Aug 07 07:42:34 PM PDT 24
Peak memory 263940 kb
Host smart-587e87bd-0f33-4bbb-a963-18e9ca284c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620211841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.620211841
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.2860186551
Short name T726
Test name
Test status
Simulation time 21385100 ps
CPU time 101.1 seconds
Started Aug 07 07:41:19 PM PDT 24
Finished Aug 07 07:43:00 PM PDT 24
Peak memory 276104 kb
Host smart-6c348919-3c3a-494d-849e-73d0e4481e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860186551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2860186551
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.247617065
Short name T787
Test name
Test status
Simulation time 108144800 ps
CPU time 13.93 seconds
Started Aug 07 07:41:27 PM PDT 24
Finished Aug 07 07:41:42 PM PDT 24
Peak memory 258420 kb
Host smart-6ed64f80-7ce7-49ed-bbe1-ae5a09ac8144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247617065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.247617065
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.142662275
Short name T427
Test name
Test status
Simulation time 39084400 ps
CPU time 15.92 seconds
Started Aug 07 07:41:22 PM PDT 24
Finished Aug 07 07:41:38 PM PDT 24
Peak memory 284688 kb
Host smart-1a4d4b2c-e340-46d0-a4b7-bf45a2f28301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142662275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.142662275
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3513858801
Short name T476
Test name
Test status
Simulation time 10554100 ps
CPU time 20.92 seconds
Started Aug 07 07:41:22 PM PDT 24
Finished Aug 07 07:41:43 PM PDT 24
Peak memory 274184 kb
Host smart-24f84601-cc11-4de7-9174-c352c9311381
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513858801 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3513858801
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1998769210
Short name T956
Test name
Test status
Simulation time 6460072700 ps
CPU time 94.42 seconds
Started Aug 07 07:41:16 PM PDT 24
Finished Aug 07 07:42:51 PM PDT 24
Peak memory 263468 kb
Host smart-36b99fad-68a2-4154-9f94-949cda22e626
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998769210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.1998769210
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2808013213
Short name T620
Test name
Test status
Simulation time 24367451300 ps
CPU time 166.97 seconds
Started Aug 07 07:41:28 PM PDT 24
Finished Aug 07 07:44:15 PM PDT 24
Peak memory 285600 kb
Host smart-7f7b132f-a10e-4a5c-a7b5-684490856068
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808013213 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.2808013213
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.4078510192
Short name T464
Test name
Test status
Simulation time 140363000 ps
CPU time 133.47 seconds
Started Aug 07 07:41:22 PM PDT 24
Finished Aug 07 07:43:35 PM PDT 24
Peak memory 261288 kb
Host smart-fb31541b-6950-4a13-8963-52bb4ea5f43f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078510192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.4078510192
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.3125412262
Short name T348
Test name
Test status
Simulation time 76667700 ps
CPU time 29.42 seconds
Started Aug 07 07:41:28 PM PDT 24
Finished Aug 07 07:41:58 PM PDT 24
Peak memory 275940 kb
Host smart-6a988c5f-7ce6-4f0e-a094-36fb960f47ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125412262 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.3125412262
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.490588313
Short name T394
Test name
Test status
Simulation time 1958502700 ps
CPU time 80.82 seconds
Started Aug 07 07:41:22 PM PDT 24
Finished Aug 07 07:42:43 PM PDT 24
Peak memory 264012 kb
Host smart-5ca43015-af55-4acb-a4b6-da156f1ee79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490588313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.490588313
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.126168294
Short name T751
Test name
Test status
Simulation time 25764300 ps
CPU time 76.7 seconds
Started Aug 07 07:41:20 PM PDT 24
Finished Aug 07 07:42:36 PM PDT 24
Peak memory 275692 kb
Host smart-9fed7773-a033-4133-ba19-011512443f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126168294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.126168294
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.236631126
Short name T678
Test name
Test status
Simulation time 41848000 ps
CPU time 13.74 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:41:54 PM PDT 24
Peak memory 258500 kb
Host smart-7b7ceb55-30a0-4bce-a090-217ef28b2c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236631126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.236631126
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3055377008
Short name T438
Test name
Test status
Simulation time 50738700 ps
CPU time 16.2 seconds
Started Aug 07 07:41:31 PM PDT 24
Finished Aug 07 07:41:47 PM PDT 24
Peak memory 284684 kb
Host smart-7905996d-50ca-4942-8244-3b4d1feff336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055377008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3055377008
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2331566094
Short name T539
Test name
Test status
Simulation time 29840200 ps
CPU time 21.02 seconds
Started Aug 07 07:41:30 PM PDT 24
Finished Aug 07 07:41:51 PM PDT 24
Peak memory 273868 kb
Host smart-a104b96a-3be9-4033-a243-80cb27deb6a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331566094 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2331566094
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2013635948
Short name T657
Test name
Test status
Simulation time 3300765200 ps
CPU time 64.01 seconds
Started Aug 07 07:41:22 PM PDT 24
Finished Aug 07 07:42:26 PM PDT 24
Peak memory 260760 kb
Host smart-7a2d60e8-9549-41b7-b91e-50701d137ef9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013635948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.2013635948
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.3251463580
Short name T36
Test name
Test status
Simulation time 1812508000 ps
CPU time 250.74 seconds
Started Aug 07 07:41:28 PM PDT 24
Finished Aug 07 07:45:39 PM PDT 24
Peak memory 285476 kb
Host smart-cd00aff5-6d41-4799-bc9c-9c85d5719219
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251463580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.3251463580
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3127027138
Short name T577
Test name
Test status
Simulation time 15928326100 ps
CPU time 247.92 seconds
Started Aug 07 07:41:30 PM PDT 24
Finished Aug 07 07:45:38 PM PDT 24
Peak memory 285640 kb
Host smart-70b15051-ab57-47f0-903a-eb6f9af41aea
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127027138 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.3127027138
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2003833115
Short name T979
Test name
Test status
Simulation time 169965000 ps
CPU time 131.11 seconds
Started Aug 07 07:41:20 PM PDT 24
Finished Aug 07 07:43:31 PM PDT 24
Peak memory 265324 kb
Host smart-c0d4ee92-1613-4d98-afe3-9a723434b2ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003833115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2003833115
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.3759456353
Short name T529
Test name
Test status
Simulation time 76318400 ps
CPU time 32.07 seconds
Started Aug 07 07:41:31 PM PDT 24
Finished Aug 07 07:42:03 PM PDT 24
Peak memory 273908 kb
Host smart-0bc80fc2-13af-4b5e-8d45-4065817064c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759456353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.3759456353
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1853439881
Short name T22
Test name
Test status
Simulation time 27698600 ps
CPU time 31.28 seconds
Started Aug 07 07:41:31 PM PDT 24
Finished Aug 07 07:42:02 PM PDT 24
Peak memory 273912 kb
Host smart-83d84e34-143d-4426-bd32-95db4ee5d41d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853439881 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1853439881
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.3748084380
Short name T896
Test name
Test status
Simulation time 1439902900 ps
CPU time 75.74 seconds
Started Aug 07 07:41:32 PM PDT 24
Finished Aug 07 07:42:48 PM PDT 24
Peak memory 264004 kb
Host smart-e284bf83-65bb-4cf1-a331-6a528ad94f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748084380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3748084380
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.4195603999
Short name T593
Test name
Test status
Simulation time 51434000 ps
CPU time 198.3 seconds
Started Aug 07 07:41:20 PM PDT 24
Finished Aug 07 07:44:39 PM PDT 24
Peak memory 280268 kb
Host smart-5e6c86b7-5c3f-416a-9d8f-ebada1e55bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195603999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.4195603999
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.313638603
Short name T934
Test name
Test status
Simulation time 343377900 ps
CPU time 14.22 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:41:55 PM PDT 24
Peak memory 258412 kb
Host smart-d9314e07-c5c7-48f1-876d-92c0dfbae49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313638603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.313638603
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2405169967
Short name T1036
Test name
Test status
Simulation time 27731200 ps
CPU time 15.96 seconds
Started Aug 07 07:41:38 PM PDT 24
Finished Aug 07 07:41:54 PM PDT 24
Peak memory 284652 kb
Host smart-f73cbda3-aaa0-4c3f-825c-82cfad574f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405169967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2405169967
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.1638650965
Short name T579
Test name
Test status
Simulation time 36901100 ps
CPU time 22.7 seconds
Started Aug 07 07:41:31 PM PDT 24
Finished Aug 07 07:41:54 PM PDT 24
Peak memory 265816 kb
Host smart-472ebcbf-fd4e-4572-ab47-b4e58d3cb139
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638650965 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.1638650965
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2155740648
Short name T903
Test name
Test status
Simulation time 2078198700 ps
CPU time 121.8 seconds
Started Aug 07 07:41:30 PM PDT 24
Finished Aug 07 07:43:32 PM PDT 24
Peak memory 261032 kb
Host smart-76c14600-2ec7-44e9-9fc3-3256f648d61f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155740648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2155740648
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.928901560
Short name T777
Test name
Test status
Simulation time 699060100 ps
CPU time 166.14 seconds
Started Aug 07 07:41:30 PM PDT 24
Finished Aug 07 07:44:17 PM PDT 24
Peak memory 294568 kb
Host smart-b6343756-1839-49e5-bdcb-459268ef7e26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928901560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.928901560
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.520651032
Short name T972
Test name
Test status
Simulation time 11903313300 ps
CPU time 322.47 seconds
Started Aug 07 07:41:32 PM PDT 24
Finished Aug 07 07:46:54 PM PDT 24
Peak memory 285488 kb
Host smart-dd6b6492-9fc9-464a-a1f1-32e2c994f929
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520651032 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.520651032
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.22352727
Short name T177
Test name
Test status
Simulation time 140324600 ps
CPU time 114.09 seconds
Started Aug 07 07:41:31 PM PDT 24
Finished Aug 07 07:43:25 PM PDT 24
Peak memory 263112 kb
Host smart-71a3dd34-5d3e-407d-b8c1-77ca5dd2dda3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22352727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp
_reset.22352727
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.416099177
Short name T615
Test name
Test status
Simulation time 132581500 ps
CPU time 31.42 seconds
Started Aug 07 07:41:32 PM PDT 24
Finished Aug 07 07:42:03 PM PDT 24
Peak memory 273892 kb
Host smart-d15f59de-6ae4-498f-beb5-4a65b07d8241
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416099177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_rw_evict.416099177
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.2822242565
Short name T395
Test name
Test status
Simulation time 9024854500 ps
CPU time 84.33 seconds
Started Aug 07 07:41:30 PM PDT 24
Finished Aug 07 07:42:54 PM PDT 24
Peak memory 262416 kb
Host smart-131cd052-f5ae-4e82-9203-6a5fd699ced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822242565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2822242565
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.213075595
Short name T225
Test name
Test status
Simulation time 96561900 ps
CPU time 77.04 seconds
Started Aug 07 07:41:31 PM PDT 24
Finished Aug 07 07:42:48 PM PDT 24
Peak memory 275976 kb
Host smart-eec1d183-6d6c-4d70-aae2-1deaf33df3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213075595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.213075595
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.2855131911
Short name T816
Test name
Test status
Simulation time 58963200 ps
CPU time 13.65 seconds
Started Aug 07 07:41:39 PM PDT 24
Finished Aug 07 07:41:53 PM PDT 24
Peak memory 258384 kb
Host smart-68c787bb-dc39-4924-aa33-7bf6c1fa7909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855131911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
2855131911
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.1895603674
Short name T708
Test name
Test status
Simulation time 16455000 ps
CPU time 13.57 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:41:55 PM PDT 24
Peak memory 284776 kb
Host smart-1b81b410-23ed-4a39-8f4e-5ad753e63ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895603674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.1895603674
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2484654031
Short name T852
Test name
Test status
Simulation time 2000045300 ps
CPU time 76.25 seconds
Started Aug 07 07:41:39 PM PDT 24
Finished Aug 07 07:42:56 PM PDT 24
Peak memory 262976 kb
Host smart-f00e1a4b-daf8-40fb-b07e-9041940534b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484654031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.2484654031
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.910970314
Short name T319
Test name
Test status
Simulation time 12710976100 ps
CPU time 358.5 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:47:39 PM PDT 24
Peak memory 285484 kb
Host smart-59f35c12-24d8-4ca9-b4df-bb8e940b6654
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910970314 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.910970314
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.1193443009
Short name T1110
Test name
Test status
Simulation time 51386000 ps
CPU time 110.15 seconds
Started Aug 07 07:41:45 PM PDT 24
Finished Aug 07 07:43:35 PM PDT 24
Peak memory 260076 kb
Host smart-eb0ec5a5-9735-476a-bec9-76ee4ff0221d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193443009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.1193443009
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1373717803
Short name T922
Test name
Test status
Simulation time 1454482100 ps
CPU time 68.44 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:42:49 PM PDT 24
Peak memory 263372 kb
Host smart-ae77e7b1-2b8f-4c3c-b3db-f0cd2ba997d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373717803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1373717803
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.759473282
Short name T1038
Test name
Test status
Simulation time 309869700 ps
CPU time 176 seconds
Started Aug 07 07:41:39 PM PDT 24
Finished Aug 07 07:44:35 PM PDT 24
Peak memory 277288 kb
Host smart-a84242d2-9ccb-41a3-8b70-890375ac12af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759473282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.759473282
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2023250300
Short name T944
Test name
Test status
Simulation time 37229300 ps
CPU time 13.65 seconds
Started Aug 07 07:41:39 PM PDT 24
Finished Aug 07 07:41:53 PM PDT 24
Peak memory 265380 kb
Host smart-b49b64bd-b0de-4bc1-b1c4-b62d868a0051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023250300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2023250300
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.2152642427
Short name T510
Test name
Test status
Simulation time 27060600 ps
CPU time 15.97 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:41:57 PM PDT 24
Peak memory 283352 kb
Host smart-521a7292-6845-4b6a-b12a-f26ea194bee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152642427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2152642427
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.1605173444
Short name T371
Test name
Test status
Simulation time 14986700 ps
CPU time 21.08 seconds
Started Aug 07 07:41:44 PM PDT 24
Finished Aug 07 07:42:05 PM PDT 24
Peak memory 273808 kb
Host smart-fd820a33-3aa2-4615-9a07-cab072558d67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605173444 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.1605173444
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.3462917275
Short name T1115
Test name
Test status
Simulation time 2446852000 ps
CPU time 89.09 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:43:10 PM PDT 24
Peak memory 263512 kb
Host smart-f46ce4d1-f37e-41f2-93f3-45942140cf4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462917275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.3462917275
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.932024751
Short name T589
Test name
Test status
Simulation time 17135547000 ps
CPU time 184.27 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:44:45 PM PDT 24
Peak memory 291224 kb
Host smart-664f7e5d-11c6-4cf5-9655-e22f763d6ae8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932024751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas
h_ctrl_intr_rd.932024751
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.349565050
Short name T316
Test name
Test status
Simulation time 87733094800 ps
CPU time 545.33 seconds
Started Aug 07 07:41:44 PM PDT 24
Finished Aug 07 07:50:49 PM PDT 24
Peak memory 292376 kb
Host smart-3f4e5d62-44ff-45e6-af56-f3712a42592f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349565050 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.349565050
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2638944737
Short name T505
Test name
Test status
Simulation time 542486200 ps
CPU time 134.76 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:43:55 PM PDT 24
Peak memory 265304 kb
Host smart-cad3530f-3088-4a9c-b6a2-8a2b977a1381
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638944737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2638944737
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2763789
Short name T117
Test name
Test status
Simulation time 31458000 ps
CPU time 31.57 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:42:12 PM PDT 24
Peak memory 273892 kb
Host smart-f0d0d9fb-356d-4404-885e-d0a363adf9a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash
_ctrl_rw_evict.2763789
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2986697341
Short name T475
Test name
Test status
Simulation time 65285600 ps
CPU time 31.05 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:42:12 PM PDT 24
Peak memory 273848 kb
Host smart-4bb2b6a5-7490-4cc9-ad37-b144c63a2d1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986697341 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2986697341
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3275520213
Short name T719
Test name
Test status
Simulation time 1482613100 ps
CPU time 71.78 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:42:53 PM PDT 24
Peak memory 263848 kb
Host smart-0b040375-cda2-4ec1-b7e3-c2c2f4423cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275520213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3275520213
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.3690160306
Short name T958
Test name
Test status
Simulation time 28558100 ps
CPU time 99.72 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:43:20 PM PDT 24
Peak memory 276256 kb
Host smart-e3e3102f-a03d-481c-8d69-fef87ad22405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690160306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3690160306
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2707815987
Short name T1052
Test name
Test status
Simulation time 138682700 ps
CPU time 14.04 seconds
Started Aug 07 07:41:49 PM PDT 24
Finished Aug 07 07:42:03 PM PDT 24
Peak memory 258304 kb
Host smart-4fa77da5-e8bf-4304-9ecc-1ba9c68f46dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707815987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2707815987
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.2652659559
Short name T901
Test name
Test status
Simulation time 67397500 ps
CPU time 15.91 seconds
Started Aug 07 07:41:48 PM PDT 24
Finished Aug 07 07:42:04 PM PDT 24
Peak memory 284740 kb
Host smart-f73ed042-85e5-414b-b181-4dcac6bf69b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652659559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2652659559
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.157743620
Short name T605
Test name
Test status
Simulation time 38278900 ps
CPU time 20.77 seconds
Started Aug 07 07:41:50 PM PDT 24
Finished Aug 07 07:42:10 PM PDT 24
Peak memory 273788 kb
Host smart-ce4d707e-4651-44d1-b2a2-e470908ee8c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157743620 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.157743620
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.4125347359
Short name T836
Test name
Test status
Simulation time 10978065300 ps
CPU time 127.39 seconds
Started Aug 07 07:41:41 PM PDT 24
Finished Aug 07 07:43:49 PM PDT 24
Peak memory 262332 kb
Host smart-f8ebb1c2-b309-42b9-ae09-edee40c4cf99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125347359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.4125347359
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.715880787
Short name T587
Test name
Test status
Simulation time 1437455400 ps
CPU time 171.75 seconds
Started Aug 07 07:41:48 PM PDT 24
Finished Aug 07 07:44:40 PM PDT 24
Peak memory 291936 kb
Host smart-48e4e368-4b5c-4011-b3e7-e9fb19bcd0b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715880787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas
h_ctrl_intr_rd.715880787
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3727318780
Short name T638
Test name
Test status
Simulation time 9309382400 ps
CPU time 246.9 seconds
Started Aug 07 07:41:48 PM PDT 24
Finished Aug 07 07:45:55 PM PDT 24
Peak memory 291484 kb
Host smart-4b80167d-58f8-4fdc-b6e6-68f2f07d9fb9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727318780 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.3727318780
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.4012716902
Short name T808
Test name
Test status
Simulation time 75592100 ps
CPU time 116.12 seconds
Started Aug 07 07:41:43 PM PDT 24
Finished Aug 07 07:43:39 PM PDT 24
Peak memory 260304 kb
Host smart-b7ad67ff-9444-4926-a8cd-25ba36b0f03d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012716902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.4012716902
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.3090195282
Short name T345
Test name
Test status
Simulation time 28142500 ps
CPU time 31.39 seconds
Started Aug 07 07:41:49 PM PDT 24
Finished Aug 07 07:42:20 PM PDT 24
Peak memory 274824 kb
Host smart-ad492f7e-326e-417e-9d05-8e2f52dd2356
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090195282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.3090195282
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.3858617885
Short name T1006
Test name
Test status
Simulation time 1590352800 ps
CPU time 77.96 seconds
Started Aug 07 07:41:49 PM PDT 24
Finished Aug 07 07:43:07 PM PDT 24
Peak memory 263956 kb
Host smart-ff7d242e-0a84-4cd6-b0ba-2e9740c369e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858617885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.3858617885
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.1425086283
Short name T455
Test name
Test status
Simulation time 250161000 ps
CPU time 173 seconds
Started Aug 07 07:41:40 PM PDT 24
Finished Aug 07 07:44:33 PM PDT 24
Peak memory 279632 kb
Host smart-33100325-b97a-4240-9b69-833355c644ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425086283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1425086283
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.234513093
Short name T636
Test name
Test status
Simulation time 49965500 ps
CPU time 14.02 seconds
Started Aug 07 07:41:58 PM PDT 24
Finished Aug 07 07:42:12 PM PDT 24
Peak memory 258348 kb
Host smart-290eda28-d202-4e36-9d6b-3030c0491101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234513093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.234513093
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.2790134477
Short name T423
Test name
Test status
Simulation time 38117600 ps
CPU time 15.89 seconds
Started Aug 07 07:41:58 PM PDT 24
Finished Aug 07 07:42:14 PM PDT 24
Peak memory 284676 kb
Host smart-4df80352-9278-4caf-9f1b-49113f85012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790134477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2790134477
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.3173220737
Short name T523
Test name
Test status
Simulation time 20343600 ps
CPU time 22.53 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:42:20 PM PDT 24
Peak memory 273844 kb
Host smart-35a7d14e-c914-48c6-b785-7f42d0a3c1ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173220737 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.3173220737
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3553852353
Short name T305
Test name
Test status
Simulation time 7465239200 ps
CPU time 60.78 seconds
Started Aug 07 07:41:49 PM PDT 24
Finished Aug 07 07:42:50 PM PDT 24
Peak memory 261212 kb
Host smart-da1d6155-b2f3-43fd-99f1-19b06ab0f27a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553852353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3553852353
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.3995443994
Short name T1063
Test name
Test status
Simulation time 3844806600 ps
CPU time 126.81 seconds
Started Aug 07 07:41:49 PM PDT 24
Finished Aug 07 07:43:56 PM PDT 24
Peak memory 291288 kb
Host smart-cc6a5155-2954-4217-bfe6-4358227db248
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995443994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.3995443994
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1407078596
Short name T660
Test name
Test status
Simulation time 11338203500 ps
CPU time 130.9 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:44:08 PM PDT 24
Peak memory 293488 kb
Host smart-fddd97b6-6e69-42aa-9caf-8afa075d197e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407078596 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1407078596
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1309050731
Short name T506
Test name
Test status
Simulation time 363207800 ps
CPU time 110.74 seconds
Started Aug 07 07:41:49 PM PDT 24
Finished Aug 07 07:43:40 PM PDT 24
Peak memory 260184 kb
Host smart-5469ac34-5e64-48da-a7e8-f62f253e738c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309050731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1309050731
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.4290852099
Short name T733
Test name
Test status
Simulation time 85290300 ps
CPU time 31.85 seconds
Started Aug 07 07:41:58 PM PDT 24
Finished Aug 07 07:42:30 PM PDT 24
Peak memory 273892 kb
Host smart-608fa526-fbb2-4e75-8e3f-ec6f44203ae6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290852099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.4290852099
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1853744683
Short name T1049
Test name
Test status
Simulation time 41133600 ps
CPU time 31.49 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 273888 kb
Host smart-ed37558d-09d9-4fcf-8ffb-33dbe2f8cae9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853744683 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1853744683
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.2297441483
Short name T908
Test name
Test status
Simulation time 400945300 ps
CPU time 58.2 seconds
Started Aug 07 07:41:55 PM PDT 24
Finished Aug 07 07:42:54 PM PDT 24
Peak memory 263952 kb
Host smart-3e10e67b-f57d-4ca0-98e6-a5a0d8babb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297441483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2297441483
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.3084574491
Short name T703
Test name
Test status
Simulation time 424003600 ps
CPU time 144.78 seconds
Started Aug 07 07:41:48 PM PDT 24
Finished Aug 07 07:44:13 PM PDT 24
Peak memory 277144 kb
Host smart-cce7f6ca-6e8d-434e-a838-a2b2be81b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084574491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3084574491
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.2728292430
Short name T680
Test name
Test status
Simulation time 162231800 ps
CPU time 14.04 seconds
Started Aug 07 07:34:32 PM PDT 24
Finished Aug 07 07:34:46 PM PDT 24
Peak memory 258396 kb
Host smart-5d8b0f3d-9b6e-4740-bcc1-d59fe6342619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728292430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2
728292430
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.957381023
Short name T822
Test name
Test status
Simulation time 39862200 ps
CPU time 14.38 seconds
Started Aug 07 07:34:32 PM PDT 24
Finished Aug 07 07:34:46 PM PDT 24
Peak memory 265384 kb
Host smart-4f9844c9-c679-4be1-861e-d58e43600d76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957381023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.957381023
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1240756191
Short name T856
Test name
Test status
Simulation time 19631500 ps
CPU time 13.66 seconds
Started Aug 07 07:34:34 PM PDT 24
Finished Aug 07 07:34:47 PM PDT 24
Peak memory 283240 kb
Host smart-9f34812a-96dd-4d70-a1d1-6bf05befa1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240756191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1240756191
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.1626166618
Short name T877
Test name
Test status
Simulation time 38608200 ps
CPU time 23.2 seconds
Started Aug 07 07:34:35 PM PDT 24
Finished Aug 07 07:34:58 PM PDT 24
Peak memory 273844 kb
Host smart-6ea960c5-56f6-4717-9e44-59fb1399260f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626166618 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.1626166618
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2298918538
Short name T143
Test name
Test status
Simulation time 8778536700 ps
CPU time 2511.9 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 08:15:52 PM PDT 24
Peak memory 263176 kb
Host smart-4d984033-c0bd-4e57-8f18-212cf4b1810d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2298918538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.2298918538
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.4046157228
Short name T84
Test name
Test status
Simulation time 7968772400 ps
CPU time 2759.25 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 08:19:59 PM PDT 24
Peak memory 264116 kb
Host smart-2617456e-1381-4c46-b235-16ffbf790930
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046157228 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.4046157228
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.4170606364
Short name T631
Test name
Test status
Simulation time 359000800 ps
CPU time 943.83 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 07:49:43 PM PDT 24
Peak memory 273156 kb
Host smart-820b6b36-a6f3-4bbe-aea0-bdf5197c4fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170606364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.4170606364
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.154493143
Short name T53
Test name
Test status
Simulation time 150200000 ps
CPU time 24.46 seconds
Started Aug 07 07:33:58 PM PDT 24
Finished Aug 07 07:34:23 PM PDT 24
Peak memory 263864 kb
Host smart-bda882ef-b489-4d3e-91ee-00302baa5f94
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154493143 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_fetch_code.154493143
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1768574455
Short name T1061
Test name
Test status
Simulation time 132059977900 ps
CPU time 3898.77 seconds
Started Aug 07 07:33:58 PM PDT 24
Finished Aug 07 08:38:58 PM PDT 24
Peak memory 265356 kb
Host smart-e26fd08a-4072-4339-bba7-0f2bf71b05e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768574455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1768574455
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2924951214
Short name T184
Test name
Test status
Simulation time 282970436900 ps
CPU time 3030.01 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 08:24:30 PM PDT 24
Peak memory 265436 kb
Host smart-e65fe038-edb0-4c84-8565-061aa120487d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924951214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.2924951214
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.965980447
Short name T732
Test name
Test status
Simulation time 236970400 ps
CPU time 116.97 seconds
Started Aug 07 07:33:46 PM PDT 24
Finished Aug 07 07:35:43 PM PDT 24
Peak memory 265504 kb
Host smart-bf417db0-62dd-446a-a2d8-9b584801196f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965980447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.965980447
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.4037560451
Short name T688
Test name
Test status
Simulation time 10020594800 ps
CPU time 66.7 seconds
Started Aug 07 07:34:36 PM PDT 24
Finished Aug 07 07:35:42 PM PDT 24
Peak memory 266656 kb
Host smart-d82290cf-a23f-489c-9f9e-7b4504d95dd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037560451 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.4037560451
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3065448619
Short name T1066
Test name
Test status
Simulation time 26714200 ps
CPU time 14.18 seconds
Started Aug 07 07:34:36 PM PDT 24
Finished Aug 07 07:34:50 PM PDT 24
Peak memory 258560 kb
Host smart-9aa93da7-628a-4e24-9a3c-ee2887c55875
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065448619 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3065448619
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1783037224
Short name T659
Test name
Test status
Simulation time 40127390800 ps
CPU time 861.17 seconds
Started Aug 07 07:34:00 PM PDT 24
Finished Aug 07 07:48:21 PM PDT 24
Peak memory 264104 kb
Host smart-2bc47c17-1caf-498a-b0e4-5987d5ce000c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783037224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.1783037224
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.591135823
Short name T848
Test name
Test status
Simulation time 1096081300 ps
CPU time 32.09 seconds
Started Aug 07 07:33:45 PM PDT 24
Finished Aug 07 07:34:17 PM PDT 24
Peak memory 263260 kb
Host smart-5f2af1a3-fcf7-49ae-815b-55df7ed53d00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591135823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw
_sec_otp.591135823
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3236718934
Short name T585
Test name
Test status
Simulation time 7994909900 ps
CPU time 684.7 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:45:40 PM PDT 24
Peak memory 323468 kb
Host smart-d57bda77-bb22-42fd-88be-2c98791416fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236718934 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3236718934
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.3226543808
Short name T33
Test name
Test status
Simulation time 720651200 ps
CPU time 140.9 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:36:36 PM PDT 24
Peak memory 291268 kb
Host smart-4f2c699a-9fca-4f63-bb27-9f0c18207514
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226543808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.3226543808
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.105240713
Short name T1109
Test name
Test status
Simulation time 65390227300 ps
CPU time 364.11 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:40:19 PM PDT 24
Peak memory 285412 kb
Host smart-38dd9b2a-01b6-4b84-a8e6-b01e51365aa3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105240713 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.105240713
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.3109555460
Short name T458
Test name
Test status
Simulation time 2924296500 ps
CPU time 75.37 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:35:30 PM PDT 24
Peak memory 265504 kb
Host smart-2ecd45ca-43d3-4007-83ba-e08c533c66c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109555460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.3109555460
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3654099434
Short name T578
Test name
Test status
Simulation time 35803724000 ps
CPU time 176.65 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:37:12 PM PDT 24
Peak memory 260384 kb
Host smart-8c5bdb13-feee-4e6f-8e34-0f6a80ef8285
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365
4099434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3654099434
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.3673158805
Short name T131
Test name
Test status
Simulation time 1957692400 ps
CPU time 68.28 seconds
Started Aug 07 07:34:00 PM PDT 24
Finished Aug 07 07:35:09 PM PDT 24
Peak memory 263660 kb
Host smart-06398345-c73c-4bf8-a45b-cda015da3b35
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673158805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3673158805
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.221204536
Short name T169
Test name
Test status
Simulation time 47605200 ps
CPU time 13.62 seconds
Started Aug 07 07:34:32 PM PDT 24
Finished Aug 07 07:34:46 PM PDT 24
Peak memory 265056 kb
Host smart-69c48aa0-c97f-40b5-b374-e9cd2fa8cc00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221204536 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.221204536
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.1676437785
Short name T91
Test name
Test status
Simulation time 5660326800 ps
CPU time 75.13 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 07:35:14 PM PDT 24
Peak memory 260752 kb
Host smart-df1a40bd-2d14-4cde-9314-6a3c40243294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676437785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1676437785
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.193164086
Short name T801
Test name
Test status
Simulation time 26717839900 ps
CPU time 352.07 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 07:39:51 PM PDT 24
Peak memory 275924 kb
Host smart-e3e02adb-3573-4d33-a57f-d1ca58f7896b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193164086 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.193164086
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1250343297
Short name T69
Test name
Test status
Simulation time 41550600 ps
CPU time 132.89 seconds
Started Aug 07 07:33:58 PM PDT 24
Finished Aug 07 07:36:11 PM PDT 24
Peak memory 260220 kb
Host smart-6a239a20-473f-4bb2-83f6-595f300e808f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250343297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1250343297
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.1434617534
Short name T1050
Test name
Test status
Simulation time 5556116700 ps
CPU time 199.5 seconds
Started Aug 07 07:34:18 PM PDT 24
Finished Aug 07 07:37:37 PM PDT 24
Peak memory 282144 kb
Host smart-131e174f-3e36-4f28-bc3f-128eeabecc32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434617534 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.1434617534
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2645123950
Short name T200
Test name
Test status
Simulation time 26320100 ps
CPU time 14.01 seconds
Started Aug 07 07:34:31 PM PDT 24
Finished Aug 07 07:34:45 PM PDT 24
Peak memory 261704 kb
Host smart-e564260a-1e3e-416d-ab7d-a8de9ddb6d55
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2645123950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2645123950
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.2983166794
Short name T621
Test name
Test status
Simulation time 180127900 ps
CPU time 364.16 seconds
Started Aug 07 07:33:46 PM PDT 24
Finished Aug 07 07:39:50 PM PDT 24
Peak memory 263532 kb
Host smart-b1bfa9a4-4ca6-453d-96d9-91012c795a7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983166794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2983166794
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1147837530
Short name T152
Test name
Test status
Simulation time 776668700 ps
CPU time 18.23 seconds
Started Aug 07 07:34:31 PM PDT 24
Finished Aug 07 07:34:49 PM PDT 24
Peak memory 265788 kb
Host smart-67983a8d-7ecb-4578-ad93-9ad91218a7f4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147837530 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1147837530
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2232247856
Short name T14
Test name
Test status
Simulation time 27224400 ps
CPU time 13.6 seconds
Started Aug 07 07:34:31 PM PDT 24
Finished Aug 07 07:34:44 PM PDT 24
Peak memory 265756 kb
Host smart-4fc55887-2d06-4b64-bb60-b89ed34c92e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232247856 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2232247856
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.2429753616
Short name T893
Test name
Test status
Simulation time 64284000 ps
CPU time 13.69 seconds
Started Aug 07 07:34:16 PM PDT 24
Finished Aug 07 07:34:30 PM PDT 24
Peak memory 265304 kb
Host smart-e254c251-2ce8-4154-be57-da9e4ae36f01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429753616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.flash_ctrl_prog_reset.2429753616
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.2918993436
Short name T624
Test name
Test status
Simulation time 793138500 ps
CPU time 515.41 seconds
Started Aug 07 07:33:46 PM PDT 24
Finished Aug 07 07:42:21 PM PDT 24
Peak memory 283036 kb
Host smart-54135c05-5412-4f86-8f9d-bea50ee19a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918993436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2918993436
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1923771640
Short name T665
Test name
Test status
Simulation time 8057726000 ps
CPU time 121.11 seconds
Started Aug 07 07:33:46 PM PDT 24
Finished Aug 07 07:35:47 PM PDT 24
Peak memory 263000 kb
Host smart-2fb89bcd-ef25-442c-ad26-80727abd8694
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1923771640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1923771640
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.2127596789
Short name T1021
Test name
Test status
Simulation time 713444000 ps
CPU time 34.68 seconds
Started Aug 07 07:34:30 PM PDT 24
Finished Aug 07 07:35:05 PM PDT 24
Peak memory 273844 kb
Host smart-2395f1f0-7609-4526-b0ed-393785b530b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127596789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.2127596789
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.2166959662
Short name T1009
Test name
Test status
Simulation time 18398900 ps
CPU time 23.16 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:34:38 PM PDT 24
Peak memory 265244 kb
Host smart-ba56d83b-e1f2-4e2a-964f-5c591ce4423b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166959662 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.2166959662
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.1922258814
Short name T626
Test name
Test status
Simulation time 77210600 ps
CPU time 22.61 seconds
Started Aug 07 07:33:58 PM PDT 24
Finished Aug 07 07:34:21 PM PDT 24
Peak memory 265636 kb
Host smart-8e1ff386-c1a9-4556-b887-a2a066c18bf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922258814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.1922258814
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.809587734
Short name T551
Test name
Test status
Simulation time 550214200 ps
CPU time 113.46 seconds
Started Aug 07 07:34:01 PM PDT 24
Finished Aug 07 07:35:54 PM PDT 24
Peak memory 282112 kb
Host smart-cf59463e-4bc2-4a6a-8dca-d8479439e589
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809587734 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_ro.809587734
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.2954831512
Short name T642
Test name
Test status
Simulation time 728334600 ps
CPU time 175.6 seconds
Started Aug 07 07:34:05 PM PDT 24
Finished Aug 07 07:37:01 PM PDT 24
Peak memory 282120 kb
Host smart-8c12bea6-829c-45c4-9443-7c5455cbc7ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2954831512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2954831512
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1677238737
Short name T561
Test name
Test status
Simulation time 1210513200 ps
CPU time 121.43 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:36:17 PM PDT 24
Peak memory 295444 kb
Host smart-001425e7-fead-4cdf-8e47-b18e1fca90b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677238737 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1677238737
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.2889494838
Short name T713
Test name
Test status
Simulation time 19256661300 ps
CPU time 684.66 seconds
Started Aug 07 07:34:00 PM PDT 24
Finished Aug 07 07:45:25 PM PDT 24
Peak memory 310292 kb
Host smart-b5ed6d04-601d-4b2a-a8e4-1a31b73e1eed
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889494838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.2889494838
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.3849617612
Short name T201
Test name
Test status
Simulation time 5698181200 ps
CPU time 231.24 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:38:06 PM PDT 24
Peak memory 295528 kb
Host smart-16f92c58-a754-4866-adc1-0907c5bd2da7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849617612 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.flash_ctrl_rw_serr.3849617612
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.4093726415
Short name T62
Test name
Test status
Simulation time 22114392100 ps
CPU time 4941.21 seconds
Started Aug 07 07:34:30 PM PDT 24
Finished Aug 07 08:56:52 PM PDT 24
Peak memory 287216 kb
Host smart-01283047-bbff-42b9-8f1f-7545a5828c9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093726415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.4093726415
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.2142753626
Short name T390
Test name
Test status
Simulation time 2391550500 ps
CPU time 75.27 seconds
Started Aug 07 07:34:33 PM PDT 24
Finished Aug 07 07:35:49 PM PDT 24
Peak memory 263988 kb
Host smart-9230bab2-dcdf-44f8-beb0-8b556d80bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142753626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2142753626
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.869593850
Short name T746
Test name
Test status
Simulation time 1056593100 ps
CPU time 92.75 seconds
Started Aug 07 07:34:15 PM PDT 24
Finished Aug 07 07:35:48 PM PDT 24
Peak memory 265664 kb
Host smart-14e4452b-8b1c-4fdc-abd1-63e378b8ee3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869593850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_serr_address.869593850
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.2745591834
Short name T608
Test name
Test status
Simulation time 13623073400 ps
CPU time 93.74 seconds
Started Aug 07 07:34:16 PM PDT 24
Finished Aug 07 07:35:50 PM PDT 24
Peak memory 273940 kb
Host smart-61434010-e88b-42ba-afc3-82066808c800
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745591834 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.2745591834
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.2465790881
Short name T504
Test name
Test status
Simulation time 23266400 ps
CPU time 101.6 seconds
Started Aug 07 07:33:47 PM PDT 24
Finished Aug 07 07:35:28 PM PDT 24
Peak memory 277492 kb
Host smart-e65bc471-bc51-49f0-9fe6-14f822495c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465790881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2465790881
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.4199299481
Short name T598
Test name
Test status
Simulation time 29221100 ps
CPU time 26.6 seconds
Started Aug 07 07:33:49 PM PDT 24
Finished Aug 07 07:34:16 PM PDT 24
Peak memory 259932 kb
Host smart-5dfdb130-56d7-4663-a60f-ae512ede3cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199299481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.4199299481
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.755683318
Short name T483
Test name
Test status
Simulation time 88255900 ps
CPU time 229.2 seconds
Started Aug 07 07:34:31 PM PDT 24
Finished Aug 07 07:38:20 PM PDT 24
Peak memory 271572 kb
Host smart-99ddf304-3b0b-4424-be98-cfcca51850df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755683318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress
_all.755683318
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2864288123
Short name T741
Test name
Test status
Simulation time 44501000 ps
CPU time 24.13 seconds
Started Aug 07 07:33:48 PM PDT 24
Finished Aug 07 07:34:12 PM PDT 24
Peak memory 259884 kb
Host smart-314b119c-8181-4019-9147-d3a1cba28f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864288123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2864288123
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.398446950
Short name T135
Test name
Test status
Simulation time 3041878100 ps
CPU time 223.82 seconds
Started Aug 07 07:33:59 PM PDT 24
Finished Aug 07 07:37:43 PM PDT 24
Peak memory 260296 kb
Host smart-40c3f44d-d4d0-402e-81db-449c4e1e1750
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398446950 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_wo.398446950
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.2976658777
Short name T960
Test name
Test status
Simulation time 21280300 ps
CPU time 14.01 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:42:11 PM PDT 24
Peak memory 258436 kb
Host smart-408eba42-55ed-4ccd-8aa2-46479e37ef1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976658777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
2976658777
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3730717235
Short name T915
Test name
Test status
Simulation time 50416500 ps
CPU time 16.32 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:42:14 PM PDT 24
Peak memory 275292 kb
Host smart-c6597829-e152-4598-ba71-ad63dc20a036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730717235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3730717235
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3428572137
Short name T363
Test name
Test status
Simulation time 10746300 ps
CPU time 22.19 seconds
Started Aug 07 07:41:58 PM PDT 24
Finished Aug 07 07:42:20 PM PDT 24
Peak memory 273832 kb
Host smart-ee4255c6-05bd-40c1-b0ba-5fc4eea2d031
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428572137 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3428572137
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.4184272554
Short name T1097
Test name
Test status
Simulation time 3656224500 ps
CPU time 155.66 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:44:33 PM PDT 24
Peak memory 261156 kb
Host smart-7dcb5cfd-c2b0-47bf-8202-ae419346708b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184272554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.4184272554
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.1749996234
Short name T72
Test name
Test status
Simulation time 77744000 ps
CPU time 110.6 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:43:48 PM PDT 24
Peak memory 260364 kb
Host smart-ad8e169b-a577-4c31-b566-2388f0edd80c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749996234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.1749996234
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.3165401230
Short name T758
Test name
Test status
Simulation time 4657624100 ps
CPU time 59.63 seconds
Started Aug 07 07:41:56 PM PDT 24
Finished Aug 07 07:42:56 PM PDT 24
Peak memory 263868 kb
Host smart-37315370-ca17-4e70-9632-6c3f64ca178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165401230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3165401230
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.1275342474
Short name T892
Test name
Test status
Simulation time 27515000 ps
CPU time 75.91 seconds
Started Aug 07 07:41:57 PM PDT 24
Finished Aug 07 07:43:13 PM PDT 24
Peak memory 276784 kb
Host smart-ac383e2d-b796-4fe4-b922-537983ca5c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275342474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1275342474
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.707070020
Short name T768
Test name
Test status
Simulation time 245490800 ps
CPU time 13.67 seconds
Started Aug 07 07:42:07 PM PDT 24
Finished Aug 07 07:42:21 PM PDT 24
Peak memory 258528 kb
Host smart-81ed0386-c8ee-43f4-b170-744371367214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707070020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.707070020
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.1125332554
Short name T770
Test name
Test status
Simulation time 15894200 ps
CPU time 15.89 seconds
Started Aug 07 07:42:06 PM PDT 24
Finished Aug 07 07:42:22 PM PDT 24
Peak memory 284744 kb
Host smart-aaf69d33-cdf5-4969-a6a6-58e5019e167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125332554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1125332554
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.1545873917
Short name T370
Test name
Test status
Simulation time 30384900 ps
CPU time 21.24 seconds
Started Aug 07 07:42:06 PM PDT 24
Finished Aug 07 07:42:27 PM PDT 24
Peak memory 273840 kb
Host smart-254d32f1-792c-4815-8a91-3414ea429a47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545873917 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.1545873917
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.637934988
Short name T1114
Test name
Test status
Simulation time 2034224400 ps
CPU time 83.14 seconds
Started Aug 07 07:42:05 PM PDT 24
Finished Aug 07 07:43:29 PM PDT 24
Peak memory 263316 kb
Host smart-51c969af-3b8d-4a68-a45c-db153772cbdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637934988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.637934988
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2147767382
Short name T1065
Test name
Test status
Simulation time 80338700 ps
CPU time 134.19 seconds
Started Aug 07 07:42:07 PM PDT 24
Finished Aug 07 07:44:21 PM PDT 24
Peak memory 260256 kb
Host smart-936d0c6e-bc57-47cf-80c7-454e9f0394e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147767382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2147767382
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.3255136696
Short name T397
Test name
Test status
Simulation time 8844942100 ps
CPU time 81.61 seconds
Started Aug 07 07:42:07 PM PDT 24
Finished Aug 07 07:43:29 PM PDT 24
Peak memory 260136 kb
Host smart-aec24659-9ab6-495e-8bde-69bbc820681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255136696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3255136696
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.4225774580
Short name T545
Test name
Test status
Simulation time 28020800 ps
CPU time 122.14 seconds
Started Aug 07 07:42:09 PM PDT 24
Finished Aug 07 07:44:11 PM PDT 24
Peak memory 277648 kb
Host smart-a1fd4672-a29f-4be0-92d6-e69f291cff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225774580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.4225774580
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.2228518826
Short name T94
Test name
Test status
Simulation time 86973000 ps
CPU time 14.43 seconds
Started Aug 07 07:42:14 PM PDT 24
Finished Aug 07 07:42:29 PM PDT 24
Peak memory 258304 kb
Host smart-b4cf0d23-8f7f-42c2-bc7a-36ca837a717c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228518826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
2228518826
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.2191583560
Short name T610
Test name
Test status
Simulation time 43990000 ps
CPU time 13.39 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 284560 kb
Host smart-b665304b-0563-4216-8e80-e8dbde6771ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191583560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2191583560
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.324460629
Short name T693
Test name
Test status
Simulation time 38800200 ps
CPU time 22.36 seconds
Started Aug 07 07:42:06 PM PDT 24
Finished Aug 07 07:42:29 PM PDT 24
Peak memory 274152 kb
Host smart-58724300-1cbb-4c41-b3ea-7683dc2537c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324460629 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.324460629
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2828183905
Short name T734
Test name
Test status
Simulation time 2871416800 ps
CPU time 75.13 seconds
Started Aug 07 07:42:06 PM PDT 24
Finished Aug 07 07:43:21 PM PDT 24
Peak memory 261144 kb
Host smart-f4037f18-87a9-4fc2-a8fc-a1ea4750324b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828183905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2828183905
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2991291116
Short name T555
Test name
Test status
Simulation time 34529100 ps
CPU time 134.71 seconds
Started Aug 07 07:42:05 PM PDT 24
Finished Aug 07 07:44:20 PM PDT 24
Peak memory 264912 kb
Host smart-2c237160-0fac-410a-9c5f-b65fcc9d1575
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991291116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2991291116
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.4251092490
Short name T196
Test name
Test status
Simulation time 14273812100 ps
CPU time 98.16 seconds
Started Aug 07 07:42:06 PM PDT 24
Finished Aug 07 07:43:44 PM PDT 24
Peak memory 263968 kb
Host smart-206b15c4-4b55-43f3-9bb4-041f2c0a8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251092490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.4251092490
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.89623021
Short name T878
Test name
Test status
Simulation time 56975000 ps
CPU time 104.79 seconds
Started Aug 07 07:42:07 PM PDT 24
Finished Aug 07 07:43:52 PM PDT 24
Peak memory 276428 kb
Host smart-29655428-4c32-4a77-b242-3efcb61683cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89623021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.89623021
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.55723321
Short name T802
Test name
Test status
Simulation time 285018700 ps
CPU time 14.07 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:42:29 PM PDT 24
Peak memory 258308 kb
Host smart-a9d724f3-9252-4bad-922d-f6640b8534d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55723321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.55723321
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3668999850
Short name T738
Test name
Test status
Simulation time 29983100 ps
CPU time 13.45 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:42:28 PM PDT 24
Peak memory 284700 kb
Host smart-0b16c241-037c-4b81-94a2-79a7949be515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668999850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3668999850
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.30008270
Short name T47
Test name
Test status
Simulation time 19752900 ps
CPU time 21.13 seconds
Started Aug 07 07:42:20 PM PDT 24
Finished Aug 07 07:42:41 PM PDT 24
Peak memory 273864 kb
Host smart-e2a9f2df-66b4-4b9c-8caf-daab2d1b3362
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008270 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.flash_ctrl_disable.30008270
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.948986510
Short name T779
Test name
Test status
Simulation time 3494024900 ps
CPU time 187.54 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:45:22 PM PDT 24
Peak memory 260936 kb
Host smart-663d4360-d18f-4966-8e5a-552c2d9c9a44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948986510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.948986510
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.425668384
Short name T686
Test name
Test status
Simulation time 74405700 ps
CPU time 110.79 seconds
Started Aug 07 07:42:18 PM PDT 24
Finished Aug 07 07:44:09 PM PDT 24
Peak memory 265304 kb
Host smart-abe8a799-50bd-440c-a74a-5ee40beb6407
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425668384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ot
p_reset.425668384
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.370738904
Short name T391
Test name
Test status
Simulation time 8484651900 ps
CPU time 75.9 seconds
Started Aug 07 07:42:14 PM PDT 24
Finished Aug 07 07:43:30 PM PDT 24
Peak memory 263984 kb
Host smart-0ae57bca-6205-4d4d-98c0-984c48ab34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370738904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.370738904
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.718562556
Short name T50
Test name
Test status
Simulation time 72008600 ps
CPU time 51.65 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:43:07 PM PDT 24
Peak memory 271488 kb
Host smart-c2034951-a75f-4dfe-8975-a7863b0dd488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718562556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.718562556
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3613417941
Short name T596
Test name
Test status
Simulation time 45858100 ps
CPU time 13.92 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:42:29 PM PDT 24
Peak memory 258372 kb
Host smart-cfdd4f97-3986-4323-8437-a71af8286109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613417941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3613417941
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.466525556
Short name T1010
Test name
Test status
Simulation time 110509300 ps
CPU time 15.85 seconds
Started Aug 07 07:42:17 PM PDT 24
Finished Aug 07 07:42:33 PM PDT 24
Peak memory 284764 kb
Host smart-23a88639-10b6-4447-9d61-0d34f29eef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466525556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.466525556
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2235099716
Short name T862
Test name
Test status
Simulation time 5651494200 ps
CPU time 174.26 seconds
Started Aug 07 07:42:19 PM PDT 24
Finished Aug 07 07:45:14 PM PDT 24
Peak memory 263460 kb
Host smart-c1193b2a-42eb-4684-a105-26e381be5310
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235099716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.2235099716
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.2978046798
Short name T710
Test name
Test status
Simulation time 74274300 ps
CPU time 110.69 seconds
Started Aug 07 07:42:14 PM PDT 24
Finished Aug 07 07:44:05 PM PDT 24
Peak memory 260200 kb
Host smart-848c8867-9644-4b1d-b762-45daac8634d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978046798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.2978046798
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3455335337
Short name T383
Test name
Test status
Simulation time 2430259900 ps
CPU time 67.06 seconds
Started Aug 07 07:42:14 PM PDT 24
Finished Aug 07 07:43:21 PM PDT 24
Peak memory 265012 kb
Host smart-21f9f100-3247-4610-ae80-0aa5c6cd620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455335337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3455335337
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.3304356365
Short name T981
Test name
Test status
Simulation time 34732100 ps
CPU time 50.31 seconds
Started Aug 07 07:42:16 PM PDT 24
Finished Aug 07 07:43:06 PM PDT 24
Peak memory 271392 kb
Host smart-34fc7c87-cf83-44c3-b338-9e6dd7179a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304356365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3304356365
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.3080967257
Short name T477
Test name
Test status
Simulation time 398918900 ps
CPU time 13.74 seconds
Started Aug 07 07:42:23 PM PDT 24
Finished Aug 07 07:42:36 PM PDT 24
Peak memory 265288 kb
Host smart-0d2755d0-eea6-45c9-85f3-5b548ffffcc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080967257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
3080967257
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2700089870
Short name T842
Test name
Test status
Simulation time 56008600 ps
CPU time 15.81 seconds
Started Aug 07 07:42:26 PM PDT 24
Finished Aug 07 07:42:42 PM PDT 24
Peak memory 284820 kb
Host smart-9eef16a8-2538-4ce7-b671-94db780a87c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700089870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2700089870
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.2395105957
Short name T999
Test name
Test status
Simulation time 26440000 ps
CPU time 21.99 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:42:46 PM PDT 24
Peak memory 273848 kb
Host smart-4bf77244-17b8-482a-91d0-35502202a974
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395105957 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.2395105957
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4183773815
Short name T534
Test name
Test status
Simulation time 21265752200 ps
CPU time 147.32 seconds
Started Aug 07 07:42:16 PM PDT 24
Finished Aug 07 07:44:43 PM PDT 24
Peak memory 263476 kb
Host smart-d80d663f-aefd-418e-83fb-0873934b9fad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183773815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.4183773815
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.2924146916
Short name T676
Test name
Test status
Simulation time 42018400 ps
CPU time 134.09 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:44:29 PM PDT 24
Peak memory 261192 kb
Host smart-ebc7f16a-35d4-4fed-aaa8-08552a272383
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924146916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.2924146916
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.3794752206
Short name T378
Test name
Test status
Simulation time 6276421100 ps
CPU time 89.15 seconds
Started Aug 07 07:42:23 PM PDT 24
Finished Aug 07 07:43:52 PM PDT 24
Peak memory 263928 kb
Host smart-86c1630d-f380-4611-a3ad-2475ea7b9d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794752206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3794752206
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.404637966
Short name T1025
Test name
Test status
Simulation time 98472500 ps
CPU time 99.56 seconds
Started Aug 07 07:42:15 PM PDT 24
Finished Aug 07 07:43:55 PM PDT 24
Peak memory 276232 kb
Host smart-7c60b5d0-7261-4143-a7ec-d606a453e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404637966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.404637966
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3245160072
Short name T952
Test name
Test status
Simulation time 19141600 ps
CPU time 13.62 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:42:38 PM PDT 24
Peak memory 265328 kb
Host smart-c92ef42e-c372-4419-b9a6-ff8c2668baef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245160072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3245160072
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.5771494
Short name T550
Test name
Test status
Simulation time 24249600 ps
CPU time 16.09 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:42:40 PM PDT 24
Peak memory 284700 kb
Host smart-8de67bc1-6d8a-4f80-ae30-c9eba89db3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5771494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.5771494
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.1062783963
Short name T364
Test name
Test status
Simulation time 18040700 ps
CPU time 22.29 seconds
Started Aug 07 07:42:25 PM PDT 24
Finished Aug 07 07:42:48 PM PDT 24
Peak memory 273832 kb
Host smart-b57c12aa-c78e-4445-8f68-4b0dc9919ee9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062783963 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.1062783963
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2077649352
Short name T413
Test name
Test status
Simulation time 2921705300 ps
CPU time 158.43 seconds
Started Aug 07 07:42:26 PM PDT 24
Finished Aug 07 07:45:05 PM PDT 24
Peak memory 261300 kb
Host smart-1092ded1-16c7-4a04-8ded-500597749045
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077649352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.2077649352
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.428464609
Short name T1042
Test name
Test status
Simulation time 136163200 ps
CPU time 134.69 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:44:39 PM PDT 24
Peak memory 262460 kb
Host smart-2f299b63-e39b-40cb-9722-28ca6e642164
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428464609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot
p_reset.428464609
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.1120190363
Short name T381
Test name
Test status
Simulation time 4593687000 ps
CPU time 59.81 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:43:24 PM PDT 24
Peak memory 263904 kb
Host smart-1042fee7-2534-451d-8208-c0f5e7fa5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120190363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1120190363
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3454383378
Short name T854
Test name
Test status
Simulation time 67304900 ps
CPU time 52.15 seconds
Started Aug 07 07:42:23 PM PDT 24
Finished Aug 07 07:43:16 PM PDT 24
Peak memory 271500 kb
Host smart-54729846-a8a6-4547-bc8d-8e6d4d44c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454383378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3454383378
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.2624965822
Short name T590
Test name
Test status
Simulation time 50114100 ps
CPU time 14.14 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:42:47 PM PDT 24
Peak memory 265304 kb
Host smart-5251740b-db9f-45c4-9876-3d08840fc2ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624965822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
2624965822
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.2776246703
Short name T753
Test name
Test status
Simulation time 16997400 ps
CPU time 15.87 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:42:40 PM PDT 24
Peak memory 283344 kb
Host smart-a67ae4b6-6872-41f6-914d-dd001d431e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776246703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2776246703
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.1197798676
Short name T82
Test name
Test status
Simulation time 50059900 ps
CPU time 21.98 seconds
Started Aug 07 07:42:25 PM PDT 24
Finished Aug 07 07:42:47 PM PDT 24
Peak memory 273852 kb
Host smart-521018a6-4e74-42e9-98d5-f3144fcb9ffd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197798676 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.1197798676
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.1130722044
Short name T420
Test name
Test status
Simulation time 5647273900 ps
CPU time 109.93 seconds
Started Aug 07 07:42:25 PM PDT 24
Finished Aug 07 07:44:15 PM PDT 24
Peak memory 263340 kb
Host smart-b81abbdc-a5fc-4dc8-8300-9f2700dba97c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130722044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.1130722044
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2651880002
Short name T442
Test name
Test status
Simulation time 131291900 ps
CPU time 133.25 seconds
Started Aug 07 07:42:23 PM PDT 24
Finished Aug 07 07:44:36 PM PDT 24
Peak memory 261296 kb
Host smart-c0e0065d-f894-47d5-91d2-a1c71f1ca075
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651880002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2651880002
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2929883008
Short name T664
Test name
Test status
Simulation time 5136583900 ps
CPU time 72.91 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:43:37 PM PDT 24
Peak memory 265324 kb
Host smart-3d7e7aab-7f33-416d-b486-b67bbb7d64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929883008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2929883008
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3276113735
Short name T554
Test name
Test status
Simulation time 202024200 ps
CPU time 192.81 seconds
Started Aug 07 07:42:24 PM PDT 24
Finished Aug 07 07:45:37 PM PDT 24
Peak memory 281496 kb
Host smart-b1683899-9d88-4435-8b89-8c74ffeef8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276113735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3276113735
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1396628637
Short name T876
Test name
Test status
Simulation time 311494500 ps
CPU time 14.57 seconds
Started Aug 07 07:42:29 PM PDT 24
Finished Aug 07 07:42:44 PM PDT 24
Peak memory 258432 kb
Host smart-be1d9bea-1dc2-4c67-b557-7c29a0c97c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396628637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1396628637
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.1841664098
Short name T1069
Test name
Test status
Simulation time 21504800 ps
CPU time 16.05 seconds
Started Aug 07 07:42:34 PM PDT 24
Finished Aug 07 07:42:50 PM PDT 24
Peak memory 284720 kb
Host smart-7f57ae50-c9e9-4ec7-848b-d0918072cea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841664098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1841664098
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.4075982172
Short name T164
Test name
Test status
Simulation time 59473800 ps
CPU time 22.23 seconds
Started Aug 07 07:42:34 PM PDT 24
Finished Aug 07 07:42:56 PM PDT 24
Peak memory 273876 kb
Host smart-b0cd9192-5860-4a85-9b9d-c33dd1add952
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075982172 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.4075982172
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.1799220627
Short name T306
Test name
Test status
Simulation time 2319812400 ps
CPU time 94.47 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:44:08 PM PDT 24
Peak memory 260232 kb
Host smart-245bde24-862c-47d3-9e32-df077319d42d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799220627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.1799220627
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.635136039
Short name T784
Test name
Test status
Simulation time 39577200 ps
CPU time 134.22 seconds
Started Aug 07 07:42:32 PM PDT 24
Finished Aug 07 07:44:46 PM PDT 24
Peak memory 265200 kb
Host smart-d8661fee-d700-49f7-9699-21fce647e80e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635136039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot
p_reset.635136039
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.3228494143
Short name T962
Test name
Test status
Simulation time 3930822300 ps
CPU time 78.4 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:43:51 PM PDT 24
Peak memory 263880 kb
Host smart-fc9c3202-894b-4bd0-912c-1ced4cab2a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228494143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3228494143
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.1567473581
Short name T666
Test name
Test status
Simulation time 49936600 ps
CPU time 124.17 seconds
Started Aug 07 07:42:36 PM PDT 24
Finished Aug 07 07:44:40 PM PDT 24
Peak memory 268272 kb
Host smart-6288ffed-2b74-40b7-858c-2f19ca82b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567473581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1567473581
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.2192726158
Short name T1060
Test name
Test status
Simulation time 92439500 ps
CPU time 14.04 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:42:47 PM PDT 24
Peak memory 258304 kb
Host smart-f3e89fc0-0c6c-4ad2-a9c9-d9e56d1f80f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192726158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
2192726158
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.3281956951
Short name T429
Test name
Test status
Simulation time 36048600 ps
CPU time 13.73 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:42:47 PM PDT 24
Peak memory 275256 kb
Host smart-da54e07d-8104-489c-a41c-fc48f3d41e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281956951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3281956951
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.2444278037
Short name T834
Test name
Test status
Simulation time 17228600 ps
CPU time 21 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:42:54 PM PDT 24
Peak memory 273800 kb
Host smart-1f040214-e432-4785-9a18-30ff0002aa93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444278037 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.2444278037
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.822643588
Short name T798
Test name
Test status
Simulation time 2353759000 ps
CPU time 144.56 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:44:57 PM PDT 24
Peak memory 261276 kb
Host smart-9b0eeb6a-9860-4dc1-849a-2b1e930aeac3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822643588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h
w_sec_otp.822643588
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.2425416458
Short name T760
Test name
Test status
Simulation time 154907300 ps
CPU time 132.64 seconds
Started Aug 07 07:42:32 PM PDT 24
Finished Aug 07 07:44:45 PM PDT 24
Peak memory 262512 kb
Host smart-0f1b1f3e-9f46-479e-a817-023acbfffcba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425416458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.2425416458
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3385751676
Short name T393
Test name
Test status
Simulation time 5512446600 ps
CPU time 62.31 seconds
Started Aug 07 07:42:32 PM PDT 24
Finished Aug 07 07:43:35 PM PDT 24
Peak memory 264048 kb
Host smart-88072b64-6642-4186-9fa5-acbf156173dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385751676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3385751676
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2308243566
Short name T653
Test name
Test status
Simulation time 69275200 ps
CPU time 170.32 seconds
Started Aug 07 07:42:36 PM PDT 24
Finished Aug 07 07:45:26 PM PDT 24
Peak memory 277836 kb
Host smart-69b55823-c692-4279-b628-b93bafd5b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308243566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2308243566
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.3841101071
Short name T618
Test name
Test status
Simulation time 49307500 ps
CPU time 13.77 seconds
Started Aug 07 07:34:54 PM PDT 24
Finished Aug 07 07:35:08 PM PDT 24
Peak memory 258384 kb
Host smart-f0c3dc1b-8bee-49f8-9c91-aa6a8aff4b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841101071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3
841101071
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1135146869
Short name T474
Test name
Test status
Simulation time 22448200 ps
CPU time 16 seconds
Started Aug 07 07:34:57 PM PDT 24
Finished Aug 07 07:35:13 PM PDT 24
Peak memory 283400 kb
Host smart-2fd4fc02-14f1-4d87-9e21-2dc64856a58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135146869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1135146869
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1372690940
Short name T367
Test name
Test status
Simulation time 35986600 ps
CPU time 22.74 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:35:09 PM PDT 24
Peak memory 273744 kb
Host smart-bd99ce78-aab3-4a65-a0d4-fd188db01c61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372690940 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1372690940
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.4135533392
Short name T541
Test name
Test status
Simulation time 11253686000 ps
CPU time 2741.1 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 08:20:28 PM PDT 24
Peak memory 263044 kb
Host smart-3a8c8fca-174c-4bbd-afd3-d412a4d209e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4135533392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.4135533392
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2025491823
Short name T906
Test name
Test status
Simulation time 637190700 ps
CPU time 913.58 seconds
Started Aug 07 07:34:49 PM PDT 24
Finished Aug 07 07:50:03 PM PDT 24
Peak memory 273492 kb
Host smart-c4f33fb8-c094-4268-af45-f96df5e47a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025491823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2025491823
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.3537992752
Short name T702
Test name
Test status
Simulation time 1166509100 ps
CPU time 28.37 seconds
Started Aug 07 07:34:49 PM PDT 24
Finished Aug 07 07:35:18 PM PDT 24
Peak memory 262876 kb
Host smart-5ff2eb8f-803f-4841-a192-f5b1b2fb02e3
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537992752 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_fetch_code.3537992752
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3321257710
Short name T284
Test name
Test status
Simulation time 10020266600 ps
CPU time 90.8 seconds
Started Aug 07 07:34:54 PM PDT 24
Finished Aug 07 07:36:25 PM PDT 24
Peak memory 333772 kb
Host smart-ed65b7fa-d09e-4c3e-911d-d407bf58064c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321257710 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3321257710
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2099299774
Short name T332
Test name
Test status
Simulation time 48677800 ps
CPU time 13.83 seconds
Started Aug 07 07:34:58 PM PDT 24
Finished Aug 07 07:35:12 PM PDT 24
Peak memory 260280 kb
Host smart-c7665a1a-eab3-4bfd-9f1c-ff2bb8993059
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099299774 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2099299774
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3704984341
Short name T847
Test name
Test status
Simulation time 40120121800 ps
CPU time 837.6 seconds
Started Aug 07 07:34:34 PM PDT 24
Finished Aug 07 07:48:32 PM PDT 24
Peak memory 261224 kb
Host smart-f8d87f64-15ba-4012-9367-5fce99d019cb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704984341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.3704984341
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1716751676
Short name T465
Test name
Test status
Simulation time 4912762300 ps
CPU time 209.59 seconds
Started Aug 07 07:34:32 PM PDT 24
Finished Aug 07 07:38:02 PM PDT 24
Peak memory 263560 kb
Host smart-f3721262-9797-4e70-91af-74c860751459
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716751676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1716751676
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.237790125
Short name T329
Test name
Test status
Simulation time 1438827900 ps
CPU time 134.89 seconds
Started Aug 07 07:34:51 PM PDT 24
Finished Aug 07 07:37:06 PM PDT 24
Peak memory 294620 kb
Host smart-3c9e1ae4-efbc-4fb5-98d0-dd4d46ca5ed9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237790125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_intr_rd.237790125
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.99574168
Short name T646
Test name
Test status
Simulation time 44383925600 ps
CPU time 195.8 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:38:02 PM PDT 24
Peak memory 292268 kb
Host smart-2c25dcf0-f502-4fd8-83c0-61250104dc55
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99574168 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.99574168
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3992951003
Short name T640
Test name
Test status
Simulation time 1886804500 ps
CPU time 60.67 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:35:47 PM PDT 24
Peak memory 260820 kb
Host smart-6b39addf-4a73-4408-a8d5-4832e9cd738f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992951003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3992951003
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3717265023
Short name T456
Test name
Test status
Simulation time 44296979500 ps
CPU time 220.65 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:38:27 PM PDT 24
Peak memory 265492 kb
Host smart-7059e143-a13c-4208-b1e4-fedd09479f9a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371
7265023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3717265023
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3333907034
Short name T632
Test name
Test status
Simulation time 4036091800 ps
CPU time 84.04 seconds
Started Aug 07 07:34:49 PM PDT 24
Finished Aug 07 07:36:13 PM PDT 24
Peak memory 261176 kb
Host smart-a3836719-bb13-4628-b94c-6ba0d10bf153
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333907034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3333907034
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1330322493
Short name T538
Test name
Test status
Simulation time 47182500 ps
CPU time 14.33 seconds
Started Aug 07 07:34:56 PM PDT 24
Finished Aug 07 07:35:11 PM PDT 24
Peak memory 260416 kb
Host smart-763df1df-1307-4052-a727-fbdfb94ed7f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330322493 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1330322493
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3487632684
Short name T937
Test name
Test status
Simulation time 11910289900 ps
CPU time 186.4 seconds
Started Aug 07 07:34:33 PM PDT 24
Finished Aug 07 07:37:40 PM PDT 24
Peak memory 265432 kb
Host smart-c3a4d372-c7ce-4dd5-b919-da7c43e1958f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487632684 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.3487632684
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.880253814
Short name T943
Test name
Test status
Simulation time 316788900 ps
CPU time 134.98 seconds
Started Aug 07 07:34:33 PM PDT 24
Finished Aug 07 07:36:48 PM PDT 24
Peak memory 261192 kb
Host smart-654fe68b-9214-4f24-ba44-6f51928ee6ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880253814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp
_reset.880253814
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.4173229351
Short name T841
Test name
Test status
Simulation time 230115500 ps
CPU time 323.57 seconds
Started Aug 07 07:34:32 PM PDT 24
Finished Aug 07 07:39:56 PM PDT 24
Peak memory 263468 kb
Host smart-224fb7ac-7efe-4109-a03c-ece1f23548c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173229351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.4173229351
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.1104181132
Short name T609
Test name
Test status
Simulation time 2518025800 ps
CPU time 172.18 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:37:38 PM PDT 24
Peak memory 260788 kb
Host smart-64b7cf17-b4f6-4a4f-b855-2224991fb787
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104181132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.flash_ctrl_prog_reset.1104181132
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.1687960706
Short name T149
Test name
Test status
Simulation time 3040736300 ps
CPU time 1259.69 seconds
Started Aug 07 07:34:32 PM PDT 24
Finished Aug 07 07:55:32 PM PDT 24
Peak memory 288236 kb
Host smart-cd452c9b-105d-474d-8589-717a5676b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687960706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.1687960706
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.4217593757
Short name T955
Test name
Test status
Simulation time 1179212000 ps
CPU time 133.95 seconds
Started Aug 07 07:34:49 PM PDT 24
Finished Aug 07 07:37:03 PM PDT 24
Peak memory 291964 kb
Host smart-5e1b0714-9b17-4f4f-9897-9f2050d65362
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217593757 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.4217593757
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1417154591
Short name T987
Test name
Test status
Simulation time 468770700 ps
CPU time 126.16 seconds
Started Aug 07 07:34:45 PM PDT 24
Finished Aug 07 07:36:52 PM PDT 24
Peak memory 282136 kb
Host smart-e35fa7f8-be74-4ebc-8205-ea9143a3d823
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1417154591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1417154591
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3636495072
Short name T740
Test name
Test status
Simulation time 594737000 ps
CPU time 174.9 seconds
Started Aug 07 07:34:44 PM PDT 24
Finished Aug 07 07:37:39 PM PDT 24
Peak memory 282140 kb
Host smart-8a2c163e-1a06-4047-becf-bb5c9c69b3b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636495072 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3636495072
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.883845430
Short name T211
Test name
Test status
Simulation time 3892403900 ps
CPU time 603.78 seconds
Started Aug 07 07:34:48 PM PDT 24
Finished Aug 07 07:44:52 PM PDT 24
Peak memory 310728 kb
Host smart-ec1c25e4-839b-48c8-8b94-2788b4491a6b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883845430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_rw.883845430
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.2916372723
Short name T939
Test name
Test status
Simulation time 1373296900 ps
CPU time 239.94 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:38:46 PM PDT 24
Peak memory 287768 kb
Host smart-4129771b-1704-45da-871e-981e7c5de53e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916372723 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_derr.2916372723
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.2352813921
Short name T1074
Test name
Test status
Simulation time 28497000 ps
CPU time 31.15 seconds
Started Aug 07 07:34:46 PM PDT 24
Finished Aug 07 07:35:17 PM PDT 24
Peak memory 275904 kb
Host smart-fd6651a7-ac9e-42af-aa4d-6cf9e6246182
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352813921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.2352813921
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3873832596
Short name T344
Test name
Test status
Simulation time 31444800 ps
CPU time 32.53 seconds
Started Aug 07 07:34:50 PM PDT 24
Finished Aug 07 07:35:22 PM PDT 24
Peak memory 273856 kb
Host smart-70811478-4850-4f5e-a9b3-70a9f7868f64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873832596 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3873832596
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.1696918576
Short name T39
Test name
Test status
Simulation time 8682014900 ps
CPU time 226.18 seconds
Started Aug 07 07:34:47 PM PDT 24
Finished Aug 07 07:38:34 PM PDT 24
Peak memory 295696 kb
Host smart-cfb967a1-f94f-45da-868c-a5763480b5d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696918576 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.flash_ctrl_rw_serr.1696918576
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3285325816
Short name T588
Test name
Test status
Simulation time 1056413100 ps
CPU time 58.88 seconds
Started Aug 07 07:34:45 PM PDT 24
Finished Aug 07 07:35:44 PM PDT 24
Peak memory 262868 kb
Host smart-beed9185-8473-4f8c-8447-7e3ee791fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285325816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3285325816
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.568437390
Short name T691
Test name
Test status
Simulation time 38757600 ps
CPU time 131.41 seconds
Started Aug 07 07:34:35 PM PDT 24
Finished Aug 07 07:36:46 PM PDT 24
Peak memory 268832 kb
Host smart-8fe7246b-0681-4122-ba0f-88df8f7a7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568437390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.568437390
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.2374149947
Short name T1105
Test name
Test status
Simulation time 2500848900 ps
CPU time 173.88 seconds
Started Aug 07 07:34:48 PM PDT 24
Finished Aug 07 07:37:42 PM PDT 24
Peak memory 265548 kb
Host smart-a678f096-911a-4767-a0e9-aa1b6d843064
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374149947 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.2374149947
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1542408138
Short name T1040
Test name
Test status
Simulation time 17084900 ps
CPU time 15.81 seconds
Started Aug 07 07:42:34 PM PDT 24
Finished Aug 07 07:42:50 PM PDT 24
Peak memory 283392 kb
Host smart-636ffbd9-5a00-42c0-ad95-cdde65a5013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542408138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1542408138
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.1227592967
Short name T182
Test name
Test status
Simulation time 41280600 ps
CPU time 133.58 seconds
Started Aug 07 07:42:32 PM PDT 24
Finished Aug 07 07:44:45 PM PDT 24
Peak memory 261324 kb
Host smart-72a796c3-759e-403c-a4fd-942d84ce6da6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227592967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.1227592967
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3166139333
Short name T1012
Test name
Test status
Simulation time 13945500 ps
CPU time 15.98 seconds
Started Aug 07 07:42:33 PM PDT 24
Finished Aug 07 07:42:49 PM PDT 24
Peak memory 284684 kb
Host smart-c4da2cda-be8d-4acc-b010-f8beb74f515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166139333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3166139333
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.2742342058
Short name T71
Test name
Test status
Simulation time 42204800 ps
CPU time 133.51 seconds
Started Aug 07 07:42:36 PM PDT 24
Finished Aug 07 07:44:49 PM PDT 24
Peak memory 260472 kb
Host smart-94ca24ff-42a4-4e0d-93f6-ac7166aeacb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742342058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.2742342058
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.2406895945
Short name T866
Test name
Test status
Simulation time 16877000 ps
CPU time 16.17 seconds
Started Aug 07 07:42:42 PM PDT 24
Finished Aug 07 07:42:58 PM PDT 24
Peak memory 284716 kb
Host smart-21cf9d5e-b56c-4832-aa07-d2da551c40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406895945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2406895945
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.1303726143
Short name T1090
Test name
Test status
Simulation time 73287500 ps
CPU time 134.38 seconds
Started Aug 07 07:42:31 PM PDT 24
Finished Aug 07 07:44:46 PM PDT 24
Peak memory 261168 kb
Host smart-758b5ce9-62da-4d20-977e-e7abc5775244
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303726143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.1303726143
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.3815173867
Short name T521
Test name
Test status
Simulation time 156161300 ps
CPU time 13.54 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:55 PM PDT 24
Peak memory 284748 kb
Host smart-ec2e6b9b-d872-4aa0-95a4-64c89ee138da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815173867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.3815173867
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.1119933647
Short name T973
Test name
Test status
Simulation time 68256900 ps
CPU time 134.73 seconds
Started Aug 07 07:42:40 PM PDT 24
Finished Aug 07 07:44:55 PM PDT 24
Peak memory 260436 kb
Host smart-7645a87b-bc17-4155-97e4-1d7e365d13b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119933647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.1119933647
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.2041505745
Short name T864
Test name
Test status
Simulation time 40965300 ps
CPU time 15.58 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:56 PM PDT 24
Peak memory 284712 kb
Host smart-c8f49882-7a66-4632-a628-b68c0077332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041505745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2041505745
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.3489389414
Short name T170
Test name
Test status
Simulation time 39213400 ps
CPU time 111.99 seconds
Started Aug 07 07:42:47 PM PDT 24
Finished Aug 07 07:44:39 PM PDT 24
Peak memory 264320 kb
Host smart-dc8cd41b-7819-40c5-ba66-8ce5d61c0b85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489389414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.3489389414
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.301132642
Short name T101
Test name
Test status
Simulation time 13953900 ps
CPU time 13.61 seconds
Started Aug 07 07:42:44 PM PDT 24
Finished Aug 07 07:42:58 PM PDT 24
Peak memory 283396 kb
Host smart-cd9aa1e2-ad6e-4b85-9605-b12706f9b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301132642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.301132642
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.3932840863
Short name T977
Test name
Test status
Simulation time 41727100 ps
CPU time 134.2 seconds
Started Aug 07 07:42:42 PM PDT 24
Finished Aug 07 07:44:56 PM PDT 24
Peak memory 260248 kb
Host smart-b8bb632d-949e-4a8e-aaa8-405001f69ff7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932840863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.3932840863
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2074682460
Short name T651
Test name
Test status
Simulation time 47979800 ps
CPU time 16.18 seconds
Started Aug 07 07:42:43 PM PDT 24
Finished Aug 07 07:42:59 PM PDT 24
Peak memory 283520 kb
Host smart-81e87d65-bec8-4bc9-9265-6fdbf12ed34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074682460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2074682460
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.1692818533
Short name T1092
Test name
Test status
Simulation time 140963300 ps
CPU time 133.19 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:44:54 PM PDT 24
Peak memory 261408 kb
Host smart-a094ba6f-b668-4886-be53-fb859eafb04f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692818533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.1692818533
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.1793807839
Short name T672
Test name
Test status
Simulation time 23787200 ps
CPU time 13.65 seconds
Started Aug 07 07:42:42 PM PDT 24
Finished Aug 07 07:42:56 PM PDT 24
Peak memory 284576 kb
Host smart-8ca1fd3f-9c36-42e7-8e8b-2bf808f6ed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793807839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1793807839
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.171412066
Short name T771
Test name
Test status
Simulation time 125310200 ps
CPU time 112.68 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:44:34 PM PDT 24
Peak memory 260164 kb
Host smart-2cca4eac-16a9-4cde-ad8f-bcb66aa8c8c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171412066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.171412066
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2694304439
Short name T436
Test name
Test status
Simulation time 23318100 ps
CPU time 13.46 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:54 PM PDT 24
Peak memory 283512 kb
Host smart-4e60b237-b6f3-44f2-8aa7-77d379505e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694304439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2694304439
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.4133200231
Short name T859
Test name
Test status
Simulation time 13167300 ps
CPU time 16.05 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:57 PM PDT 24
Peak memory 284812 kb
Host smart-f1cfd30f-cc4f-4a84-8d3b-9c0fe80b43b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133200231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.4133200231
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.2436383001
Short name T176
Test name
Test status
Simulation time 80125100 ps
CPU time 132.68 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:45:01 PM PDT 24
Peak memory 260312 kb
Host smart-86815671-c716-4ba1-853f-a7b8461096db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436383001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.2436383001
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.4172762120
Short name T843
Test name
Test status
Simulation time 204382800 ps
CPU time 14.34 seconds
Started Aug 07 07:35:14 PM PDT 24
Finished Aug 07 07:35:28 PM PDT 24
Peak memory 258316 kb
Host smart-2fac035f-63b1-4e29-9bd2-b40ebea153bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172762120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.4
172762120
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1226431944
Short name T1093
Test name
Test status
Simulation time 57802400 ps
CPU time 16.4 seconds
Started Aug 07 07:35:16 PM PDT 24
Finished Aug 07 07:35:33 PM PDT 24
Peak memory 283348 kb
Host smart-41072a9d-9041-4e29-a51d-a027f2c499ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226431944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1226431944
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.2302419526
Short name T1108
Test name
Test status
Simulation time 10294300 ps
CPU time 22.3 seconds
Started Aug 07 07:35:13 PM PDT 24
Finished Aug 07 07:35:35 PM PDT 24
Peak memory 273816 kb
Host smart-68f96ad4-926b-4ef4-b0af-01ad74fc7b96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302419526 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.2302419526
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.2976104702
Short name T916
Test name
Test status
Simulation time 7450852900 ps
CPU time 2370.97 seconds
Started Aug 07 07:34:58 PM PDT 24
Finished Aug 07 08:14:29 PM PDT 24
Peak memory 263072 kb
Host smart-653c2e20-1a93-4224-9fd5-4ac473acd8e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2976104702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.2976104702
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.1905438522
Short name T290
Test name
Test status
Simulation time 780412200 ps
CPU time 984.42 seconds
Started Aug 07 07:34:58 PM PDT 24
Finished Aug 07 07:51:23 PM PDT 24
Peak memory 273616 kb
Host smart-9cd0dfb8-8ee5-44e9-8964-7ff7ed140dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905438522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1905438522
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1838241862
Short name T286
Test name
Test status
Simulation time 10019561900 ps
CPU time 66.19 seconds
Started Aug 07 07:35:14 PM PDT 24
Finished Aug 07 07:36:21 PM PDT 24
Peak memory 275480 kb
Host smart-efd3ac64-1b7e-4983-a4b8-cdfb50d701d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838241862 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1838241862
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.1267788864
Short name T165
Test name
Test status
Simulation time 47366500 ps
CPU time 13.63 seconds
Started Aug 07 07:35:15 PM PDT 24
Finished Aug 07 07:35:28 PM PDT 24
Peak memory 258664 kb
Host smart-bb5908e1-4f36-4836-af20-e8f05932ecbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267788864 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1267788864
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.377138825
Short name T933
Test name
Test status
Simulation time 40124416800 ps
CPU time 890.44 seconds
Started Aug 07 07:34:57 PM PDT 24
Finished Aug 07 07:49:47 PM PDT 24
Peak memory 265204 kb
Host smart-85b0e4be-9a89-4a7e-a820-fbade2eeeccd
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377138825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.377138825
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.781596601
Short name T557
Test name
Test status
Simulation time 4073030900 ps
CPU time 149.88 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:37:35 PM PDT 24
Peak memory 260668 kb
Host smart-dc1b9ef7-45e8-4150-a2b5-ed2c4771cb68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781596601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw
_sec_otp.781596601
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.1302979289
Short name T1095
Test name
Test status
Simulation time 22477740000 ps
CPU time 228.65 seconds
Started Aug 07 07:35:04 PM PDT 24
Finished Aug 07 07:38:53 PM PDT 24
Peak memory 285280 kb
Host smart-809dfd08-d119-43b4-b95f-5085acc5845b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302979289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.1302979289
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1431123150
Short name T8
Test name
Test status
Simulation time 7489972800 ps
CPU time 141.25 seconds
Started Aug 07 07:35:04 PM PDT 24
Finished Aug 07 07:37:25 PM PDT 24
Peak memory 293452 kb
Host smart-92223aea-5f78-4019-a9ca-3f7d0e586b6b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431123150 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1431123150
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.462503262
Short name T448
Test name
Test status
Simulation time 7930738000 ps
CPU time 71.11 seconds
Started Aug 07 07:35:04 PM PDT 24
Finished Aug 07 07:36:15 PM PDT 24
Peak memory 265416 kb
Host smart-b03425b7-25dc-476a-b87e-7073e7913bab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462503262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.flash_ctrl_intr_wr.462503262
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2716036880
Short name T461
Test name
Test status
Simulation time 39539374700 ps
CPU time 187.09 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:38:13 PM PDT 24
Peak memory 260816 kb
Host smart-a701d8bd-a212-420c-a897-d48321d25cce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271
6036880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2716036880
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.1634088324
Short name T439
Test name
Test status
Simulation time 2258128600 ps
CPU time 91.7 seconds
Started Aug 07 07:34:57 PM PDT 24
Finished Aug 07 07:36:29 PM PDT 24
Peak memory 263824 kb
Host smart-2b2a96a8-7814-4362-bfb4-0a8aa93f6307
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634088324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.1634088324
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.1494821375
Short name T749
Test name
Test status
Simulation time 35214781900 ps
CPU time 1180.25 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:54:45 PM PDT 24
Peak memory 275336 kb
Host smart-4b5bb1e7-2e67-408b-ac0a-46f7a5bc0c6a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494821375 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.1494821375
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.1395746920
Short name T527
Test name
Test status
Simulation time 40237100 ps
CPU time 131.11 seconds
Started Aug 07 07:34:56 PM PDT 24
Finished Aug 07 07:37:07 PM PDT 24
Peak memory 260068 kb
Host smart-079f5843-2c0a-4989-b8fb-46f9167f3bcf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395746920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.1395746920
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.2794628732
Short name T581
Test name
Test status
Simulation time 714677800 ps
CPU time 214.78 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:38:40 PM PDT 24
Peak memory 263404 kb
Host smart-83206351-c9b5-492e-b4e9-9b75606af206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794628732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.2794628732
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.3858136350
Short name T870
Test name
Test status
Simulation time 25663900 ps
CPU time 13.63 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:35:19 PM PDT 24
Peak memory 259136 kb
Host smart-2d4bee21-fb8b-4e53-ad98-fd4df7dc7083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858136350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.flash_ctrl_prog_reset.3858136350
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.401561640
Short name T563
Test name
Test status
Simulation time 209834800 ps
CPU time 779.02 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:48:05 PM PDT 24
Peak memory 285580 kb
Host smart-d50f3771-d8b0-4078-b9ab-4ad5e9d42ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401561640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.401561640
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.2708286341
Short name T102
Test name
Test status
Simulation time 105095000 ps
CPU time 32.53 seconds
Started Aug 07 07:35:14 PM PDT 24
Finished Aug 07 07:35:46 PM PDT 24
Peak memory 273928 kb
Host smart-a137d26d-f014-43b6-904b-caf79faa1bf1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708286341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.2708286341
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.558501704
Short name T797
Test name
Test status
Simulation time 625817900 ps
CPU time 105.35 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:36:50 PM PDT 24
Peak memory 282112 kb
Host smart-e9a0e7f5-faaf-4473-9602-fd5835c4e445
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558501704 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.558501704
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.3381722040
Short name T1008
Test name
Test status
Simulation time 3198486700 ps
CPU time 165.5 seconds
Started Aug 07 07:35:06 PM PDT 24
Finished Aug 07 07:37:52 PM PDT 24
Peak memory 284296 kb
Host smart-43daa043-d834-496c-ad67-6f20ebba212d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3381722040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3381722040
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1843285931
Short name T750
Test name
Test status
Simulation time 843086700 ps
CPU time 128 seconds
Started Aug 07 07:35:04 PM PDT 24
Finished Aug 07 07:37:12 PM PDT 24
Peak memory 290300 kb
Host smart-544991fe-9a0d-4eb3-94b2-f92fdb2cadbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843285931 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1843285931
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.988699530
Short name T213
Test name
Test status
Simulation time 4547814700 ps
CPU time 532.61 seconds
Started Aug 07 07:35:06 PM PDT 24
Finished Aug 07 07:43:59 PM PDT 24
Peak memory 314736 kb
Host smart-872a2b4a-2af0-4150-b3c6-eac754aea476
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988699530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_rw.988699530
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.3611109977
Short name T928
Test name
Test status
Simulation time 2196321200 ps
CPU time 181.41 seconds
Started Aug 07 07:35:04 PM PDT 24
Finished Aug 07 07:38:05 PM PDT 24
Peak memory 285616 kb
Host smart-6fbdce35-3464-453e-b4f4-dbdd22484803
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611109977 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_derr.3611109977
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.2355834814
Short name T513
Test name
Test status
Simulation time 43020100 ps
CPU time 31.5 seconds
Started Aug 07 07:35:06 PM PDT 24
Finished Aug 07 07:35:37 PM PDT 24
Peak memory 275924 kb
Host smart-ef86cc9d-7d31-4cdf-942a-f451c8100320
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355834814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.2355834814
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1560547998
Short name T341
Test name
Test status
Simulation time 27734700 ps
CPU time 31.78 seconds
Started Aug 07 07:35:05 PM PDT 24
Finished Aug 07 07:35:37 PM PDT 24
Peak memory 275920 kb
Host smart-5e958bde-a376-4287-a649-c26c0a5ff1e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560547998 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.1560547998
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.1147335701
Short name T404
Test name
Test status
Simulation time 5006644700 ps
CPU time 259.56 seconds
Started Aug 07 07:35:03 PM PDT 24
Finished Aug 07 07:39:22 PM PDT 24
Peak memory 282144 kb
Host smart-e3fda1af-be3c-4eb6-9b31-00565755306c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147335701 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.flash_ctrl_rw_serr.1147335701
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.1104545529
Short name T970
Test name
Test status
Simulation time 482621400 ps
CPU time 62.06 seconds
Started Aug 07 07:35:15 PM PDT 24
Finished Aug 07 07:36:17 PM PDT 24
Peak memory 263928 kb
Host smart-d1974c24-2331-47c8-850f-7f656d1e251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104545529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1104545529
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.700451607
Short name T948
Test name
Test status
Simulation time 23699500 ps
CPU time 99.85 seconds
Started Aug 07 07:34:56 PM PDT 24
Finished Aug 07 07:36:36 PM PDT 24
Peak memory 277152 kb
Host smart-dfc29af7-89b0-4721-8460-5c12912230de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700451607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.700451607
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.3155305307
Short name T137
Test name
Test status
Simulation time 4975023500 ps
CPU time 212.86 seconds
Started Aug 07 07:34:55 PM PDT 24
Finished Aug 07 07:38:28 PM PDT 24
Peak memory 260204 kb
Host smart-df36bcf8-a11f-4ed3-b608-185dfacbef43
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155305307 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.3155305307
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.2189010846
Short name T540
Test name
Test status
Simulation time 13885700 ps
CPU time 13.65 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:55 PM PDT 24
Peak memory 283408 kb
Host smart-5685c4f7-f3de-4ebe-ab46-d67e27579380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189010846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2189010846
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2833930287
Short name T727
Test name
Test status
Simulation time 79930900 ps
CPU time 134.45 seconds
Started Aug 07 07:42:44 PM PDT 24
Finished Aug 07 07:44:58 PM PDT 24
Peak memory 264460 kb
Host smart-6ccc422e-75a8-4a59-be70-0846fb3e9e08
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833930287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2833930287
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.4274103606
Short name T889
Test name
Test status
Simulation time 28028000 ps
CPU time 15.94 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:57 PM PDT 24
Peak memory 283348 kb
Host smart-cecb19ef-2d8f-4f13-9731-12a08afcbca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274103606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.4274103606
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.2529048919
Short name T463
Test name
Test status
Simulation time 133954700 ps
CPU time 112.45 seconds
Started Aug 07 07:42:40 PM PDT 24
Finished Aug 07 07:44:33 PM PDT 24
Peak memory 260368 kb
Host smart-782e5c0c-9742-42b3-833b-227f61198175
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529048919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.2529048919
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3167280064
Short name T514
Test name
Test status
Simulation time 166731000 ps
CPU time 15.92 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:57 PM PDT 24
Peak memory 275308 kb
Host smart-f473478c-ab4f-440b-ad03-198afc60bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167280064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3167280064
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3484447698
Short name T181
Test name
Test status
Simulation time 331539200 ps
CPU time 136.06 seconds
Started Aug 07 07:42:42 PM PDT 24
Finished Aug 07 07:44:58 PM PDT 24
Peak memory 261264 kb
Host smart-9e86f491-1b9b-44d3-81d5-9345fae8b5ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484447698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3484447698
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3306418843
Short name T1017
Test name
Test status
Simulation time 45857000 ps
CPU time 16.22 seconds
Started Aug 07 07:42:41 PM PDT 24
Finished Aug 07 07:42:58 PM PDT 24
Peak memory 284640 kb
Host smart-4e2e5277-e066-4d73-a0f6-7b97aeba52ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306418843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3306418843
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.2334608765
Short name T179
Test name
Test status
Simulation time 38004000 ps
CPU time 112.96 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:44:41 PM PDT 24
Peak memory 260312 kb
Host smart-dfb30f00-98f7-4167-b2d7-6b7b9c0db622
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334608765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.2334608765
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1241618807
Short name T858
Test name
Test status
Simulation time 17331400 ps
CPU time 15.85 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:43:04 PM PDT 24
Peak memory 284692 kb
Host smart-12f2ffc6-4b67-4968-ba28-faf3ef0eda79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241618807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1241618807
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.1516170831
Short name T725
Test name
Test status
Simulation time 36518000 ps
CPU time 112.56 seconds
Started Aug 07 07:42:51 PM PDT 24
Finished Aug 07 07:44:44 PM PDT 24
Peak memory 260128 kb
Host smart-c9d4d331-1979-45c7-a3fa-5c298582d4b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516170831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.1516170831
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.846246532
Short name T1057
Test name
Test status
Simulation time 15864300 ps
CPU time 13.44 seconds
Started Aug 07 07:42:50 PM PDT 24
Finished Aug 07 07:43:03 PM PDT 24
Peak memory 284648 kb
Host smart-f2da79b0-0c56-49ff-8245-b6fbed042771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846246532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.846246532
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.263622169
Short name T562
Test name
Test status
Simulation time 157271600 ps
CPU time 113.58 seconds
Started Aug 07 07:42:49 PM PDT 24
Finished Aug 07 07:44:43 PM PDT 24
Peak memory 261368 kb
Host smart-c13e977a-053a-4d2b-8b77-99113eaedd19
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263622169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_ot
p_reset.263622169
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2082742803
Short name T516
Test name
Test status
Simulation time 23982700 ps
CPU time 16.03 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:43:04 PM PDT 24
Peak memory 283368 kb
Host smart-18b0fca0-34f8-4979-8c8d-7041437dd005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082742803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2082742803
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.280469619
Short name T692
Test name
Test status
Simulation time 131545900 ps
CPU time 128.39 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:44:56 PM PDT 24
Peak memory 261172 kb
Host smart-b6905756-95fd-4ccf-97ae-b504eb8cabf5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280469619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot
p_reset.280469619
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.120792341
Short name T1070
Test name
Test status
Simulation time 14512500 ps
CPU time 15.92 seconds
Started Aug 07 07:42:50 PM PDT 24
Finished Aug 07 07:43:06 PM PDT 24
Peak memory 275236 kb
Host smart-dc6d9432-30e7-4d10-8419-fb9af7e8e70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120792341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.120792341
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3973390619
Short name T74
Test name
Test status
Simulation time 37370700 ps
CPU time 135.67 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:45:04 PM PDT 24
Peak memory 260160 kb
Host smart-3dd2ec5e-484f-4b89-a57b-28fa7a246a66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973390619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3973390619
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.2539064278
Short name T965
Test name
Test status
Simulation time 40724900 ps
CPU time 16.53 seconds
Started Aug 07 07:42:49 PM PDT 24
Finished Aug 07 07:43:05 PM PDT 24
Peak memory 284616 kb
Host smart-74a4307f-ff22-4fd4-8156-230a6c61c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539064278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2539064278
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3809622547
Short name T942
Test name
Test status
Simulation time 232076300 ps
CPU time 135.11 seconds
Started Aug 07 07:42:51 PM PDT 24
Finished Aug 07 07:45:06 PM PDT 24
Peak memory 260160 kb
Host smart-9501ab32-35c6-492b-9911-e03f8aac3d20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809622547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3809622547
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.199444430
Short name T480
Test name
Test status
Simulation time 15241900 ps
CPU time 13.37 seconds
Started Aug 07 07:42:51 PM PDT 24
Finished Aug 07 07:43:05 PM PDT 24
Peak memory 284740 kb
Host smart-a8fbfd2e-758e-49ac-9cf9-b0c89e25047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199444430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.199444430
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.3869400735
Short name T450
Test name
Test status
Simulation time 79907100 ps
CPU time 131.44 seconds
Started Aug 07 07:42:49 PM PDT 24
Finished Aug 07 07:45:01 PM PDT 24
Peak memory 260120 kb
Host smart-663957c3-34af-4618-aae6-92fc195d702a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869400735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.3869400735
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.438075690
Short name T417
Test name
Test status
Simulation time 166561200 ps
CPU time 13.85 seconds
Started Aug 07 07:35:48 PM PDT 24
Finished Aug 07 07:36:02 PM PDT 24
Peak memory 265348 kb
Host smart-cad6ba9a-8268-487d-a0cf-8ba86c1639fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438075690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.438075690
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2621846425
Short name T1064
Test name
Test status
Simulation time 28887800 ps
CPU time 13.75 seconds
Started Aug 07 07:35:39 PM PDT 24
Finished Aug 07 07:35:53 PM PDT 24
Peak memory 283424 kb
Host smart-fd5a015b-c32f-4aad-8284-077247b5702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621846425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2621846425
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.4096285013
Short name T376
Test name
Test status
Simulation time 12304500 ps
CPU time 22.55 seconds
Started Aug 07 07:35:41 PM PDT 24
Finished Aug 07 07:36:03 PM PDT 24
Peak memory 266732 kb
Host smart-e12d7c4b-7ecf-49d7-aeb7-18b791ec1e24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096285013 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.4096285013
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3444639226
Short name T951
Test name
Test status
Simulation time 6626866100 ps
CPU time 2352.24 seconds
Started Aug 07 07:35:23 PM PDT 24
Finished Aug 07 08:14:35 PM PDT 24
Peak memory 264660 kb
Host smart-28e80e62-201e-4cd0-a301-dbc79f4267e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3444639226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3444639226
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.794798662
Short name T756
Test name
Test status
Simulation time 3723245600 ps
CPU time 835.49 seconds
Started Aug 07 07:35:23 PM PDT 24
Finished Aug 07 07:49:19 PM PDT 24
Peak memory 273628 kb
Host smart-ddca61c8-cdb3-4e7a-8be6-b7559e4d08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794798662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.794798662
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1979559081
Short name T524
Test name
Test status
Simulation time 149222700 ps
CPU time 26.9 seconds
Started Aug 07 07:35:22 PM PDT 24
Finished Aug 07 07:35:49 PM PDT 24
Peak memory 263908 kb
Host smart-3daeda1a-97b5-40e2-bad0-31e69485f746
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979559081 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_fetch_code.1979559081
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2271556161
Short name T287
Test name
Test status
Simulation time 10031827200 ps
CPU time 119.57 seconds
Started Aug 07 07:35:50 PM PDT 24
Finished Aug 07 07:37:50 PM PDT 24
Peak memory 275776 kb
Host smart-7433fab2-586c-4a8c-aee7-ebe40fd75b04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271556161 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2271556161
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1340324682
Short name T1073
Test name
Test status
Simulation time 15856300 ps
CPU time 13.56 seconds
Started Aug 07 07:35:50 PM PDT 24
Finished Aug 07 07:36:04 PM PDT 24
Peak memory 265024 kb
Host smart-ed834346-a207-41df-81dd-eee6315d818f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340324682 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1340324682
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1217829427
Short name T410
Test name
Test status
Simulation time 2176636800 ps
CPU time 116.26 seconds
Started Aug 07 07:35:22 PM PDT 24
Finished Aug 07 07:37:19 PM PDT 24
Peak memory 262228 kb
Host smart-4fc87266-a1d6-418b-8c27-0cdcc20ba148
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217829427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1217829427
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.1711894512
Short name T528
Test name
Test status
Simulation time 5207992800 ps
CPU time 202.31 seconds
Started Aug 07 07:35:30 PM PDT 24
Finished Aug 07 07:38:52 PM PDT 24
Peak memory 285260 kb
Host smart-2f7dcd5c-0684-46a1-9ccd-8b4011f653e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711894512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.1711894512
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1149277124
Short name T353
Test name
Test status
Simulation time 25180599000 ps
CPU time 262.71 seconds
Started Aug 07 07:35:31 PM PDT 24
Finished Aug 07 07:39:54 PM PDT 24
Peak memory 285516 kb
Host smart-b0f9bf1e-0420-49c5-ab02-7d8a5e40c6f3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149277124 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.1149277124
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.2265195280
Short name T525
Test name
Test status
Simulation time 2277622700 ps
CPU time 74.14 seconds
Started Aug 07 07:35:31 PM PDT 24
Finished Aug 07 07:36:46 PM PDT 24
Peak memory 260860 kb
Host smart-30135d88-82fb-407e-b418-16f7abff507a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265195280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.2265195280
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3251313528
Short name T559
Test name
Test status
Simulation time 23394297400 ps
CPU time 195.8 seconds
Started Aug 07 07:35:31 PM PDT 24
Finished Aug 07 07:38:47 PM PDT 24
Peak memory 260272 kb
Host smart-376f40e4-1954-4bac-9039-014a2f178561
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325
1313528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3251313528
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2044975398
Short name T18
Test name
Test status
Simulation time 1987504300 ps
CPU time 78.78 seconds
Started Aug 07 07:35:25 PM PDT 24
Finished Aug 07 07:36:43 PM PDT 24
Peak memory 260028 kb
Host smart-2161e302-738b-4374-bb90-04b2ec409227
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044975398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2044975398
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2900638300
Short name T969
Test name
Test status
Simulation time 15314400 ps
CPU time 13.54 seconds
Started Aug 07 07:35:42 PM PDT 24
Finished Aug 07 07:35:56 PM PDT 24
Peak memory 263888 kb
Host smart-d2ffc207-b1b2-4628-b99b-d4de846e46e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900638300 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2900638300
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.637867892
Short name T1031
Test name
Test status
Simulation time 64598900 ps
CPU time 110.6 seconds
Started Aug 07 07:35:22 PM PDT 24
Finished Aug 07 07:37:12 PM PDT 24
Peak memory 261392 kb
Host smart-142005dd-24cd-4b04-9fbb-a621de04d709
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637867892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.637867892
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.1392782332
Short name T936
Test name
Test status
Simulation time 14301542400 ps
CPU time 366.52 seconds
Started Aug 07 07:35:22 PM PDT 24
Finished Aug 07 07:41:29 PM PDT 24
Peak memory 263476 kb
Host smart-04b7316c-24c9-415a-a69e-7e3f199b07db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392782332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1392782332
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.4263417279
Short name T512
Test name
Test status
Simulation time 428992200 ps
CPU time 22.15 seconds
Started Aug 07 07:35:30 PM PDT 24
Finished Aug 07 07:35:53 PM PDT 24
Peak memory 259696 kb
Host smart-35c021dd-4a2c-4517-9672-5801d6a1ba02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263417279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.flash_ctrl_prog_reset.4263417279
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.2094995279
Short name T886
Test name
Test status
Simulation time 1674678600 ps
CPU time 1250.37 seconds
Started Aug 07 07:35:18 PM PDT 24
Finished Aug 07 07:56:09 PM PDT 24
Peak memory 286044 kb
Host smart-48f347ad-a396-4e3e-af0e-eeef8d84a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094995279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.2094995279
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2548948631
Short name T451
Test name
Test status
Simulation time 182914100 ps
CPU time 31.09 seconds
Started Aug 07 07:35:40 PM PDT 24
Finished Aug 07 07:36:11 PM PDT 24
Peak memory 275928 kb
Host smart-af39a357-74db-44ad-9b8d-6d312709169e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548948631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2548948631
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1988989045
Short name T208
Test name
Test status
Simulation time 608217600 ps
CPU time 109.5 seconds
Started Aug 07 07:35:31 PM PDT 24
Finished Aug 07 07:37:21 PM PDT 24
Peak memory 281996 kb
Host smart-6b5333bb-b251-44bd-884d-dde768e625f5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988989045 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.1988989045
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.417594110
Short name T212
Test name
Test status
Simulation time 731797300 ps
CPU time 178.04 seconds
Started Aug 07 07:35:33 PM PDT 24
Finished Aug 07 07:38:31 PM PDT 24
Peak memory 282124 kb
Host smart-27ce6df5-c0fa-4553-9c26-5ad95a9f77df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
417594110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.417594110
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.2071636176
Short name T661
Test name
Test status
Simulation time 3045623300 ps
CPU time 173.71 seconds
Started Aug 07 07:35:32 PM PDT 24
Finished Aug 07 07:38:26 PM PDT 24
Peak memory 295368 kb
Host smart-b04b9332-923f-43cd-9c7a-8ae5657003e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071636176 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2071636176
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.4250916702
Short name T478
Test name
Test status
Simulation time 6048759500 ps
CPU time 546.87 seconds
Started Aug 07 07:35:30 PM PDT 24
Finished Aug 07 07:44:37 PM PDT 24
Peak memory 314716 kb
Host smart-2d9cc5f7-ffbf-4f67-9ace-e42e26ff0690
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250916702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.4250916702
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.2002681469
Short name T907
Test name
Test status
Simulation time 1277454000 ps
CPU time 183.18 seconds
Started Aug 07 07:35:30 PM PDT 24
Finished Aug 07 07:38:34 PM PDT 24
Peak memory 295492 kb
Host smart-9d57c5fe-14e2-46b4-aafd-0ae187041887
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002681469 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.flash_ctrl_rw_serr.2002681469
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1386645711
Short name T396
Test name
Test status
Simulation time 5606076400 ps
CPU time 73.14 seconds
Started Aug 07 07:35:43 PM PDT 24
Finished Aug 07 07:36:56 PM PDT 24
Peak memory 263916 kb
Host smart-7ade18bd-2e4a-4eff-8fa6-5c228a94221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386645711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1386645711
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.994388163
Short name T1096
Test name
Test status
Simulation time 66069900 ps
CPU time 102.86 seconds
Started Aug 07 07:35:13 PM PDT 24
Finished Aug 07 07:36:56 PM PDT 24
Peak memory 277368 kb
Host smart-d796920d-2a06-4f7a-b5dc-b0d6d7668bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994388163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.994388163
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.2944252641
Short name T683
Test name
Test status
Simulation time 15987779900 ps
CPU time 235.33 seconds
Started Aug 07 07:35:30 PM PDT 24
Finished Aug 07 07:39:26 PM PDT 24
Peak memory 265424 kb
Host smart-777dc945-35c8-446b-bcf1-4eb40314c075
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944252641 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.2944252641
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.4189634118
Short name T411
Test name
Test status
Simulation time 14698900 ps
CPU time 15.88 seconds
Started Aug 07 07:42:51 PM PDT 24
Finished Aug 07 07:43:07 PM PDT 24
Peak memory 284696 kb
Host smart-49c92d38-60bc-4ce0-b7a2-aa911941e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189634118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4189634118
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.2273302613
Short name T109
Test name
Test status
Simulation time 39215500 ps
CPU time 132.75 seconds
Started Aug 07 07:42:48 PM PDT 24
Finished Aug 07 07:45:01 PM PDT 24
Peak memory 264312 kb
Host smart-c5a29897-d63c-4087-bdfc-f02852b386d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273302613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.2273302613
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.631670787
Short name T115
Test name
Test status
Simulation time 15146900 ps
CPU time 15.97 seconds
Started Aug 07 07:42:59 PM PDT 24
Finished Aug 07 07:43:15 PM PDT 24
Peak memory 275284 kb
Host smart-f66c9880-4425-45e3-ad85-5bb512247332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631670787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.631670787
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.867320069
Short name T580
Test name
Test status
Simulation time 75900700 ps
CPU time 133.19 seconds
Started Aug 07 07:42:59 PM PDT 24
Finished Aug 07 07:45:13 PM PDT 24
Peak memory 264308 kb
Host smart-54b81af4-9453-4f0e-9c95-a2abeac66b85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867320069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot
p_reset.867320069
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.3424362217
Short name T705
Test name
Test status
Simulation time 15891500 ps
CPU time 16.53 seconds
Started Aug 07 07:43:00 PM PDT 24
Finished Aug 07 07:43:17 PM PDT 24
Peak memory 283432 kb
Host smart-8dc9d50d-bbe8-44fc-8b26-666237ba4e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424362217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3424362217
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3202808559
Short name T498
Test name
Test status
Simulation time 336607100 ps
CPU time 134.68 seconds
Started Aug 07 07:43:00 PM PDT 24
Finished Aug 07 07:45:15 PM PDT 24
Peak memory 260172 kb
Host smart-54249935-ce51-4d96-90ab-d15b0f56fe56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202808559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3202808559
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1600060601
Short name T517
Test name
Test status
Simulation time 16672000 ps
CPU time 16.43 seconds
Started Aug 07 07:42:59 PM PDT 24
Finished Aug 07 07:43:15 PM PDT 24
Peak memory 283480 kb
Host smart-34a1c149-d643-4fc3-b2dd-6f949eb9ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600060601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1600060601
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3866406126
Short name T13
Test name
Test status
Simulation time 40104100 ps
CPU time 133.48 seconds
Started Aug 07 07:42:58 PM PDT 24
Finished Aug 07 07:45:12 PM PDT 24
Peak memory 261460 kb
Host smart-a87db6d7-1803-4c23-953f-a1d4b2d3b7a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866406126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3866406126
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2209048922
Short name T966
Test name
Test status
Simulation time 16910500 ps
CPU time 13.64 seconds
Started Aug 07 07:43:03 PM PDT 24
Finished Aug 07 07:43:17 PM PDT 24
Peak memory 284648 kb
Host smart-45f8fc17-f5e5-4a5c-b54e-b7c2b8269e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209048922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2209048922
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.640140480
Short name T998
Test name
Test status
Simulation time 14161000 ps
CPU time 16.09 seconds
Started Aug 07 07:42:59 PM PDT 24
Finished Aug 07 07:43:15 PM PDT 24
Peak memory 275360 kb
Host smart-e446ea0c-55ea-4ea3-8460-75c374106377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640140480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.640140480
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2089073547
Short name T701
Test name
Test status
Simulation time 56102900 ps
CPU time 131.28 seconds
Started Aug 07 07:42:58 PM PDT 24
Finished Aug 07 07:45:10 PM PDT 24
Peak memory 260264 kb
Host smart-e8fe46b1-484b-4d93-8c58-e9dad21876c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089073547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2089073547
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.1318869996
Short name T552
Test name
Test status
Simulation time 21733900 ps
CPU time 16.21 seconds
Started Aug 07 07:43:02 PM PDT 24
Finished Aug 07 07:43:18 PM PDT 24
Peak memory 283364 kb
Host smart-2ea1114a-0929-4f4f-a4a8-91214c2cd815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318869996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1318869996
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3394423384
Short name T623
Test name
Test status
Simulation time 72416400 ps
CPU time 132 seconds
Started Aug 07 07:42:58 PM PDT 24
Finished Aug 07 07:45:11 PM PDT 24
Peak memory 260072 kb
Host smart-af4b4903-1574-4352-9473-123738bfb773
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394423384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3394423384
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.709896518
Short name T434
Test name
Test status
Simulation time 45220000 ps
CPU time 15.92 seconds
Started Aug 07 07:43:01 PM PDT 24
Finished Aug 07 07:43:17 PM PDT 24
Peak memory 283368 kb
Host smart-095241d3-d098-4a0f-83be-8d4c20e4d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709896518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.709896518
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1973780382
Short name T891
Test name
Test status
Simulation time 138365600 ps
CPU time 114.05 seconds
Started Aug 07 07:43:01 PM PDT 24
Finished Aug 07 07:44:55 PM PDT 24
Peak memory 260364 kb
Host smart-f0e6e9e7-325a-4bbb-b079-f9d95a7cd584
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973780382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1973780382
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.4045673454
Short name T2
Test name
Test status
Simulation time 42765200 ps
CPU time 15.97 seconds
Started Aug 07 07:43:13 PM PDT 24
Finished Aug 07 07:43:29 PM PDT 24
Peak memory 283448 kb
Host smart-861cb3c3-ee6f-48a8-a97c-9f6a27406a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045673454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.4045673454
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.2472940575
Short name T1098
Test name
Test status
Simulation time 284327000 ps
CPU time 132.47 seconds
Started Aug 07 07:43:01 PM PDT 24
Finished Aug 07 07:45:13 PM PDT 24
Peak memory 261292 kb
Host smart-5070debc-7644-4b49-b76d-496c01f20e2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472940575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.2472940575
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.3726167561
Short name T679
Test name
Test status
Simulation time 13089200 ps
CPU time 15.81 seconds
Started Aug 07 07:43:11 PM PDT 24
Finished Aug 07 07:43:27 PM PDT 24
Peak memory 284732 kb
Host smart-70cc63f4-9717-4c98-bd57-18a625ddd5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726167561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3726167561
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.3711794082
Short name T957
Test name
Test status
Simulation time 185811400 ps
CPU time 134.18 seconds
Started Aug 07 07:43:11 PM PDT 24
Finished Aug 07 07:45:25 PM PDT 24
Peak memory 260136 kb
Host smart-f918e395-b7ea-41ee-8101-8ed0af561e55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711794082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.3711794082
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3442903124
Short name T602
Test name
Test status
Simulation time 120358700 ps
CPU time 13.77 seconds
Started Aug 07 07:36:18 PM PDT 24
Finished Aug 07 07:36:32 PM PDT 24
Peak memory 258428 kb
Host smart-9a882966-206e-456f-9a80-054d7cccb770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442903124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
442903124
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2060940060
Short name T986
Test name
Test status
Simulation time 15763700 ps
CPU time 15.84 seconds
Started Aug 07 07:36:16 PM PDT 24
Finished Aug 07 07:36:32 PM PDT 24
Peak memory 284760 kb
Host smart-3870f5d9-a3bc-4bb5-9856-12d03fbc0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060940060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2060940060
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.3839936398
Short name T79
Test name
Test status
Simulation time 10192800 ps
CPU time 22.46 seconds
Started Aug 07 07:36:07 PM PDT 24
Finished Aug 07 07:36:29 PM PDT 24
Peak memory 274984 kb
Host smart-1359d05c-f3f0-4a6b-8330-d841931d1725
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839936398 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.3839936398
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.140940144
Short name T905
Test name
Test status
Simulation time 46017350800 ps
CPU time 2460.84 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 08:17:00 PM PDT 24
Peak memory 263052 kb
Host smart-46e494ba-7d84-424e-996a-db29cb6d547c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=140940144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.140940144
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.1731470316
Short name T611
Test name
Test status
Simulation time 1999201800 ps
CPU time 828.3 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:49:47 PM PDT 24
Peak memory 270720 kb
Host smart-7e40dbb0-70dc-4b3e-8296-4bb6fd294749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731470316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1731470316
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.2077838779
Short name T59
Test name
Test status
Simulation time 477458700 ps
CPU time 26.38 seconds
Started Aug 07 07:36:00 PM PDT 24
Finished Aug 07 07:36:26 PM PDT 24
Peak memory 262612 kb
Host smart-46d22ef2-dbaf-4d0c-8bd3-f4bdd44fef41
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077838779 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_fetch_code.2077838779
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3890435743
Short name T151
Test name
Test status
Simulation time 10012576600 ps
CPU time 103.1 seconds
Started Aug 07 07:36:17 PM PDT 24
Finished Aug 07 07:38:01 PM PDT 24
Peak memory 285548 kb
Host smart-ba652b47-4253-4cc7-9fd1-a7d48f55cdaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890435743 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3890435743
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.854118648
Short name T159
Test name
Test status
Simulation time 48076700 ps
CPU time 13.5 seconds
Started Aug 07 07:36:16 PM PDT 24
Finished Aug 07 07:36:30 PM PDT 24
Peak memory 265008 kb
Host smart-b27c9511-96c0-482c-a65e-fe0fea7d54aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854118648 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.854118648
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1649021049
Short name T1014
Test name
Test status
Simulation time 130173202300 ps
CPU time 926.59 seconds
Started Aug 07 07:35:50 PM PDT 24
Finished Aug 07 07:51:16 PM PDT 24
Peak memory 264332 kb
Host smart-cafb29b3-5451-4fbc-afbe-e2edf50cdccb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649021049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.1649021049
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.3818020887
Short name T412
Test name
Test status
Simulation time 7345197500 ps
CPU time 102.89 seconds
Started Aug 07 07:35:51 PM PDT 24
Finished Aug 07 07:37:34 PM PDT 24
Peak memory 260748 kb
Host smart-3aa80c19-c104-48f1-92f2-ba6e50361eff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818020887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.3818020887
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.1433612741
Short name T953
Test name
Test status
Simulation time 1958149300 ps
CPU time 175.02 seconds
Started Aug 07 07:35:59 PM PDT 24
Finished Aug 07 07:38:54 PM PDT 24
Peak memory 293508 kb
Host smart-3a0abc7e-9b89-449e-8520-d62f2e2d9f29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433612741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.1433612741
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1579414074
Short name T752
Test name
Test status
Simulation time 6086586600 ps
CPU time 138.15 seconds
Started Aug 07 07:36:09 PM PDT 24
Finished Aug 07 07:38:27 PM PDT 24
Peak memory 293444 kb
Host smart-497d1d57-35ab-4c5e-a8b8-10b6e1ae5994
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579414074 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1579414074
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.1474924391
Short name T715
Test name
Test status
Simulation time 4257047500 ps
CPU time 67.77 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:37:06 PM PDT 24
Peak memory 265400 kb
Host smart-0cb7f97f-f7d1-4a4d-8d60-906fbbeb4867
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474924391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.1474924391
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3440510341
Short name T685
Test name
Test status
Simulation time 97432768600 ps
CPU time 261.77 seconds
Started Aug 07 07:36:07 PM PDT 24
Finished Aug 07 07:40:29 PM PDT 24
Peak memory 260524 kb
Host smart-a4b23ee3-0935-4033-a1d9-52a18b0004f9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344
0510341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3440510341
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.702521536
Short name T122
Test name
Test status
Simulation time 3481523200 ps
CPU time 72.44 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:37:11 PM PDT 24
Peak memory 261128 kb
Host smart-e2fd5647-80eb-4294-9e8f-dcf4ec5f13fe
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702521536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.702521536
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.338347508
Short name T910
Test name
Test status
Simulation time 16984700 ps
CPU time 13.73 seconds
Started Aug 07 07:36:15 PM PDT 24
Finished Aug 07 07:36:29 PM PDT 24
Peak memory 265024 kb
Host smart-1ad0306b-7164-413b-aa66-a9ca5deba234
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338347508 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.338347508
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3436045817
Short name T127
Test name
Test status
Simulation time 108089413000 ps
CPU time 938.54 seconds
Started Aug 07 07:35:52 PM PDT 24
Finished Aug 07 07:51:31 PM PDT 24
Peak memory 275016 kb
Host smart-69341192-56cf-4d4c-a40f-106ebbc3d59c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436045817 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.3436045817
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.777282534
Short name T1089
Test name
Test status
Simulation time 43938800 ps
CPU time 129.25 seconds
Started Aug 07 07:35:52 PM PDT 24
Finished Aug 07 07:38:02 PM PDT 24
Peak memory 261228 kb
Host smart-56f94b38-1602-4dd5-a672-efc2ab17f61d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777282534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp
_reset.777282534
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3962839430
Short name T684
Test name
Test status
Simulation time 952742500 ps
CPU time 293.13 seconds
Started Aug 07 07:35:52 PM PDT 24
Finished Aug 07 07:40:45 PM PDT 24
Peak memory 263420 kb
Host smart-ad9838eb-80e0-423c-80c1-1f776b940cbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962839430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3962839430
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.182890627
Short name T549
Test name
Test status
Simulation time 304152700 ps
CPU time 14.93 seconds
Started Aug 07 07:36:09 PM PDT 24
Finished Aug 07 07:36:24 PM PDT 24
Peak memory 265392 kb
Host smart-93636c12-4428-4f6d-9c75-a512c2e807c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182890627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.flash_ctrl_prog_reset.182890627
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.2278272018
Short name T1106
Test name
Test status
Simulation time 678250400 ps
CPU time 796.86 seconds
Started Aug 07 07:35:48 PM PDT 24
Finished Aug 07 07:49:05 PM PDT 24
Peak memory 283056 kb
Host smart-d71579a9-7ea1-4469-b98e-3c11748ddfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278272018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2278272018
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1706530509
Short name T214
Test name
Test status
Simulation time 255159300 ps
CPU time 36.59 seconds
Started Aug 07 07:36:06 PM PDT 24
Finished Aug 07 07:36:43 PM PDT 24
Peak memory 275088 kb
Host smart-655b84f5-6a43-47d6-9266-1a3f0fef1bdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706530509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1706530509
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.2804812681
Short name T466
Test name
Test status
Simulation time 3709819800 ps
CPU time 140.75 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:38:19 PM PDT 24
Peak memory 282092 kb
Host smart-497102e8-75d8-48af-8575-6059b36b2a18
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804812681 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.2804812681
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.3936909174
Short name T926
Test name
Test status
Simulation time 1325423900 ps
CPU time 170.31 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:38:49 PM PDT 24
Peak memory 282064 kb
Host smart-e8cd89c8-69a4-4c3f-8d4f-053a3a656b92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3936909174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.3936909174
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.470611763
Short name T1048
Test name
Test status
Simulation time 13230793400 ps
CPU time 567.62 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:45:26 PM PDT 24
Peak memory 314744 kb
Host smart-fec4a57e-4686-4f3e-a811-c4e3080525d5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470611763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_rw.470611763
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.1047137241
Short name T56
Test name
Test status
Simulation time 6649390200 ps
CPU time 280.43 seconds
Started Aug 07 07:35:58 PM PDT 24
Finished Aug 07 07:40:39 PM PDT 24
Peak memory 291896 kb
Host smart-612e3e7d-4ee0-43f5-85d0-193f9860f05d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047137241 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_derr.1047137241
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.688794754
Short name T566
Test name
Test status
Simulation time 83555300 ps
CPU time 31.88 seconds
Started Aug 07 07:36:10 PM PDT 24
Finished Aug 07 07:36:42 PM PDT 24
Peak memory 273876 kb
Host smart-c26ab0de-3d56-43fd-90aa-ba580a4ef0fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688794754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_rw_evict.688794754
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3910369635
Short name T1026
Test name
Test status
Simulation time 66015000 ps
CPU time 28.64 seconds
Started Aug 07 07:36:07 PM PDT 24
Finished Aug 07 07:36:36 PM PDT 24
Peak memory 273928 kb
Host smart-5b550d4a-2c2c-40d4-a2b3-0715699652d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910369635 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3910369635
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1758464223
Short name T386
Test name
Test status
Simulation time 7436213600 ps
CPU time 70.69 seconds
Started Aug 07 07:36:10 PM PDT 24
Finished Aug 07 07:37:20 PM PDT 24
Peak memory 264280 kb
Host smart-20a7ef15-7ded-4311-bc0b-3b63914b0ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758464223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1758464223
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1680653442
Short name T736
Test name
Test status
Simulation time 31159900 ps
CPU time 78.9 seconds
Started Aug 07 07:35:49 PM PDT 24
Finished Aug 07 07:37:08 PM PDT 24
Peak memory 276924 kb
Host smart-695cc3c7-7d22-44b0-960b-316dd8a18609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680653442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1680653442
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.778289203
Short name T508
Test name
Test status
Simulation time 4674673500 ps
CPU time 182.01 seconds
Started Aug 07 07:35:59 PM PDT 24
Finished Aug 07 07:39:01 PM PDT 24
Peak memory 260224 kb
Host smart-6c50705d-2e58-4799-8334-bb50bf33e694
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778289203 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_wo.778289203
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2650034072
Short name T730
Test name
Test status
Simulation time 31250000 ps
CPU time 13.65 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:37:24 PM PDT 24
Peak memory 258432 kb
Host smart-034ee666-3c79-40cd-a599-3e55fe0eb9dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650034072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
650034072
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1760981476
Short name T430
Test name
Test status
Simulation time 34748000 ps
CPU time 16.19 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:37:26 PM PDT 24
Peak memory 284620 kb
Host smart-1ddb1b55-7b5a-415f-a945-2ab4abbf1052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760981476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1760981476
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.2140580309
Short name T453
Test name
Test status
Simulation time 12859600 ps
CPU time 22.23 seconds
Started Aug 07 07:37:09 PM PDT 24
Finished Aug 07 07:37:32 PM PDT 24
Peak memory 273728 kb
Host smart-c16f51a7-d4ba-4fbf-a737-c2bd23f76bc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140580309 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.2140580309
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.352556039
Short name T575
Test name
Test status
Simulation time 4696791400 ps
CPU time 2243.02 seconds
Started Aug 07 07:36:26 PM PDT 24
Finished Aug 07 08:13:50 PM PDT 24
Peak memory 263072 kb
Host smart-c371f577-e9dd-493b-a2e2-af7b2aa2a48e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=352556039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.352556039
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.2145880978
Short name T890
Test name
Test status
Simulation time 1337052900 ps
CPU time 876.51 seconds
Started Aug 07 07:36:27 PM PDT 24
Finished Aug 07 07:51:04 PM PDT 24
Peak memory 273656 kb
Host smart-7db97a94-3a4c-437a-bf3b-5c336708bd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145880978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2145880978
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.3219422261
Short name T4
Test name
Test status
Simulation time 362557800 ps
CPU time 21.09 seconds
Started Aug 07 07:36:28 PM PDT 24
Finished Aug 07 07:36:49 PM PDT 24
Peak memory 262864 kb
Host smart-cf98af85-be43-4716-8276-8182ad937ff7
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219422261 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_fetch_code.3219422261
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.125059426
Short name T614
Test name
Test status
Simulation time 10019946100 ps
CPU time 65.38 seconds
Started Aug 07 07:37:09 PM PDT 24
Finished Aug 07 07:38:15 PM PDT 24
Peak memory 276556 kb
Host smart-009f777f-8529-4f7c-b290-c932ad8e6751
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125059426 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.125059426
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1552749782
Short name T984
Test name
Test status
Simulation time 45176400 ps
CPU time 13.6 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:37:24 PM PDT 24
Peak memory 258648 kb
Host smart-abb6ad74-48b6-4037-a95a-51b505b9a3c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552749782 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1552749782
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.3010600099
Short name T938
Test name
Test status
Simulation time 10131832100 ps
CPU time 50.98 seconds
Started Aug 07 07:36:15 PM PDT 24
Finished Aug 07 07:37:06 PM PDT 24
Peak memory 263452 kb
Host smart-06542de8-a60a-4047-837a-3a313a2ee4f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010600099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.3010600099
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.4122975918
Short name T1081
Test name
Test status
Simulation time 5418413000 ps
CPU time 205.94 seconds
Started Aug 07 07:36:25 PM PDT 24
Finished Aug 07 07:39:51 PM PDT 24
Peak memory 291812 kb
Host smart-05691745-32a3-45ea-a862-1dc13fba0edc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122975918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.4122975918
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1033746045
Short name T321
Test name
Test status
Simulation time 24145250200 ps
CPU time 279.1 seconds
Started Aug 07 07:36:26 PM PDT 24
Finished Aug 07 07:41:05 PM PDT 24
Peak memory 290116 kb
Host smart-6040db78-5432-43bb-9e44-4b46efc0a60a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033746045 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1033746045
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3406717085
Short name T627
Test name
Test status
Simulation time 9138282100 ps
CPU time 74.25 seconds
Started Aug 07 07:36:30 PM PDT 24
Finished Aug 07 07:37:45 PM PDT 24
Peak memory 265444 kb
Host smart-498a70e4-ca98-499f-b61f-0dddd57d3fe9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406717085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3406717085
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3283614809
Short name T839
Test name
Test status
Simulation time 64325205000 ps
CPU time 178.71 seconds
Started Aug 07 07:36:27 PM PDT 24
Finished Aug 07 07:39:26 PM PDT 24
Peak memory 260540 kb
Host smart-6f6cdb1e-e016-4c86-8ccf-6eb78b935952
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328
3614809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3283614809
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.121599129
Short name T619
Test name
Test status
Simulation time 1696242500 ps
CPU time 64.75 seconds
Started Aug 07 07:36:28 PM PDT 24
Finished Aug 07 07:37:33 PM PDT 24
Peak memory 263556 kb
Host smart-277fbc8c-3b90-47dc-a6a2-c8589e80e400
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121599129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.121599129
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.4269269185
Short name T289
Test name
Test status
Simulation time 15534300 ps
CPU time 13.59 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:37:24 PM PDT 24
Peak memory 260324 kb
Host smart-8fb22cd5-0adb-40d3-a962-e641f0af70c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269269185 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.4269269185
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3785945086
Short name T144
Test name
Test status
Simulation time 11736607500 ps
CPU time 553.91 seconds
Started Aug 07 07:36:26 PM PDT 24
Finished Aug 07 07:45:40 PM PDT 24
Peak memory 274680 kb
Host smart-f5bebe5a-d537-47e7-a639-8b4296a44a45
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785945086 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.3785945086
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.2428475426
Short name T940
Test name
Test status
Simulation time 41423500 ps
CPU time 131.57 seconds
Started Aug 07 07:36:27 PM PDT 24
Finished Aug 07 07:38:38 PM PDT 24
Peak memory 265504 kb
Host smart-3f049337-0b0b-4540-9c60-7aa5ecc21b7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428475426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.2428475426
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.906394432
Short name T754
Test name
Test status
Simulation time 70358800 ps
CPU time 69.56 seconds
Started Aug 07 07:36:21 PM PDT 24
Finished Aug 07 07:37:31 PM PDT 24
Peak memory 263452 kb
Host smart-94f890a6-1daf-4e1e-b9f1-086699d9e3f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906394432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.906394432
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3600132207
Short name T407
Test name
Test status
Simulation time 31594000 ps
CPU time 13.61 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:37:23 PM PDT 24
Peak memory 259052 kb
Host smart-6a528160-a97e-49dc-bd7b-3c2728e267d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600132207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.flash_ctrl_prog_reset.3600132207
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2232518655
Short name T145
Test name
Test status
Simulation time 1512319100 ps
CPU time 1520.39 seconds
Started Aug 07 07:36:15 PM PDT 24
Finished Aug 07 08:01:35 PM PDT 24
Peak memory 290288 kb
Host smart-4cd2115e-f5e4-4bf1-b138-fc7c4c84db4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232518655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2232518655
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.2624808868
Short name T335
Test name
Test status
Simulation time 159117200 ps
CPU time 34.61 seconds
Started Aug 07 07:37:09 PM PDT 24
Finished Aug 07 07:37:44 PM PDT 24
Peak memory 275916 kb
Host smart-77504722-05b4-458b-a4be-626db7f42fb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624808868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.2624808868
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.1240473975
Short name T1029
Test name
Test status
Simulation time 2014770600 ps
CPU time 128.95 seconds
Started Aug 07 07:36:26 PM PDT 24
Finished Aug 07 07:38:35 PM PDT 24
Peak memory 289460 kb
Host smart-c4066913-5354-4e22-aae2-8c6296180fc9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240473975 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.1240473975
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.677208554
Short name T252
Test name
Test status
Simulation time 580319500 ps
CPU time 147.85 seconds
Started Aug 07 07:36:31 PM PDT 24
Finished Aug 07 07:38:59 PM PDT 24
Peak memory 282104 kb
Host smart-c4091b84-2422-4fbe-ad92-af3259f586ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
677208554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.677208554
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.463856324
Short name T796
Test name
Test status
Simulation time 3459512100 ps
CPU time 582.34 seconds
Started Aug 07 07:36:29 PM PDT 24
Finished Aug 07 07:46:11 PM PDT 24
Peak memory 310120 kb
Host smart-758b748a-e739-4864-b153-94e975df609d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463856324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_rw.463856324
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.426706249
Short name T913
Test name
Test status
Simulation time 1903912700 ps
CPU time 237.76 seconds
Started Aug 07 07:36:30 PM PDT 24
Finished Aug 07 07:40:28 PM PDT 24
Peak memory 282236 kb
Host smart-278a82b6-4d6f-49d8-ab9b-fd6223529364
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426706249 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_derr.426706249
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.4163323432
Short name T574
Test name
Test status
Simulation time 38704100 ps
CPU time 31.04 seconds
Started Aug 07 07:37:11 PM PDT 24
Finished Aug 07 07:37:42 PM PDT 24
Peak memory 273932 kb
Host smart-8ed7032a-eb0d-4076-a9b9-a5b1e045855b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163323432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.4163323432
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1511289282
Short name T967
Test name
Test status
Simulation time 28067000 ps
CPU time 32.09 seconds
Started Aug 07 07:37:11 PM PDT 24
Finished Aug 07 07:37:44 PM PDT 24
Peak memory 274048 kb
Host smart-719537eb-5e80-46e6-b06f-eba455d31941
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511289282 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1511289282
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.4040966725
Short name T658
Test name
Test status
Simulation time 7075870200 ps
CPU time 238.12 seconds
Started Aug 07 07:36:26 PM PDT 24
Finished Aug 07 07:40:24 PM PDT 24
Peak memory 295508 kb
Host smart-fea9dbdd-6a08-4c89-955e-8ac379b6a491
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040966725 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.flash_ctrl_rw_serr.4040966725
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.1060536352
Short name T384
Test name
Test status
Simulation time 4292137000 ps
CPU time 77.99 seconds
Started Aug 07 07:37:10 PM PDT 24
Finished Aug 07 07:38:28 PM PDT 24
Peak memory 264404 kb
Host smart-1cfe13ce-393c-4d5a-b358-ca694af17e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060536352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1060536352
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.1608992701
Short name T767
Test name
Test status
Simulation time 24837000 ps
CPU time 124.04 seconds
Started Aug 07 07:36:18 PM PDT 24
Finished Aug 07 07:38:23 PM PDT 24
Peak memory 277528 kb
Host smart-e1fb912f-bbe0-4524-a0c3-99b1385bf738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608992701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1608992701
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2965784012
Short name T472
Test name
Test status
Simulation time 10912765700 ps
CPU time 154.07 seconds
Started Aug 07 07:36:25 PM PDT 24
Finished Aug 07 07:39:00 PM PDT 24
Peak memory 265524 kb
Host smart-7fb9bc53-aa9e-428a-88b5-4a500fa1c7da
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965784012 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2965784012
Directory /workspace/9.flash_ctrl_wo/latest
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