Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24544314	1		T1	505		T2	130		T3	66
full_word	7406177	1		T2	1		T3	40		T4	349

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31950141	1		T1	505		T2	131		T3	106
auto[TlIntgErrCmd]	120	1		T75	4		T77	5		T112	8
auto[TlIntgErrData]	113	1		T75	8		T77	5		T112	7
auto[TlIntgErrBoth]	117	1		T75	8		T77	10		T112	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27497945	1		T1	497		T2	123		T3	59
auto[1]	4452546	1		T1	8		T2	8		T3	47

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23828962	1		T1	497		T2	123		T3	58
auto[TlIntgErrNone]	partial	auto[1]	715032	1		T1	8		T2	7		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	3668836	1		T3	1		T4	214		T19	1
auto[TlIntgErrNone]	full_word	auto[1]	3737311	1		T2	1		T3	39		T4	135
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T75	2		T112	4		T236	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1		T75	1		T77	3		T112	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T112	1		T233	1		T269	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1		T75	1		T77	2		T112	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T75	1		T77	2		T112	5
auto[TlIntgErrData]	partial	auto[1]	58	1		T75	6		T77	2		T112	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T75	1		T357	3		T358	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T77	1		T354	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1		T75	2		T77	5		T112	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T75	6		T77	4		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T77	1		T268	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T273	1		T356	1		T360	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18358	1		T75	19		T77	18		T113	995
full_word	3787598	1		T4	20		T5	16422		T7	41599

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3805623	1		T4	20		T5	16422		T7	41599
auto[TlIntgErrCmd]	102	1		T75	5		T77	8		T112	6
auto[TlIntgErrData]	143	1		T75	11		T77	6		T112	10
auto[TlIntgErrBoth]	88	1		T75	4		T77	4		T112	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3783176	1		T4	20		T5	16422		T7	41599
auto[1]	22780	1		T75	12		T77	10		T113	1273

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1220	1		T113	58		T206	2		T207	20
auto[TlIntgErrNone]	partial	auto[1]	16833	1		T113	937		T206	41		T207	412
auto[TlIntgErrNone]	full_word	auto[0]	3781816	1		T4	20		T5	16422		T7	41599
auto[TlIntgErrNone]	full_word	auto[1]	5754	1		T113	336		T206	26		T207	188
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T75	1		T77	2		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T75	4		T77	6		T112	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T112	1		T269	2		T354	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T354	1		T359	2		T358	1
auto[TlIntgErrData]	partial	auto[0]	66	1		T75	5		T77	5		T112	6
auto[TlIntgErrData]	partial	auto[1]	63	1		T75	5		T77	1		T112	3
auto[TlIntgErrData]	full_word	auto[0]	7	1		T75	1		T356	1		T355	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T112	1		T268	1		T273	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T75	1		T77	1		T112	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T75	3		T77	3		T112	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T361	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T112	1		T273	1		T269	1