Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1503149704	1499842024	0	0
CheckNGreaterZero_A	4152	4152	0	0
GntImpliesReady_A	1503149704	409510714	0	0
GntImpliesValid_A	1503149704	409510714	0	0
GrantKnown_A	1503149704	1499842024	0	0
IdxKnown_A	1503149704	1499842024	0	0
IndexIsCorrect_A	1503149704	409510714	0	0
NoReadyValidNoGrant_A	1503149704	168582678	0	0
Priority_A	1503149704	433616550	0	0
ReadyAndValidImplyGrant_A	1503149704	409510714	0	0
ReqAndReadyImplyGrant_A	1503149704	409510714	0	0
ReqImpliesValid_A	1503149704	433616550	0	0
ValidKnown_A	1503149704	1499842024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	1499842024	0	0
T1	13972	11080	0	0
T2	11436	8952	0	0
T3	4668	3692	0	0
T4	20540	20112	0	0
T5	2280464	2279780	0	0
T6	952416	952032	0	0
T7	1352728	1352504	0	0
T19	10280	9916	0	0
T20	14452	11636	0	0
T21	20892	20608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4152	4152	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	409510714	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	32914	0	0
T6	952416	414160	0	0
T7	1352728	460192	0	0
T9	0	164028	0	0
T10	0	173316	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	409510714	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	32914	0	0
T6	952416	414160	0	0
T7	1352728	460192	0	0
T9	0	164028	0	0
T10	0	173316	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	1499842024	0	0
T1	13972	11080	0	0
T2	11436	8952	0	0
T3	4668	3692	0	0
T4	20540	20112	0	0
T5	2280464	2279780	0	0
T6	952416	952032	0	0
T7	1352728	1352504	0	0
T19	10280	9916	0	0
T20	14452	11636	0	0
T21	20892	20608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	1499842024	0	0
T1	13972	11080	0	0
T2	11436	8952	0	0
T3	4668	3692	0	0
T4	20540	20112	0	0
T5	2280464	2279780	0	0
T6	952416	952032	0	0
T7	1352728	1352504	0	0
T19	10280	9916	0	0
T20	14452	11636	0	0
T21	20892	20608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	409510714	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	32914	0	0
T6	952416	414160	0	0
T7	1352728	460192	0	0
T9	0	164028	0	0
T10	0	173316	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	168582678	0	0
T1	6986	1436	0	0
T2	5718	608	0	0
T3	2334	536	0	0
T4	20540	1402	0	0
T5	2280464	1190308	0	0
T6	952416	256	0	0
T7	1352728	171338	0	0
T10	0	82862	0	0
T19	10280	256	0	0
T20	14452	928	0	0
T21	20892	256	0	0
T22	140534	0	0	0
T24	0	66110	0	0
T28	0	346	0	0
T29	659672	0	0	0
T43	0	1746	0	0
T49	0	20	0	0
T51	0	53234	0	0
T52	0	12	0	0
T66	2202	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	433616550	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	506644	0	0
T6	952416	414160	0	0
T7	1352728	561738	0	0
T9	0	164028	0	0
T10	0	206334	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	409510714	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	32914	0	0
T6	952416	414160	0	0
T7	1352728	460192	0	0
T9	0	164028	0	0
T10	0	173316	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	409510714	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	32914	0	0
T6	952416	414160	0	0
T7	1352728	460192	0	0
T9	0	164028	0	0
T10	0	173316	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	433616550	0	0
T1	6986	360	0	0
T2	5718	152	0	0
T3	2334	134	0	0
T4	20540	4668	0	0
T5	2280464	506644	0	0
T6	952416	414160	0	0
T7	1352728	561738	0	0
T9	0	164028	0	0
T10	0	206334	0	0
T19	10280	64	0	0
T20	14452	282	0	0
T21	20892	64	0	0
T22	140534	0	0	0
T28	0	664	0	0
T29	659672	0	0	0
T43	0	600	0	0
T49	0	12	0	0
T52	0	8	0	0
T66	2202	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1503149704	1499842024	0	0
T1	13972	11080	0	0
T2	11436	8952	0	0
T3	4668	3692	0	0
T4	20540	20112	0	0
T5	2280464	2279780	0	0
T6	952416	952032	0	0
T7	1352728	1352504	0	0
T19	10280	9916	0	0
T20	14452	11636	0	0
T21	20892	20608	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375787426	374960506	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375787426	108585985	0	0
GntImpliesValid_A	375787426	108585985	0	0
GrantKnown_A	375787426	374960506	0	0
IdxKnown_A	375787426	374960506	0	0
IndexIsCorrect_A	375787426	108585985	0	0
NoReadyValidNoGrant_A	375787426	44093263	0	0
Priority_A	375787426	114636760	0	0
ReadyAndValidImplyGrant_A	375787426	108585985	0	0
ReqAndReadyImplyGrant_A	375787426	108585985	0	0
ReqImpliesValid_A	375787426	114636760	0	0
ValidKnown_A	375787426	374960506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585985	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585985	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585985	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	44093263	0	0
T1	3493	718	0	0
T2	2859	304	0	0
T3	1167	268	0	0
T4	5135	649	0	0
T5	570116	299787	0	0
T6	238104	128	0	0
T7	338182	45968	0	0
T19	2570	128	0	0
T20	3613	464	0	0
T21	5223	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	114636760	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	133923	0	0
T6	238104	126458	0	0
T7	338182	162373	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585985	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585985	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	114636760	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	133923	0	0
T6	238104	126458	0	0
T7	338182	162373	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375787426	374960506	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375787426	108585907	0	0
GntImpliesValid_A	375787426	108585907	0	0
GrantKnown_A	375787426	374960506	0	0
IdxKnown_A	375787426	374960506	0	0
IndexIsCorrect_A	375787426	108585907	0	0
NoReadyValidNoGrant_A	375787426	44093263	0	0
Priority_A	375787426	114636682	0	0
ReadyAndValidImplyGrant_A	375787426	108585907	0	0
ReqAndReadyImplyGrant_A	375787426	108585907	0	0
ReqImpliesValid_A	375787426	114636682	0	0
ValidKnown_A	375787426	374960506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585907	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585907	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585907	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	44093263	0	0
T1	3493	718	0	0
T2	2859	304	0	0
T3	1167	268	0	0
T4	5135	649	0	0
T5	570116	299787	0	0
T6	238104	128	0	0
T7	338182	45968	0	0
T19	2570	128	0	0
T20	3613	464	0	0
T21	5223	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	114636682	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	133923	0	0
T6	238104	126458	0	0
T7	338182	162373	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585907	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	108585907	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	8411	0	0
T6	238104	126458	0	0
T7	338182	134872	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	114636682	0	0
T1	3493	180	0	0
T2	2859	76	0	0
T3	1167	67	0	0
T4	5135	1275	0	0
T5	570116	133923	0	0
T6	238104	126458	0	0
T7	338182	162373	0	0
T19	2570	32	0	0
T20	3613	141	0	0
T21	5223	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T6,T7

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375787426	374960506	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375787426	96169411	0	0
GntImpliesValid_A	375787426	96169411	0	0
GrantKnown_A	375787426	374960506	0	0
IdxKnown_A	375787426	374960506	0	0
IndexIsCorrect_A	375787426	96169411	0	0
NoReadyValidNoGrant_A	375787426	40198076	0	0
Priority_A	375787426	102171554	0	0
ReadyAndValidImplyGrant_A	375787426	96169411	0	0
ReqAndReadyImplyGrant_A	375787426	96169411	0	0
ReqImpliesValid_A	375787426	102171554	0	0
ValidKnown_A	375787426	374960506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	40198076	0	0
T4	5135	52	0	0
T5	570116	295367	0	0
T6	238104	0	0	0
T7	338182	39701	0	0
T10	0	41431	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T24	0	33055	0	0
T28	0	173	0	0
T29	329836	0	0	0
T43	0	873	0	0
T49	0	10	0	0
T51	0	26617	0	0
T52	0	6	0	0
T66	1101	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	102171554	0	0
T4	5135	1059	0	0
T5	570116	119399	0	0
T6	238104	80622	0	0
T7	338182	118496	0	0
T9	0	82014	0	0
T10	0	103167	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	102171554	0	0
T4	5135	1059	0	0
T5	570116	119399	0	0
T6	238104	80622	0	0
T7	338182	118496	0	0
T9	0	82014	0	0
T10	0	103167	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T6,T7

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375787426	374960506	0	0
CheckNGreaterZero_A	1038	1038	0	0
GntImpliesReady_A	375787426	96169411	0	0
GntImpliesValid_A	375787426	96169411	0	0
GrantKnown_A	375787426	374960506	0	0
IdxKnown_A	375787426	374960506	0	0
IndexIsCorrect_A	375787426	96169411	0	0
NoReadyValidNoGrant_A	375787426	40198076	0	0
Priority_A	375787426	102171554	0	0
ReadyAndValidImplyGrant_A	375787426	96169411	0	0
ReqAndReadyImplyGrant_A	375787426	96169411	0	0
ReqImpliesValid_A	375787426	102171554	0	0
ValidKnown_A	375787426	374960506	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	40198076	0	0
T4	5135	52	0	0
T5	570116	295367	0	0
T6	238104	0	0	0
T7	338182	39701	0	0
T10	0	41431	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T24	0	33055	0	0
T28	0	173	0	0
T29	329836	0	0	0
T43	0	873	0	0
T49	0	10	0	0
T51	0	26617	0	0
T52	0	6	0	0
T66	1101	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	102171554	0	0
T4	5135	1059	0	0
T5	570116	119399	0	0
T6	238104	80622	0	0
T7	338182	118496	0	0
T9	0	82014	0	0
T10	0	103167	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	96169411	0	0
T4	5135	1059	0	0
T5	570116	8046	0	0
T6	238104	80622	0	0
T7	338182	95224	0	0
T9	0	82014	0	0
T10	0	86658	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	102171554	0	0
T4	5135	1059	0	0
T5	570116	119399	0	0
T6	238104	80622	0	0
T7	338182	118496	0	0
T9	0	82014	0	0
T10	0	103167	0	0
T19	2570	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T28	0	332	0	0
T29	329836	0	0	0
T43	0	300	0	0
T49	0	6	0	0
T52	0	4	0	0
T66	1101	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0