Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T182,T13,T23
1	0	Covered	T182,T13,T23

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T22
1	1	Covered	T182,T13,T23

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T182,T13,T23
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T22,T49,T198

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T22
1	0	Covered	T6,T7,T22
1	1	Covered	T6,T7,T22

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T22
1	1	Covered	T22,T49,T198

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14
1	Covered	T22,T49,T198

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T22
1	0	Covered	T6,T7,T22
1	1	Covered	T6,T7,T22

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T6,T7,T22

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T22
1	0	Covered	T6,T7,T22
1	1	Covered	T22,T49,T198

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14
1	Covered	T22,T49,T198

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T22,T10,T49
1	Covered	T6,T7,T10

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T6,T7,T22

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T6,T7,T22

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T22
1	1	Covered	T6,T7,T22

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T22
1	1	0	Covered	T6,T7,T22
1	1	1	Covered	T6,T7,T22

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T6,T7,T10
StCalcMask	237	Covered	T6,T7,T10
StCalcPlainEcc	215	Covered	T6,T7,T22
StDisabled	193	Covered	T1,T2,T3
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T6,T7,T22
StPostPack	218	Covered	T22,T49,T198
StPrePack	195	Covered	T22,T49,T198
StReqFlash	237	Covered	T6,T7,T22
StScrambleData	244	Covered	T6,T7,T10
StWaitFlash	270	Covered	T6,T7,T22

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T6,T7,T10
StCalcMask->StScrambleData	244	Covered	T6,T7,T10
StCalcPlainEcc->StCalcMask	237	Covered	T6,T7,T10
StCalcPlainEcc->StReqFlash	237	Covered	T22,T10,T49
StIdle->StDisabled	193	Covered	T1,T2,T3
StIdle->StPackData	197	Covered	T6,T7,T22
StIdle->StPrePack	195	Covered	T22,T49,T198
StPackData->StCalcPlainEcc	215	Covered	T6,T7,T22
StPackData->StPostPack	218	Covered	T22,T49,T198
StPostPack->StCalcPlainEcc	231	Covered	T22,T49,T198
StPrePack->StPackData	205	Covered	T22,T49,T198
StReqFlash->StIdle	273	Covered	T6,T7,T22
StReqFlash->StWaitFlash	270	Covered	T6,T7,T22
StScrambleData->StCalcEcc	252	Covered	T6,T7,T10
StWaitFlash->StIdle	280	Covered	T6,T7,T22

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T22
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T22
0	0	1	Covered	T6,T7,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T49,T198
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T49,T198
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T49,T198
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T22,T49,T198
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T7,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T22,T10,T49
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T7,T10
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T7,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T7,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T6,T7,T10
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T6,T7,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T7,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T6,T7,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T7,T22
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T22
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T22
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T7,T22
0	0	1	-	-	Covered	T6,T7,T10
0	0	0	1	-	Covered	T6,T7,T10
0	0	0	0	1	Covered	T6,T7,T22
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T22
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	751574852	2436004	0	0
PostPackRule_A	751574852	1929	0	0
PrePackRule_A	751574852	1331	0	0
WidthCheck_A	2076	2076	0	0
u_state_regs_A	751574852	749921012	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751574852	2436004	0	0
T6	476208	1441	0	0
T7	676364	1715	0	0
T8	1498	1	0	0
T9	0	1401	0	0
T10	677944	1692	0	0
T15	2398	0	0	0
T20	7226	0	0	0
T21	10446	0	0	0
T22	140534	4	0	0
T24	0	901	0	0
T29	659672	0	0	0
T49	0	2	0	0
T51	0	222	0	0
T65	0	864	0	0
T66	2202	0	0	0
T68	0	32768	0	0
T69	0	1	0	0
T145	0	556	0	0
T198	0	2	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751574852	1929	0	0
T8	749	0	0	0
T9	236385	0	0	0
T10	338972	0	0	0
T15	1199	0	0	0
T22	70267	3	0	0
T25	0	3	0	0
T28	4809	0	0	0
T30	2622	0	0	0
T35	205166	0	0	0
T43	5858	0	0	0
T44	1920	0	0	0
T49	1909	2	0	0
T50	1942	0	0	0
T52	1449	0	0	0
T56	190164	0	0	0
T57	44752	0	0	0
T78	0	11	0	0
T79	0	2	0	0
T80	0	43	0	0
T93	162283	0	0	0
T95	0	61	0	0
T96	0	40	0	0
T110	1269	0	0	0
T128	0	20	0	0
T143	0	6	0	0
T149	2177	0	0	0
T150	929	0	0	0
T162	0	5	0	0
T198	1897	1	0	0
T221	0	1	0	0
T222	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751574852	1331	0	0
T8	749	0	0	0
T9	236385	0	0	0
T10	338972	0	0	0
T15	1199	0	0	0
T22	70267	3	0	0
T25	0	2	0	0
T28	4809	0	0	0
T30	2622	0	0	0
T35	205166	0	0	0
T43	5858	0	0	0
T44	1920	0	0	0
T49	1909	2	0	0
T50	1942	0	0	0
T52	1449	0	0	0
T56	190164	0	0	0
T57	44752	0	0	0
T78	0	4	0	0
T79	0	2	0	0
T80	0	31	0	0
T93	162283	0	0	0
T95	0	51	0	0
T96	0	26	0	0
T110	1269	0	0	0
T128	0	11	0	0
T143	0	3	0	0
T149	2177	0	0	0
T150	929	0	0	0
T162	0	5	0	0
T198	1897	1	0	0
T221	0	3	0	0
T223	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2076	2076	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	751574852	749921012	0	0
T1	6986	5540	0	0
T2	5718	4476	0	0
T3	2334	1846	0	0
T4	10270	10056	0	0
T5	1140232	1139890	0	0
T6	476208	476016	0	0
T7	676364	676252	0	0
T19	5140	4958	0	0
T20	7226	5818	0	0
T21	10446	10304	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T182,T13,T23
1	0	Covered	T182,T13,T23

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T22
1	1	Covered	T182,T13,T23

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T182,T13,T23
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T22,T49,T162

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T22
1	0	Covered	T6,T7,T22
1	1	Covered	T6,T7,T22

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T22
1	1	Covered	T22,T49,T162

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14
1	Covered	T22,T49,T162

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T22
1	0	Covered	T6,T7,T22
1	1	Covered	T6,T7,T22

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T6,T7,T22

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T22
1	0	Covered	T6,T7,T22
1	1	Covered	T22,T49,T162

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14
1	Covered	T22,T49,T162

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T22,T10,T49
1	Covered	T6,T7,T10

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T6,T7,T22

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T6,T7,T22

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T22
1	1	Covered	T6,T7,T22

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T22
1	1	0	Covered	T6,T7,T22
1	1	1	Covered	T6,T7,T22

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T22

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T6,T7,T10
StCalcMask	237	Covered	T6,T7,T10
StCalcPlainEcc	215	Covered	T6,T7,T22
StDisabled	193	Covered	T1,T2,T3
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T6,T7,T22
StPostPack	218	Covered	T22,T49,T162
StPrePack	195	Covered	T22,T49,T162
StReqFlash	237	Covered	T6,T7,T22
StScrambleData	244	Covered	T6,T7,T10
StWaitFlash	270	Covered	T6,T7,T22

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T6,T7,T10
StCalcMask->StScrambleData	244	Covered	T6,T7,T10
StCalcPlainEcc->StCalcMask	237	Covered	T6,T7,T10
StCalcPlainEcc->StReqFlash	237	Covered	T22,T10,T49
StIdle->StDisabled	193	Covered	T1,T2,T3
StIdle->StPackData	197	Covered	T6,T7,T22
StIdle->StPrePack	195	Covered	T22,T49,T162
StPackData->StCalcPlainEcc	215	Covered	T6,T7,T22
StPackData->StPostPack	218	Covered	T22,T49,T162
StPostPack->StCalcPlainEcc	231	Covered	T22,T49,T162
StPrePack->StPackData	205	Covered	T22,T49,T162
StReqFlash->StIdle	273	Covered	T6,T7,T22
StReqFlash->StWaitFlash	270	Covered	T6,T7,T22
StScrambleData->StCalcEcc	252	Covered	T6,T7,T10
StWaitFlash->StIdle	280	Covered	T6,T7,T22

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T22
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T22
0	0	1	Covered	T6,T7,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T49,T162
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T49,T162
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T22,T49,T162
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T22
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T22,T49,T162
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T7,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T22,T10,T49
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T7,T10
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T7,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T7,T10
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T6,T7,T10
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T6,T7,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T7,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T6,T7,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T7,T22
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T22
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T22
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T7,T22
0	0	1	-	-	Covered	T6,T7,T10
0	0	0	1	-	Covered	T6,T7,T10
0	0	0	0	1	Covered	T6,T7,T22
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T22
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	375787426	1239281	0	0
PostPackRule_A	375787426	914	0	0
PrePackRule_A	375787426	647	0	0
WidthCheck_A	1038	1038	0	0
u_state_regs_A	375787426	374960506	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	1239281	0	0
T6	238104	847	0	0
T7	338182	1007	0	0
T8	749	1	0	0
T9	0	817	0	0
T10	338972	1065	0	0
T15	1199	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	4	0	0
T24	0	575	0	0
T29	329836	0	0	0
T49	0	2	0	0
T51	0	63	0	0
T66	1101	0	0	0
T69	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	914	0	0
T8	749	0	0	0
T9	236385	0	0	0
T10	338972	0	0	0
T15	1199	0	0	0
T22	70267	3	0	0
T25	0	3	0	0
T28	4809	0	0	0
T43	5858	0	0	0
T49	1909	2	0	0
T52	1449	0	0	0
T78	0	5	0	0
T79	0	1	0	0
T80	0	16	0	0
T95	0	29	0	0
T110	1269	0	0	0
T143	0	3	0	0
T162	0	3	0	0
T222	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	647	0	0
T8	749	0	0	0
T9	236385	0	0	0
T10	338972	0	0	0
T15	1199	0	0	0
T22	70267	3	0	0
T25	0	2	0	0
T28	4809	0	0	0
T43	5858	0	0	0
T49	1909	2	0	0
T52	1449	0	0	0
T78	0	3	0	0
T79	0	1	0	0
T80	0	13	0	0
T95	0	22	0	0
T110	1269	0	0	0
T143	0	1	0	0
T162	0	5	0	0
T221	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T23,T224
1	0	Covered	T13,T23,T224

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T13,T23,T224

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T23,T224
1	0	Covered	T4,T5,T6

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T198,T162,T78

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T198,T78,T79

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14
1	Covered	T198,T78,T79

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T6,T7,T10

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T6,T7,T10
1	1	Covered	T198,T162,T78

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14
1	Covered	T198,T162,T78

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T10,T51,T198
1	Covered	T6,T7,T9

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T6,T7,T10

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T6,T7,T10

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T43
1	0	Covered	T6,T7,T9
1	1	Covered	T6,T7,T9

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T43
1	0	Covered	T6,T7,T9
1	1	Covered	T6,T7,T9

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T10
1	1	0	Covered	T6,T7,T10
1	1	1	Covered	T6,T7,T10

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T6,T7,T9
StCalcMask	237	Covered	T6,T7,T9
StCalcPlainEcc	215	Covered	T6,T7,T10
StDisabled	193	Covered	T1,T2,T3
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T6,T7,T10
StPostPack	218	Covered	T198,T162,T78
StPrePack	195	Covered	T198,T78,T79
StReqFlash	237	Covered	T6,T7,T10
StScrambleData	244	Covered	T6,T7,T9
StWaitFlash	270	Covered	T6,T7,T10

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T6,T7,T9
StCalcMask->StScrambleData	244	Covered	T6,T7,T9
StCalcPlainEcc->StCalcMask	237	Covered	T6,T7,T9
StCalcPlainEcc->StReqFlash	237	Covered	T10,T51,T198
StIdle->StDisabled	193	Covered	T1,T2,T3
StIdle->StPackData	197	Covered	T6,T7,T10
StIdle->StPrePack	195	Covered	T198,T78,T79
StPackData->StCalcPlainEcc	215	Covered	T6,T7,T10
StPackData->StPostPack	218	Covered	T198,T162,T78
StPostPack->StCalcPlainEcc	231	Covered	T198,T162,T78
StPrePack->StPackData	205	Covered	T198,T78,T79
StReqFlash->StIdle	273	Covered	T6,T7,T10
StReqFlash->StWaitFlash	270	Covered	T6,T7,T10
StScrambleData->StCalcEcc	252	Covered	T6,T7,T9
StWaitFlash->StIdle	280	Covered	T6,T7,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T10
0	1	Covered	T4,T5,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T10
0	0	1	Covered	T6,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T198,T78,T79
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T198,T78,T79
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T198,T162,T78
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T198,T162,T78
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T7,T9
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T51,T198
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T7,T9
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T7,T9
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T7,T9
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T6,T7,T9
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T6,T7,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T7,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T6,T7,T10
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T7,T10
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T7,T10
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T7,T10
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T7,T10
0	0	1	-	-	Covered	T6,T7,T9
0	0	0	1	-	Covered	T6,T7,T9
0	0	0	0	1	Covered	T6,T7,T10
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	375787426	1196723	0	0
PostPackRule_A	375787426	1015	0	0
PrePackRule_A	375787426	684	0	0
WidthCheck_A	1038	1038	0	0
u_state_regs_A	375787426	374960506	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	1196723	0	0
T6	238104	594	0	0
T7	338182	708	0	0
T8	749	0	0	0
T9	0	584	0	0
T10	338972	627	0	0
T15	1199	0	0	0
T20	3613	0	0	0
T21	5223	0	0	0
T22	70267	0	0	0
T24	0	326	0	0
T29	329836	0	0	0
T51	0	159	0	0
T65	0	864	0	0
T66	1101	0	0	0
T68	0	32768	0	0
T145	0	556	0	0
T198	0	2	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	1015	0	0
T30	2622	0	0	0
T35	205166	0	0	0
T44	1920	0	0	0
T50	1942	0	0	0
T56	190164	0	0	0
T57	44752	0	0	0
T78	0	6	0	0
T79	0	1	0	0
T80	0	27	0	0
T93	162283	0	0	0
T95	0	32	0	0
T96	0	40	0	0
T128	0	20	0	0
T143	0	3	0	0
T149	2177	0	0	0
T150	929	0	0	0
T162	0	2	0	0
T198	1897	1	0	0
T221	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	684	0	0
T30	2622	0	0	0
T35	205166	0	0	0
T44	1920	0	0	0
T50	1942	0	0	0
T56	190164	0	0	0
T57	44752	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	18	0	0
T93	162283	0	0	0
T95	0	29	0	0
T96	0	26	0	0
T128	0	11	0	0
T143	0	2	0	0
T149	2177	0	0	0
T150	929	0	0	0
T198	1897	1	0	0
T221	0	2	0	0
T223	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1038	1038	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375787426	374960506	0	0
T1	3493	2770	0	0
T2	2859	2238	0	0
T3	1167	923	0	0
T4	5135	5028	0	0
T5	570116	569945	0	0
T6	238104	238008	0	0
T7	338182	338126	0	0
T19	2570	2479	0	0
T20	3613	2909	0	0
T21	5223	5152	0	0