Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 93.75 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 87.50 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 3 13 81.25


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 3 13 81.25 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 16228 1 T79 7 T80 9 T117 17
full_word 3831375 1 T5 4 T7 16923 T6 10


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3847338 1 T5 4 T7 16923 T6 10
auto[TlIntgErrCmd] 78 1 T79 2 T80 4 T117 5
auto[TlIntgErrData] 94 1 T79 3 T80 1 T117 9
auto[TlIntgErrBoth] 93 1 T79 3 T80 5 T117 5


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3826338 1 T5 4 T7 16923 T6 10
auto[1] 21265 1 T79 5 T80 6 T117 13


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 3 13 81.25 3


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd] , auto[TlIntgErrData] , auto[TlIntgErrBoth]] [full_word] [auto[0]] -- -- 3


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1015 1 T240 59 T241 5 T242 23
auto[TlIntgErrNone] partial auto[1] 14967 1 T240 740 T241 68 T242 479
auto[TlIntgErrNone] full_word auto[0] 3825235 1 T5 4 T7 16923 T6 10
auto[TlIntgErrNone] full_word auto[1] 6121 1 T240 259 T241 17 T242 78
auto[TlIntgErrCmd] partial auto[0] 27 1 T80 2 T117 2 T259 5
auto[TlIntgErrCmd] partial auto[1] 44 1 T79 2 T80 2 T117 2
auto[TlIntgErrCmd] full_word auto[1] 7 1 T117 1 T361 1 T363 1
auto[TlIntgErrData] partial auto[0] 36 1 T80 1 T117 3 T259 1
auto[TlIntgErrData] partial auto[1] 51 1 T79 2 T117 6 T259 1
auto[TlIntgErrData] full_word auto[1] 7 1 T79 1 T289 1 T363 1
auto[TlIntgErrBoth] partial auto[0] 25 1 T79 3 T80 1 T117 1
auto[TlIntgErrBoth] partial auto[1] 63 1 T80 3 T117 3 T259 2
auto[TlIntgErrBoth] full_word auto[1] 5 1 T80 1 T117 1 T295 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 24292861 1 T1 64 T2 64 T3 277
full_word 7686546 1 T1 81 T2 43 T3 72


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 31979127 1 T1 145 T2 107 T3 349
auto[TlIntgErrCmd] 81 1 T79 1 T80 6 T117 9
auto[TlIntgErrData] 112 1 T79 3 T80 2 T117 7
auto[TlIntgErrBoth] 87 1 T79 6 T80 2 T117 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27602176 1 T1 57 T2 60 T3 277
auto[1] 4377231 1 T1 88 T2 47 T3 72


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 23634994 1 T1 57 T2 59 T3 271
auto[TlIntgErrNone] partial auto[1] 657602 1 T1 7 T2 5 T3 6
auto[TlIntgErrNone] full_word auto[0] 3967059 1 T2 1 T3 6 T4 6
auto[TlIntgErrNone] full_word auto[1] 3719472 1 T1 81 T2 42 T3 66
auto[TlIntgErrCmd] partial auto[0] 35 1 T80 5 T117 4 T294 1
auto[TlIntgErrCmd] partial auto[1] 42 1 T79 1 T80 1 T117 4
auto[TlIntgErrCmd] full_word auto[0] 2 1 T117 1 T364 1 - -
auto[TlIntgErrCmd] full_word auto[1] 2 1 T290 1 T363 1 - -
auto[TlIntgErrData] partial auto[0] 50 1 T79 1 T80 1 T117 4
auto[TlIntgErrData] partial auto[1] 57 1 T79 2 T80 1 T117 3
auto[TlIntgErrData] full_word auto[0] 1 1 T365 1 - - - -
auto[TlIntgErrData] full_word auto[1] 4 1 T289 1 T290 2 T362 1
auto[TlIntgErrBoth] partial auto[0] 31 1 T79 2 T80 1 T117 1
auto[TlIntgErrBoth] partial auto[1] 50 1 T79 3 T117 1 T259 2
auto[TlIntgErrBoth] full_word auto[0] 4 1 T80 1 T117 2 T290 1
auto[TlIntgErrBoth] full_word auto[1] 2 1 T79 1 T295 1 - -

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