Module Definition
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Module : flash_phy_rd_buf_dep
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.17 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.60 100.00 90.39 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T5,T7 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T5,T7
110Not Covered
111CoveredT1,T5,T7 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T6
11CoveredT1,T5,T7 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T5,T7
Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T7 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T7 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T5,T7
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T5,T7
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T5,T7
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T5,T7
0 - 0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 802241832 6840530 0 0
BufferDepRsp_A 802241832 800580754 0 0
BufferIncrOverFlow_A 802241832 6840545 0 0
DepBufferRspOrder_A 802241833 16680894 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 802241832 6840530 0 0
T1 12580 500 0 0
T2 2606 0 0 0
T3 3284 0 0 0
T4 3784 0 0 0
T5 1708 4 0 0
T6 2680 10 0 0
T7 244312 43467 0 0
T13 770194 0 0 0
T19 12584 188 0 0
T20 6654 120 0 0
T21 0 13 0 0
T25 0 219 0 0
T29 0 512 0 0
T41 0 14 0 0
T44 0 166 0 0
T63 0 2 0 0
T64 0 2824 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 802241832 800580754 0 0
T1 12580 11610 0 0
T2 2606 2090 0 0
T3 3284 3112 0 0
T4 3784 3642 0 0
T5 1708 1546 0 0
T6 2680 2520 0 0
T7 244312 244284 0 0
T13 770194 770164 0 0
T19 12584 12306 0 0
T20 6654 6354 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 802241832 6840545 0 0
T1 12580 500 0 0
T2 2606 0 0 0
T3 3284 0 0 0
T4 3784 0 0 0
T5 1708 4 0 0
T6 2680 10 0 0
T7 244312 43467 0 0
T13 770194 0 0 0
T19 12584 188 0 0
T20 6654 120 0 0
T21 0 13 0 0
T25 0 219 0 0
T29 0 512 0 0
T41 0 14 0 0
T44 0 166 0 0
T63 0 2 0 0
T64 0 2824 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 802241833 16680894 0 0
T1 12580 692 0 0
T2 2606 65 0 0
T3 3284 32 0 0
T4 3784 32 0 0
T5 1708 36 0 0
T6 2680 42 0 0
T7 244312 43501 0 0
T13 770194 263744 0 0
T14 0 131072 0 0
T19 12584 252 0 0
T20 6654 184 0 0
T21 0 11 0 0
T44 0 89 0 0
T63 0 2 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T7,T6 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T7,T6
110Not Covered
111CoveredT1,T7,T6 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T7,T6
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T19
11CoveredT1,T7,T6 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T7,T6
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T6,T19
10CoveredT1,T2,T3
11CoveredT1,T7,T6
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T7,T6 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T7,T6 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T7,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T7,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T7,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T7,T6
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 401120916 4018820 0 0
BufferDepRsp_A 401120916 400290377 0 0
BufferIncrOverFlow_A 401120916 4018828 0 0
DepBufferRspOrder_A 401120916 9290700 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 4018820 0 0
T1 6290 300 0 0
T2 1303 0 0 0
T3 1642 0 0 0
T4 1892 0 0 0
T5 854 0 0 0
T6 1340 10 0 0
T7 122156 18843 0 0
T13 385097 0 0 0
T19 6292 143 0 0
T20 3327 106 0 0
T21 0 2 0 0
T25 0 174 0 0
T29 0 512 0 0
T44 0 77 0 0
T64 0 2824 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 400290377 0 0
T1 6290 5805 0 0
T2 1303 1045 0 0
T3 1642 1556 0 0
T4 1892 1821 0 0
T5 854 773 0 0
T6 1340 1260 0 0
T7 122156 122142 0 0
T13 385097 385082 0 0
T19 6292 6153 0 0
T20 3327 3177 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 4018828 0 0
T1 6290 300 0 0
T2 1303 0 0 0
T3 1642 0 0 0
T4 1892 0 0 0
T5 854 0 0 0
T6 1340 10 0 0
T7 122156 18843 0 0
T13 385097 0 0 0
T19 6292 143 0 0
T20 3327 106 0 0
T21 0 2 0 0
T25 0 174 0 0
T29 0 512 0 0
T44 0 77 0 0
T64 0 2824 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 9290700 0 0
T1 6290 492 0 0
T2 1303 65 0 0
T3 1642 32 0 0
T4 1892 32 0 0
T5 854 32 0 0
T6 1340 42 0 0
T7 122156 18877 0 0
T13 385097 132672 0 0
T19 6292 207 0 0
T20 3327 170 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT13,T14,T121
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T5,T7 

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T5,T7
110Not Covered
111CoveredT1,T5,T7 

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T63
11CoveredT1,T5,T7 

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT1,T5,T63
10CoveredT1,T2,T3
11CoveredT1,T5,T7
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T7 



	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T5,T7 



	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T5,T7
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T1,T5,T7
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T5,T7
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T5,T7
0 - 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 401120916 2821710 0 0
BufferDepRsp_A 401120916 400290377 0 0
BufferIncrOverFlow_A 401120916 2821717 0 0
DepBufferRspOrder_A 401120917 7390194 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 2821710 0 0
T1 6290 200 0 0
T2 1303 0 0 0
T3 1642 0 0 0
T4 1892 0 0 0
T5 854 4 0 0
T6 1340 0 0 0
T7 122156 24624 0 0
T13 385097 0 0 0
T19 6292 45 0 0
T20 3327 14 0 0
T21 0 11 0 0
T25 0 45 0 0
T41 0 14 0 0
T44 0 89 0 0
T63 0 2 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 400290377 0 0
T1 6290 5805 0 0
T2 1303 1045 0 0
T3 1642 1556 0 0
T4 1892 1821 0 0
T5 854 773 0 0
T6 1340 1260 0 0
T7 122156 122142 0 0
T13 385097 385082 0 0
T19 6292 6153 0 0
T20 3327 3177 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120916 2821717 0 0
T1 6290 200 0 0
T2 1303 0 0 0
T3 1642 0 0 0
T4 1892 0 0 0
T5 854 4 0 0
T6 1340 0 0 0
T7 122156 24624 0 0
T13 385097 0 0 0
T19 6292 45 0 0
T20 3327 14 0 0
T21 0 11 0 0
T25 0 45 0 0
T41 0 14 0 0
T44 0 89 0 0
T63 0 2 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 401120917 7390194 0 0
T1 6290 200 0 0
T2 1303 0 0 0
T3 1642 0 0 0
T4 1892 0 0 0
T5 854 4 0 0
T6 1340 0 0 0
T7 122156 24624 0 0
T13 385097 131072 0 0
T14 0 131072 0 0
T19 6292 45 0 0
T20 3327 14 0 0
T21 0 11 0 0
T44 0 89 0 0
T63 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%