Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1604483664	1601161508	0	0
CheckNGreaterZero_A	4196	4196	0	0
GntImpliesReady_A	1604483664	399817301	0	0
GntImpliesValid_A	1604483664	399817301	0	0
GrantKnown_A	1604483664	1601161508	0	0
IdxKnown_A	1604483664	1601161508	0	0
IndexIsCorrect_A	1604483664	399817301	0	0
NoReadyValidNoGrant_A	1604483664	175165540	0	0
Priority_A	1604483664	423599733	0	0
ReadyAndValidImplyGrant_A	1604483664	399817301	0	0
ReqAndReadyImplyGrant_A	1604483664	399817301	0	0
ReqImpliesValid_A	1604483664	423599733	0	0
ValidKnown_A	1604483664	1601161508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	1601161508	0	0
T1	25160	23220	0	0
T2	5212	4180	0	0
T3	6568	6224	0	0
T4	7568	7284	0	0
T5	3416	3092	0	0
T6	5360	5040	0	0
T7	488624	488568	0	0
T13	1540388	1540328	0	0
T19	25168	24612	0	0
T20	13308	12708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4196	4196	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T13	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	399817301	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	87002	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	399817301	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	87002	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	1601161508	0	0
T1	25160	23220	0	0
T2	5212	4180	0	0
T3	6568	6224	0	0
T4	7568	7284	0	0
T5	3416	3092	0	0
T6	5360	5040	0	0
T7	488624	488568	0	0
T13	1540388	1540328	0	0
T19	25168	24612	0	0
T20	13308	12708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	1601161508	0	0
T1	25160	23220	0	0
T2	5212	4180	0	0
T3	6568	6224	0	0
T4	7568	7284	0	0
T5	3416	3092	0	0
T6	5360	5040	0	0
T7	488624	488568	0	0
T13	1540388	1540328	0	0
T19	25168	24612	0	0
T20	13308	12708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	399817301	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	87002	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	175165540	0	0
T1	25160	3292	0	0
T2	5212	520	0	0
T3	6568	256	0	0
T4	7568	256	0	0
T5	3416	276	0	0
T6	5360	286	0	0
T7	488624	2666516	0	0
T13	1540388	2109952	0	0
T14	0	1048576	0	0
T19	25168	1366	0	0
T20	13308	998	0	0
T21	0	34	0	0
T44	0	428	0	0
T63	0	10	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	423599733	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	582856	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	399817301	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	87002	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	399817301	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	87002	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	423599733	0	0
T1	25160	1384	0	0
T2	5212	130	0	0
T3	6568	952	0	0
T4	7568	952	0	0
T5	3416	72	0	0
T6	5360	84	0	0
T7	488624	582856	0	0
T13	1540388	514652	0	0
T14	0	255794	0	0
T19	25168	7264	0	0
T20	13308	856	0	0
T21	0	338	0	0
T63	0	4	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1604483664	1601161508	0	0
T1	25160	23220	0	0
T2	5212	4180	0	0
T3	6568	6224	0	0
T4	7568	7284	0	0
T5	3416	3092	0	0
T6	5360	5040	0	0
T7	488624	488568	0	0
T13	1540388	1540328	0	0
T19	25168	24612	0	0
T20	13308	12708	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401120916	400290377	0	0
CheckNGreaterZero_A	1049	1049	0	0
GntImpliesReady_A	401120916	109312138	0	0
GntImpliesValid_A	401120916	109312138	0	0
GrantKnown_A	401120916	400290377	0	0
IdxKnown_A	401120916	400290377	0	0
IndexIsCorrect_A	401120916	109312138	0	0
NoReadyValidNoGrant_A	401120916	46306402	0	0
Priority_A	401120916	115223683	0	0
ReadyAndValidImplyGrant_A	401120916	109312138	0	0
ReqAndReadyImplyGrant_A	401120916	109312138	0	0
ReqImpliesValid_A	401120916	115223683	0	0
ValidKnown_A	401120916	400290377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312138	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312138	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312138	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	46306402	0	0
T1	6290	1296	0	0
T2	1303	260	0	0
T3	1642	128	0	0
T4	1892	128	0	0
T5	854	128	0	0
T6	1340	143	0	0
T7	122156	587862	0	0
T13	385097	530688	0	0
T19	6292	573	0	0
T20	3327	475	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	115223683	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	135911	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312138	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312138	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	115223683	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	135911	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401120916	400290377	0	0
CheckNGreaterZero_A	1049	1049	0	0
GntImpliesReady_A	401120916	109312053	0	0
GntImpliesValid_A	401120916	109312053	0	0
GrantKnown_A	401120916	400290377	0	0
IdxKnown_A	401120916	400290377	0	0
IndexIsCorrect_A	401120916	109312053	0	0
NoReadyValidNoGrant_A	401120916	46306402	0	0
Priority_A	401120916	115223598	0	0
ReadyAndValidImplyGrant_A	401120916	109312053	0	0
ReqAndReadyImplyGrant_A	401120916	109312053	0	0
ReqImpliesValid_A	401120916	115223598	0	0
ValidKnown_A	401120916	400290377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312053	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312053	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312053	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	46306402	0	0
T1	6290	1296	0	0
T2	1303	260	0	0
T3	1642	128	0	0
T4	1892	128	0	0
T5	854	128	0	0
T6	1340	143	0	0
T7	122156	587862	0	0
T13	385097	530688	0	0
T19	6292	573	0	0
T20	3327	475	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	115223598	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	135911	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312053	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	109312053	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	18877	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	115223598	0	0
T1	6290	492	0	0
T2	1303	65	0	0
T3	1642	32	0	0
T4	1892	476	0	0
T5	854	32	0	0
T6	1340	42	0	0
T7	122156	135911	0	0
T13	385097	129429	0	0
T19	6292	2287	0	0
T20	3327	353	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T19
1	0	Covered	T1,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T3,T7,T19
1	1	Covered	T1,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T3,T7,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401120916	400290377	0	0
CheckNGreaterZero_A	1049	1049	0	0
GntImpliesReady_A	401120916	90596555	0	0
GntImpliesValid_A	401120916	90596555	0	0
GrantKnown_A	401120916	400290377	0	0
IdxKnown_A	401120916	400290377	0	0
IndexIsCorrect_A	401120916	90596555	0	0
NoReadyValidNoGrant_A	401120916	41276368	0	0
Priority_A	401120916	96576226	0	0
ReadyAndValidImplyGrant_A	401120916	90596555	0	0
ReqAndReadyImplyGrant_A	401120916	90596555	0	0
ReqImpliesValid_A	401120916	96576226	0	0
ValidKnown_A	401120916	400290377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	41276368	0	0
T1	6290	350	0	0
T2	1303	0	0	0
T3	1642	0	0	0
T4	1892	0	0	0
T5	854	10	0	0
T6	1340	0	0	0
T7	122156	745396	0	0
T13	385097	524288	0	0
T14	0	524288	0	0
T19	6292	110	0	0
T20	3327	24	0	0
T21	0	17	0	0
T44	0	214	0	0
T63	0	5	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	96576226	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	155517	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	96576226	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	155517	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T19
1	0	Covered	T1,T5,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T3,T7,T19
1	1	Covered	T1,T5,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T3,T7,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	401120916	400290377	0	0
CheckNGreaterZero_A	1049	1049	0	0
GntImpliesReady_A	401120916	90596555	0	0
GntImpliesValid_A	401120916	90596555	0	0
GrantKnown_A	401120916	400290377	0	0
IdxKnown_A	401120916	400290377	0	0
IndexIsCorrect_A	401120916	90596555	0	0
NoReadyValidNoGrant_A	401120916	41276368	0	0
Priority_A	401120916	96576226	0	0
ReadyAndValidImplyGrant_A	401120916	90596555	0	0
ReqAndReadyImplyGrant_A	401120916	90596555	0	0
ReqImpliesValid_A	401120916	96576226	0	0
ValidKnown_A	401120916	400290377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1049	1049	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	41276368	0	0
T1	6290	350	0	0
T2	1303	0	0	0
T3	1642	0	0	0
T4	1892	0	0	0
T5	854	10	0	0
T6	1340	0	0	0
T7	122156	745396	0	0
T13	385097	524288	0	0
T14	0	524288	0	0
T19	6292	110	0	0
T20	3327	24	0	0
T21	0	17	0	0
T44	0	214	0	0
T63	0	5	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	96576226	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	155517	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	90596555	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	24624	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	96576226	0	0
T1	6290	200	0	0
T2	1303	0	0	0
T3	1642	444	0	0
T4	1892	0	0	0
T5	854	4	0	0
T6	1340	0	0	0
T7	122156	155517	0	0
T13	385097	127897	0	0
T14	0	127897	0	0
T19	6292	1345	0	0
T20	3327	75	0	0
T21	0	169	0	0
T63	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401120916	400290377	0	0
T1	6290	5805	0	0
T2	1303	1045	0	0
T3	1642	1556	0	0
T4	1892	1821	0	0
T5	854	773	0	0
T6	1340	1260	0	0
T7	122156	122142	0	0
T13	385097	385082	0	0
T19	6292	6153	0	0
T20	3327	3177	0	0