Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	404098015	2811	0	0
addr_rd_A	404098015	2302	0	0
bank0_info0_page_cfg_0_rd_A	404098015	3147	0	0
bank0_info0_page_cfg_1_rd_A	404098015	3161	0	0
bank0_info0_page_cfg_2_rd_A	404098015	2722	0	0
bank0_info0_page_cfg_3_rd_A	404098015	2135	0	0
bank0_info0_page_cfg_4_rd_A	404098015	2543	0	0
bank0_info0_page_cfg_5_rd_A	404098015	2914	0	0
bank0_info0_page_cfg_6_rd_A	404098015	3122	0	0
bank0_info0_page_cfg_7_rd_A	404098015	2483	0	0
bank0_info0_page_cfg_8_rd_A	404098015	2648	0	0
bank0_info0_page_cfg_9_rd_A	404098015	2970	0	0
bank0_info0_regwen_0_rd_A	404098015	1438	0	0
bank0_info0_regwen_1_rd_A	404098015	1236	0	0
bank0_info0_regwen_2_rd_A	404098015	2208	0	0
bank0_info0_regwen_3_rd_A	404098015	1750	0	0
bank0_info0_regwen_4_rd_A	404098015	1798	0	0
bank0_info0_regwen_5_rd_A	404098015	1891	0	0
bank0_info0_regwen_6_rd_A	404098015	1861	0	0
bank0_info0_regwen_7_rd_A	404098015	2302	0	0
bank0_info0_regwen_8_rd_A	404098015	2452	0	0
bank0_info0_regwen_9_rd_A	404098015	1821	0	0
bank0_info1_page_cfg_rd_A	404098015	3182	0	0
bank0_info1_regwen_rd_A	404098015	2422	0	0
bank0_info2_page_cfg_0_rd_A	404098015	3083	0	0
bank0_info2_page_cfg_1_rd_A	404098015	3121	0	0
bank0_info2_regwen_0_rd_A	404098015	2347	0	0
bank0_info2_regwen_1_rd_A	404098015	2204	0	0
bank1_info0_page_cfg_0_rd_A	404098015	2696	0	0
bank1_info0_page_cfg_1_rd_A	404098015	2655	0	0
bank1_info0_page_cfg_2_rd_A	404098015	3211	0	0
bank1_info0_page_cfg_3_rd_A	404098015	3233	0	0
bank1_info0_page_cfg_4_rd_A	404098015	2726	0	0
bank1_info0_page_cfg_5_rd_A	404098015	3062	0	0
bank1_info0_page_cfg_6_rd_A	404098015	2661	0	0
bank1_info0_page_cfg_7_rd_A	404098015	2484	0	0
bank1_info0_page_cfg_8_rd_A	404098015	3040	0	0
bank1_info0_page_cfg_9_rd_A	404098015	2561	0	0
bank1_info0_regwen_0_rd_A	404098015	2245	0	0
bank1_info0_regwen_1_rd_A	404098015	2346	0	0
bank1_info0_regwen_2_rd_A	404098015	2337	0	0
bank1_info0_regwen_3_rd_A	404098015	1757	0	0
bank1_info0_regwen_4_rd_A	404098015	1865	0	0
bank1_info0_regwen_5_rd_A	404098015	2247	0	0
bank1_info0_regwen_6_rd_A	404098015	2324	0	0
bank1_info0_regwen_7_rd_A	404098015	2331	0	0
bank1_info0_regwen_8_rd_A	404098015	2327	0	0
bank1_info0_regwen_9_rd_A	404098015	1764	0	0
bank1_info1_page_cfg_rd_A	404098015	3044	0	0
bank1_info1_regwen_rd_A	404098015	1922	0	0
bank1_info2_page_cfg_0_rd_A	404098015	2482	0	0
bank1_info2_page_cfg_1_rd_A	404098015	2213	0	0
bank1_info2_regwen_0_rd_A	404098015	1672	0	0
bank1_info2_regwen_1_rd_A	404098015	1887	0	0
bank_cfg_regwen_rd_A	404098015	2199	0	0
default_region_rd_A	404098015	1966	0	0
exec_rd_A	404098015	1908	0	0
fifo_lvl_rd_A	404098015	2472	0	0
fifo_rst_rd_A	404098015	1841	0	0
hw_info_cfg_override_rd_A	404098015	2317	0	0
intr_enable_rd_A	404098015	2811	0	0
mp_region_0_rd_A	404098015	2530	0	0
mp_region_1_rd_A	404098015	1853	0	0
mp_region_2_rd_A	404098015	2055	0	0
mp_region_3_rd_A	404098015	1895	0	0
mp_region_4_rd_A	404098015	2518	0	0
mp_region_5_rd_A	404098015	2406	0	0
mp_region_6_rd_A	404098015	1935	0	0
mp_region_7_rd_A	404098015	2010	0	0
mp_region_cfg_0_rd_A	404098015	3189	0	0
mp_region_cfg_1_rd_A	404098015	3469	0	0
mp_region_cfg_2_rd_A	404098015	3111	0	0
mp_region_cfg_3_rd_A	404098015	2992	0	0
mp_region_cfg_4_rd_A	404098015	3170	0	0
mp_region_cfg_5_rd_A	404098015	3163	0	0
mp_region_cfg_6_rd_A	404098015	3045	0	0
mp_region_cfg_7_rd_A	404098015	2674	0	0
phy_alert_cfg_rd_A	404098015	1089	0	0
region_cfg_regwen_0_rd_A	404098015	2247	0	0
region_cfg_regwen_1_rd_A	404098015	1775	0	0
region_cfg_regwen_2_rd_A	404098015	2280	0	0
region_cfg_regwen_3_rd_A	404098015	1924	0	0
region_cfg_regwen_4_rd_A	404098015	1686	0	0
region_cfg_regwen_5_rd_A	404098015	1749	0	0
region_cfg_regwen_6_rd_A	404098015	2184	0	0
region_cfg_regwen_7_rd_A	404098015	2316	0	0
scratch_rd_A	404098015	2160	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2811	0	0
T79	33096	2	0	0
T117	32682	1	0	0
T240	5112	161	0	0
T241	5153	1	0	0
T242	4530	38	0	0
T253	8302	2	0	0
T254	5125	229	0	0
T255	2540	92	0	0
T256	3758	139	0	0
T259	16652	1	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2302	0	0
T241	5153	6	0	0
T264	17579	17	0	0
T270	6407	5	0	0
T285	8987	2	0	0
T320	272545	306	0	0
T321	5665	6	0	0
T322	7033	7	0	0
T323	9059	11	0	0
T324	86254	98	0	0
T325	4897	13	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3147	0	0
T241	5153	25	0	0
T264	17579	25	0	0
T270	6407	26	0	0
T285	8987	2	0	0
T320	272545	234	0	0
T321	5665	10	0	0
T322	7033	41	0	0
T323	9059	23	0	0
T324	86254	373	0	0
T326	3912	25	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3161	0	0
T241	5153	37	0	0
T264	17579	4	0	0
T270	6407	30	0	0
T285	8987	27	0	0
T320	272545	290	0	0
T321	5665	26	0	0
T322	7033	43	0	0
T323	9059	16	0	0
T324	86254	404	0	0
T327	6207	65	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2722	0	0
T241	5153	4	0	0
T264	17579	6	0	0
T270	6407	8	0	0
T285	8987	16	0	0
T320	272545	281	0	0
T321	5665	7	0	0
T322	7033	34	0	0
T323	9059	25	0	0
T324	86254	317	0	0
T326	3912	6	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2135	0	0
T241	5153	13	0	0
T264	17579	14	0	0
T270	6407	28	0	0
T285	8987	47	0	0
T320	272545	248	0	0
T321	5665	34	0	0
T322	7033	18	0	0
T323	9059	24	0	0
T324	86254	344	0	0
T326	3912	45	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2543	0	0
T241	5153	3	0	0
T270	6407	24	0	0
T285	8987	1	0	0
T320	272545	250	0	0
T321	5665	14	0	0
T322	7033	16	0	0
T323	9059	12	0	0
T324	86254	341	0	0
T326	3912	25	0	0
T327	6207	37	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2914	0	0
T241	5153	9	0	0
T264	17579	9	0	0
T270	6407	58	0	0
T285	8987	26	0	0
T320	272545	195	0	0
T321	5665	5	0	0
T322	7033	53	0	0
T323	9059	32	0	0
T324	86254	289	0	0
T326	3912	6	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3122	0	0
T241	5153	33	0	0
T264	17579	22	0	0
T270	6407	43	0	0
T285	8987	26	0	0
T320	272545	239	0	0
T321	5665	11	0	0
T322	7033	7	0	0
T323	9059	11	0	0
T324	86254	314	0	0
T326	3912	34	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2483	0	0
T241	5153	10	0	0
T264	17579	11	0	0
T270	6407	21	0	0
T285	8987	37	0	0
T320	272545	304	0	0
T321	5665	40	0	0
T322	7033	29	0	0
T323	9059	10	0	0
T324	86254	254	0	0
T326	3912	5	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2648	0	0
T241	5153	12	0	0
T264	17579	21	0	0
T270	6407	37	0	0
T285	8987	41	0	0
T320	272545	290	0	0
T321	5665	6	0	0
T322	7033	17	0	0
T323	9059	32	0	0
T324	86254	361	0	0
T326	3912	6	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2970	0	0
T241	5153	19	0	0
T264	17579	5	0	0
T270	6407	31	0	0
T285	8987	27	0	0
T320	272545	265	0	0
T321	5665	6	0	0
T322	7033	4	0	0
T323	9059	16	0	0
T324	86254	218	0	0
T326	3912	8	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1438	0	0
T241	5153	2	0	0
T264	17579	52	0	0
T270	6407	3	0	0
T285	8987	1	0	0
T320	272545	275	0	0
T321	5665	6	0	0
T322	7033	5	0	0
T323	9059	16	0	0
T324	86254	85	0	0
T326	3912	4	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1236	0	0
T241	5153	4	0	0
T264	17579	25	0	0
T270	6407	4	0	0
T285	8987	5	0	0
T320	272545	238	0	0
T321	5665	5	0	0
T322	7033	16	0	0
T323	9059	7	0	0
T324	86254	73	0	0
T326	3912	5	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2208	0	0
T241	5153	8	0	0
T264	17579	14	0	0
T270	6407	11	0	0
T285	8987	12	0	0
T320	272545	254	0	0
T321	5665	6	0	0
T322	7033	1	0	0
T323	9059	10	0	0
T324	86254	92	0	0
T326	3912	6	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1750	0	0
T241	5153	13	0	0
T264	17579	11	0	0
T270	6407	2	0	0
T285	8987	4	0	0
T320	272545	250	0	0
T321	5665	6	0	0
T322	7033	16	0	0
T323	9059	13	0	0
T324	86254	64	0	0
T326	3912	2	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1798	0	0
T241	5153	13	0	0
T264	17579	17	0	0
T270	6407	7	0	0
T285	8987	3	0	0
T320	272545	267	0	0
T321	5665	1	0	0
T322	7033	11	0	0
T323	9059	11	0	0
T324	86254	86	0	0
T328	3726	4	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1891	0	0
T241	5153	13	0	0
T264	17579	31	0	0
T270	6407	14	0	0
T285	8987	13	0	0
T320	272545	257	0	0
T321	5665	4	0	0
T322	7033	15	0	0
T323	9059	8	0	0
T324	86254	78	0	0
T326	3912	2	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1861	0	0
T241	5153	7	0	0
T264	17579	15	0	0
T270	6407	6	0	0
T285	8987	14	0	0
T320	272545	273	0	0
T321	5665	4	0	0
T322	7033	7	0	0
T323	9059	18	0	0
T324	86254	107	0	0
T326	3912	3	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2302	0	0
T241	5153	10	0	0
T264	17579	32	0	0
T270	6407	7	0	0
T285	8987	3	0	0
T320	272545	305	0	0
T321	5665	2	0	0
T322	7033	6	0	0
T323	9059	6	0	0
T324	86254	69	0	0
T326	3912	1	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2452	0	0
T241	5153	8	0	0
T264	17579	16	0	0
T270	6407	10	0	0
T285	8987	3	0	0
T320	272545	285	0	0
T321	5665	11	0	0
T322	7033	11	0	0
T323	9059	12	0	0
T324	86254	99	0	0
T326	3912	7	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1821	0	0
T241	5153	4	0	0
T264	17579	26	0	0
T270	6407	13	0	0
T320	272545	234	0	0
T321	5665	7	0	0
T322	7033	3	0	0
T323	9059	6	0	0
T324	86254	72	0	0
T326	3912	3	0	0
T327	6207	7	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3182	0	0
T241	5153	31	0	0
T264	17579	27	0	0
T270	6407	10	0	0
T285	8987	39	0	0
T320	272545	223	0	0
T321	5665	42	0	0
T322	7033	24	0	0
T323	9059	15	0	0
T324	86254	341	0	0
T326	3912	5	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2422	0	0
T241	5153	3	0	0
T264	17579	33	0	0
T270	6407	8	0	0
T285	8987	15	0	0
T320	272545	256	0	0
T321	5665	11	0	0
T322	7033	5	0	0
T323	9059	6	0	0
T324	86254	96	0	0
T326	3912	8	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3083	0	0
T241	5153	9	0	0
T264	17579	28	0	0
T270	6407	31	0	0
T285	8987	7	0	0
T320	272545	230	0	0
T321	5665	37	0	0
T322	7033	40	0	0
T323	9059	32	0	0
T324	86254	413	0	0
T326	3912	17	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3121	0	0
T264	17579	8	0	0
T270	6407	33	0	0
T285	8987	29	0	0
T320	272545	256	0	0
T321	5665	38	0	0
T322	7033	21	0	0
T323	9059	47	0	0
T324	86254	262	0	0
T326	3912	25	0	0
T328	3726	5	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2347	0	0
T241	5153	4	0	0
T264	17579	25	0	0
T270	6407	6	0	0
T285	8987	2	0	0
T320	272545	245	0	0
T321	5665	8	0	0
T322	7033	4	0	0
T324	86254	79	0	0
T326	3912	8	0	0
T328	3726	8	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2204	0	0
T241	5153	10	0	0
T264	17579	15	0	0
T270	6407	5	0	0
T285	8987	6	0	0
T320	272545	255	0	0
T321	5665	7	0	0
T322	7033	2	0	0
T323	9059	9	0	0
T324	86254	51	0	0
T326	3912	3	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2696	0	0
T241	5153	26	0	0
T264	17579	41	0	0
T270	6407	67	0	0
T285	8987	37	0	0
T320	272545	264	0	0
T321	5665	9	0	0
T322	7033	34	0	0
T323	9059	31	0	0
T324	86254	414	0	0
T326	3912	6	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2655	0	0
T241	5153	38	0	0
T264	17579	17	0	0
T270	6407	8	0	0
T285	8987	29	0	0
T320	272545	309	0	0
T321	5665	11	0	0
T322	7033	48	0	0
T323	9059	36	0	0
T324	86254	277	0	0
T326	3912	42	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3211	0	0
T241	5153	26	0	0
T264	17579	34	0	0
T270	6407	33	0	0
T285	8987	30	0	0
T320	272545	273	0	0
T321	5665	30	0	0
T322	7033	23	0	0
T323	9059	36	0	0
T324	86254	398	0	0
T326	3912	28	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3233	0	0
T241	5153	7	0	0
T264	17579	27	0	0
T270	6407	50	0	0
T285	8987	34	0	0
T320	272545	272	0	0
T321	5665	6	0	0
T322	7033	59	0	0
T323	9059	30	0	0
T324	86254	270	0	0
T326	3912	2	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2726	0	0
T241	5153	8	0	0
T264	17579	45	0	0
T270	6407	7	0	0
T285	8987	21	0	0
T320	272545	288	0	0
T321	5665	30	0	0
T322	7033	5	0	0
T323	9059	19	0	0
T324	86254	404	0	0
T326	3912	28	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3062	0	0
T241	5153	39	0	0
T264	17579	9	0	0
T270	6407	24	0	0
T285	8987	17	0	0
T320	272545	264	0	0
T321	5665	3	0	0
T322	7033	26	0	0
T323	9059	9	0	0
T324	86254	257	0	0
T326	3912	1	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2661	0	0
T241	5153	16	0	0
T264	17579	71	0	0
T270	6407	30	0	0
T285	8987	48	0	0
T320	272545	260	0	0
T321	5665	36	0	0
T322	7033	6	0	0
T323	9059	15	0	0
T324	86254	320	0	0
T326	3912	8	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2484	0	0
T241	5153	3	0	0
T264	17579	7	0	0
T270	6407	39	0	0
T285	8987	12	0	0
T320	272545	247	0	0
T321	5665	33	0	0
T322	7033	27	0	0
T323	9059	5	0	0
T324	86254	242	0	0
T326	3912	6	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3040	0	0
T241	5153	31	0	0
T264	17579	19	0	0
T270	6407	14	0	0
T285	8987	22	0	0
T320	272545	292	0	0
T321	5665	34	0	0
T322	7033	54	0	0
T323	9059	1	0	0
T324	86254	261	0	0
T326	3912	21	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2561	0	0
T241	5153	26	0	0
T264	17579	34	0	0
T270	6407	20	0	0
T285	8987	34	0	0
T320	272545	259	0	0
T321	5665	2	0	0
T322	7033	53	0	0
T323	9059	25	0	0
T324	86254	334	0	0
T326	3912	7	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2245	0	0
T241	5153	4	0	0
T264	17579	27	0	0
T270	6407	6	0	0
T285	8987	5	0	0
T320	272545	266	0	0
T321	5665	3	0	0
T322	7033	4	0	0
T323	9059	3	0	0
T324	86254	78	0	0
T326	3912	7	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2346	0	0
T241	5153	8	0	0
T264	17579	14	0	0
T270	6407	12	0	0
T285	8987	11	0	0
T320	272545	295	0	0
T321	5665	8	0	0
T322	7033	8	0	0
T323	9059	6	0	0
T324	86254	83	0	0
T326	3912	4	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2337	0	0
T241	5153	10	0	0
T264	17579	5	0	0
T270	6407	16	0	0
T285	8987	2	0	0
T320	272545	336	0	0
T321	5665	8	0	0
T322	7033	9	0	0
T323	9059	14	0	0
T324	86254	95	0	0
T327	6207	11	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1757	0	0
T241	5153	4	0	0
T264	17579	17	0	0
T270	6407	7	0	0
T285	8987	12	0	0
T320	272545	248	0	0
T321	5665	9	0	0
T322	7033	6	0	0
T323	9059	9	0	0
T324	86254	86	0	0
T326	3912	9	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1865	0	0
T241	5153	11	0	0
T264	17579	64	0	0
T270	6407	15	0	0
T285	8987	11	0	0
T320	272545	221	0	0
T321	5665	5	0	0
T322	7033	6	0	0
T323	9059	9	0	0
T324	86254	62	0	0
T326	3912	4	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2247	0	0
T241	5153	7	0	0
T264	17579	23	0	0
T270	6407	13	0	0
T320	272545	273	0	0
T321	5665	7	0	0
T322	7033	11	0	0
T323	9059	5	0	0
T324	86254	75	0	0
T326	3912	5	0	0
T327	6207	10	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2324	0	0
T241	5153	7	0	0
T264	17579	29	0	0
T270	6407	3	0	0
T320	272545	301	0	0
T321	5665	7	0	0
T322	7033	11	0	0
T323	9059	3	0	0
T324	86254	68	0	0
T326	3912	3	0	0
T328	3726	1	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2331	0	0
T241	5153	5	0	0
T264	17579	5	0	0
T270	6407	8	0	0
T285	8987	16	0	0
T320	272545	240	0	0
T321	5665	8	0	0
T322	7033	5	0	0
T323	9059	5	0	0
T324	86254	91	0	0
T326	3912	6	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2327	0	0
T241	5153	3	0	0
T264	17579	25	0	0
T270	6407	6	0	0
T285	8987	1	0	0
T320	272545	248	0	0
T321	5665	3	0	0
T322	7033	2	0	0
T323	9059	8	0	0
T324	86254	66	0	0
T326	3912	7	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1764	0	0
T241	5153	16	0	0
T264	17579	40	0	0
T270	6407	5	0	0
T285	8987	8	0	0
T320	272545	221	0	0
T321	5665	10	0	0
T322	7033	10	0	0
T324	86254	77	0	0
T326	3912	5	0	0
T328	3726	6	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3044	0	0
T241	5153	34	0	0
T264	17579	6	0	0
T270	6407	22	0	0
T285	8987	49	0	0
T320	272545	279	0	0
T321	5665	4	0	0
T322	7033	21	0	0
T323	9059	14	0	0
T324	86254	295	0	0
T326	3912	3	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1922	0	0
T241	5153	7	0	0
T264	17579	13	0	0
T270	6407	14	0	0
T285	8987	12	0	0
T320	272545	325	0	0
T321	5665	11	0	0
T322	7033	9	0	0
T323	9059	12	0	0
T324	86254	73	0	0
T326	3912	1	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2482	0	0
T241	5153	16	0	0
T264	17579	49	0	0
T270	6407	27	0	0
T285	8987	7	0	0
T320	272545	300	0	0
T321	5665	9	0	0
T322	7033	37	0	0
T323	9059	17	0	0
T324	86254	190	0	0
T326	3912	29	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2213	0	0
T241	5153	15	0	0
T264	17579	24	0	0
T270	6407	19	0	0
T285	8987	16	0	0
T320	272545	228	0	0
T321	5665	21	0	0
T322	7033	20	0	0
T323	9059	13	0	0
T324	86254	347	0	0
T326	3912	28	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1672	0	0
T241	5153	10	0	0
T264	17579	14	0	0
T270	6407	10	0	0
T285	8987	4	0	0
T320	272545	251	0	0
T321	5665	7	0	0
T322	7033	9	0	0
T323	9059	1	0	0
T324	86254	67	0	0
T327	6207	6	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1887	0	0
T241	5153	5	0	0
T264	17579	18	0	0
T270	6407	12	0	0
T285	8987	12	0	0
T320	272545	242	0	0
T321	5665	2	0	0
T322	7033	11	0	0
T323	9059	15	0	0
T324	86254	87	0	0
T326	3912	3	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2199	0	0
T264	17579	8	0	0
T270	6407	9	0	0
T285	8987	11	0	0
T320	272545	214	0	0
T321	5665	13	0	0
T322	7033	2	0	0
T323	9059	12	0	0
T324	86254	89	0	0
T326	3912	8	0	0
T328	3726	3	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1966	0	0
T241	5153	28	0	0
T264	17579	24	0	0
T270	6407	44	0	0
T285	8987	20	0	0
T320	272545	226	0	0
T321	5665	3	0	0
T322	7033	6	0	0
T323	9059	21	0	0
T324	86254	260	0	0
T326	3912	8	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1908	0	0
T241	5153	8	0	0
T264	17579	12	0	0
T270	6407	12	0	0
T285	8987	11	0	0
T320	272545	342	0	0
T321	5665	5	0	0
T322	7033	3	0	0
T323	9059	7	0	0
T324	86254	57	0	0
T326	3912	8	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2472	0	0
T241	5153	11	0	0
T264	17579	10	0	0
T270	6407	4	0	0
T285	8987	9	0	0
T320	272545	260	0	0
T321	5665	10	0	0
T322	7033	4	0	0
T323	9059	16	0	0
T324	86254	123	0	0
T326	3912	4	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1841	0	0
T241	5153	13	0	0
T264	17579	14	0	0
T270	6407	14	0	0
T285	8987	4	0	0
T320	272545	276	0	0
T321	5665	10	0	0
T322	7033	7	0	0
T324	86254	83	0	0
T326	3912	3	0	0
T328	3726	5	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2317	0	0
T241	5153	15	0	0
T264	17579	33	0	0
T270	6407	2	0	0
T285	8987	20	0	0
T320	272545	246	0	0
T321	5665	4	0	0
T322	7033	9	0	0
T323	9059	4	0	0
T324	86254	125	0	0
T326	3912	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2811	0	0
T241	5153	9	0	0
T264	17579	7	0	0
T270	6407	8	0	0
T285	8987	26	0	0
T320	272545	246	0	0
T321	5665	25	0	0
T322	7033	36	0	0
T323	9059	13	0	0
T324	86254	189	0	0
T326	3912	10	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2530	0	0
T241	5153	20	0	0
T270	6407	27	0	0
T285	8987	13	0	0
T320	272545	293	0	0
T321	5665	6	0	0
T322	7033	18	0	0
T323	9059	24	0	0
T324	86254	131	0	0
T326	3912	2	0	0
T328	3726	7	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1853	0	0
T241	5153	8	0	0
T264	17579	27	0	0
T270	6407	23	0	0
T320	272545	266	0	0
T321	5665	14	0	0
T322	7033	16	0	0
T323	9059	5	0	0
T324	86254	111	0	0
T327	6207	28	0	0
T328	3726	1	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2055	0	0
T241	5153	15	0	0
T264	17579	25	0	0
T270	6407	17	0	0
T320	272545	279	0	0
T321	5665	4	0	0
T322	7033	11	0	0
T323	9059	2	0	0
T324	86254	126	0	0
T326	3912	7	0	0
T328	3726	6	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1895	0	0
T241	5153	2	0	0
T264	17579	12	0	0
T270	6407	19	0	0
T285	8987	21	0	0
T320	272545	226	0	0
T321	5665	10	0	0
T322	7033	14	0	0
T324	86254	93	0	0
T326	3912	4	0	0
T328	3726	16	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2518	0	0
T241	5153	2	0	0
T264	17579	12	0	0
T270	6407	8	0	0
T285	8987	12	0	0
T320	272545	301	0	0
T321	5665	13	0	0
T322	7033	12	0	0
T323	9059	11	0	0
T324	86254	138	0	0
T326	3912	5	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2406	0	0
T241	5153	17	0	0
T264	17579	6	0	0
T270	6407	15	0	0
T285	8987	9	0	0
T320	272545	244	0	0
T321	5665	5	0	0
T322	7033	12	0	0
T323	9059	11	0	0
T324	86254	107	0	0
T326	3912	2	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1935	0	0
T241	5153	1	0	0
T264	17579	15	0	0
T270	6407	13	0	0
T285	8987	14	0	0
T320	272545	247	0	0
T321	5665	11	0	0
T322	7033	11	0	0
T323	9059	11	0	0
T324	86254	116	0	0
T326	3912	10	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2010	0	0
T241	5153	4	0	0
T264	17579	44	0	0
T270	6407	12	0	0
T285	8987	8	0	0
T320	272545	262	0	0
T321	5665	6	0	0
T322	7033	4	0	0
T323	9059	8	0	0
T324	86254	95	0	0
T328	3726	4	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3189	0	0
T241	5153	10	0	0
T264	17579	27	0	0
T270	6407	30	0	0
T285	8987	22	0	0
T320	272545	296	0	0
T321	5665	4	0	0
T322	7033	32	0	0
T323	9059	21	0	0
T324	86254	287	0	0
T326	3912	6	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3469	0	0
T241	5153	25	0	0
T264	17579	35	0	0
T270	6407	30	0	0
T285	8987	42	0	0
T320	272545	348	0	0
T321	5665	34	0	0
T322	7033	53	0	0
T323	9059	11	0	0
T324	86254	357	0	0
T326	3912	40	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3111	0	0
T241	5153	12	0	0
T264	17579	12	0	0
T270	6407	8	0	0
T285	8987	15	0	0
T320	272545	260	0	0
T321	5665	28	0	0
T322	7033	56	0	0
T323	9059	38	0	0
T324	86254	341	0	0
T326	3912	8	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2992	0	0
T241	5153	19	0	0
T270	6407	13	0	0
T285	8987	41	0	0
T320	272545	184	0	0
T321	5665	27	0	0
T322	7033	80	0	0
T323	9059	19	0	0
T324	86254	334	0	0
T326	3912	35	0	0
T328	3726	34	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3170	0	0
T241	5153	7	0	0
T264	17579	29	0	0
T270	6407	29	0	0
T285	8987	12	0	0
T320	272545	287	0	0
T321	5665	14	0	0
T322	7033	6	0	0
T323	9059	10	0	0
T324	86254	290	0	0
T326	3912	31	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3163	0	0
T241	5153	8	0	0
T264	17579	19	0	0
T270	6407	29	0	0
T285	8987	18	0	0
T320	272545	285	0	0
T321	5665	6	0	0
T322	7033	63	0	0
T323	9059	12	0	0
T324	86254	259	0	0
T326	3912	21	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	3045	0	0
T241	5153	4	0	0
T264	17579	35	0	0
T270	6407	62	0	0
T285	8987	12	0	0
T320	272545	312	0	0
T321	5665	32	0	0
T322	7033	20	0	0
T323	9059	4	0	0
T324	86254	249	0	0
T326	3912	1	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2674	0	0
T241	5153	31	0	0
T264	17579	7	0	0
T270	6407	37	0	0
T285	8987	8	0	0
T320	272545	291	0	0
T321	5665	9	0	0
T322	7033	4	0	0
T323	9059	26	0	0
T324	86254	375	0	0
T326	3912	22	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1089	0	0
T241	5153	7	0	0
T264	17579	5	0	0
T285	8987	2	0	0
T321	5665	7	0	0
T323	9059	2	0	0
T325	4897	7	0	0
T329	4718	8	0	0
T330	19316	53	0	0
T331	156781	986	0	0
T332	9758	12	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2247	0	0
T241	5153	6	0	0
T264	17579	49	0	0
T270	6407	6	0	0
T285	8987	12	0	0
T320	272545	285	0	0
T321	5665	4	0	0
T322	7033	14	0	0
T324	86254	58	0	0
T326	3912	1	0	0
T327	6207	6	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1775	0	0
T241	5153	5	0	0
T264	17579	35	0	0
T270	6407	3	0	0
T285	8987	2	0	0
T320	272545	194	0	0
T321	5665	11	0	0
T322	7033	7	0	0
T323	9059	14	0	0
T324	86254	81	0	0
T328	3726	1	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2280	0	0
T241	5153	14	0	0
T264	17579	48	0	0
T270	6407	6	0	0
T320	272545	246	0	0
T321	5665	7	0	0
T322	7033	8	0	0
T323	9059	4	0	0
T324	86254	91	0	0
T326	3912	7	0	0
T327	6207	3	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1924	0	0
T241	5153	10	0	0
T264	17579	23	0	0
T270	6407	9	0	0
T285	8987	7	0	0
T320	272545	316	0	0
T321	5665	7	0	0
T322	7033	4	0	0
T323	9059	15	0	0
T324	86254	76	0	0
T326	3912	7	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1686	0	0
T241	5153	13	0	0
T264	17579	18	0	0
T270	6407	12	0	0
T285	8987	6	0	0
T320	272545	235	0	0
T321	5665	8	0	0
T322	7033	8	0	0
T323	9059	12	0	0
T324	86254	72	0	0
T326	3912	4	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	1749	0	0
T241	5153	8	0	0
T264	17579	21	0	0
T270	6407	4	0	0
T285	8987	9	0	0
T320	272545	248	0	0
T321	5665	11	0	0
T322	7033	6	0	0
T323	9059	9	0	0
T324	86254	78	0	0
T326	3912	2	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2184	0	0
T241	5153	5	0	0
T264	17579	7	0	0
T270	6407	2	0	0
T285	8987	12	0	0
T320	272545	249	0	0
T321	5665	5	0	0
T322	7033	3	0	0
T323	9059	26	0	0
T324	86254	37	0	0
T326	3912	3	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2316	0	0
T241	5153	1	0	0
T264	17579	32	0	0
T270	6407	6	0	0
T285	8987	5	0	0
T320	272545	221	0	0
T321	5665	9	0	0
T322	7033	5	0	0
T323	9059	4	0	0
T324	86254	78	0	0
T326	3912	5	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404098015	2160	0	0
T241	5153	2	0	0
T264	17579	24	0	0
T270	6407	14	0	0
T285	8987	7	0	0
T320	272545	252	0	0
T321	5665	3	0	0
T322	7033	5	0	0
T323	9059	5	0	0
T324	86254	74	0	0
T326	3912	6	0	0