Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20297	1		T122	633		T123	644		T125	706
full_word	3750207	1		T4	16377		T6	16072		T7	9329

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3770256	1		T4	16377		T6	16072		T7	9329
auto[TlIntgErrCmd]	72	1		T124	5		T209	1		T210	6
auto[TlIntgErrData]	96	1		T124	4		T209	5		T210	8
auto[TlIntgErrBoth]	80	1		T209	3		T210	5		T277	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3744724	1		T4	16377		T6	16072		T7	9329
auto[1]	25780	1		T122	776		T123	897		T125	819

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1240	1		T122	36		T123	58		T125	22
auto[TlIntgErrNone]	partial	auto[1]	18830	1		T122	597		T123	586		T125	684
auto[TlIntgErrNone]	full_word	auto[0]	3743380	1		T4	16377		T6	16072		T7	9329
auto[TlIntgErrNone]	full_word	auto[1]	6806	1		T122	179		T123	311		T125	135
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T124	1		T209	1		T210	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1		T124	2		T210	5		T297	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T252	1		T345	2		T346	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T124	2		T339	1		T340	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T124	3		T209	3		T210	4
auto[TlIntgErrData]	partial	auto[1]	43	1		T209	2		T210	3		T297	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T210	1		T252	1		T254	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T124	1		T347	1		T341	1
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T210	2		T277	2		T252	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T209	2		T210	2		T277	3
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T209	1		T210	1		T342	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24438897	1		T1	290		T2	5197		T3	194
full_word	7904666	1		T1	131		T2	14698		T3	49

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32343293	1		T1	421		T2	19895		T3	243
auto[TlIntgErrCmd]	91	1		T124	7		T210	5		T297	5
auto[TlIntgErrData]	81	1		T124	1		T209	5		T210	4
auto[TlIntgErrBoth]	98	1		T124	2		T209	5		T210	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27869891	1		T1	296		T2	4573		T3	191
auto[1]	4473672	1		T1	125		T2	15322		T3	52

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23762605	1		T1	278		T2	2348		T3	189
auto[TlIntgErrNone]	partial	auto[1]	676042	1		T1	12		T2	2849		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	4107152	1		T1	18		T2	2225		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	3797494	1		T1	113		T2	12473		T3	47
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T124	5		T210	2		T297	2
auto[TlIntgErrCmd]	partial	auto[1]	41	1		T124	2		T210	3		T297	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T343	1		T348	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T297	1		T277	1		T349	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T124	1		T209	2		T210	1
auto[TlIntgErrData]	partial	auto[1]	32	1		T209	3		T210	2		T297	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T343	1		T347	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T210	1		T252	1		T254	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T124	2		T209	1		T210	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T209	4		T210	7		T297	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T210	1		T340	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T349	1		T342	1		T345	1