Line Coverage for Module :
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 68 | 63 | 92.65 |
CONT_ASSIGN | 107 | 0 | 0 | |
CONT_ASSIGN | 114 | 0 | 0 | |
ALWAYS | 129 | 3 | 3 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 6 | 75.00 |
ALWAYS | 299 | 6 | 5 | 83.33 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 0 | 0 | |
CONT_ASSIGN | 477 | 0 | 0 | |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 0 | 0 | |
ALWAYS | 492 | 4 | 2 | 50.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
107 |
|
unreachable |
114 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
|
unreachable |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
162 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
0 |
1 |
285 |
1 |
1 |
286 |
0 |
1 |
289 |
1 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
0 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
|
unreachable |
477 |
|
unreachable |
479 |
1 |
1 |
486 |
|
unreachable |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
0 |
1 |
504 |
|
unreachable |
510 |
0 |
1 |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
620 |
1 |
1 |
Line Coverage for Module :
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 72 | 69 | 95.83 |
CONT_ASSIGN | 107 | 0 | 0 | |
CONT_ASSIGN | 114 | 0 | 0 | |
ALWAYS | 129 | 4 | 4 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 6 | 75.00 |
ALWAYS | 299 | 6 | 5 | 83.33 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 492 | 4 | 4 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
107 |
|
unreachable |
114 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
0 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
0 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
305 |
0 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
477 |
1 |
1 |
479 |
1 |
1 |
486 |
1 |
1 |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
504 |
|
unreachable |
510 |
1 |
1 |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
620 |
1 |
1 |
Line Coverage for Module :
tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 71 | 69 | 97.18 |
CONT_ASSIGN | 107 | 0 | 0 | |
CONT_ASSIGN | 114 | 0 | 0 | |
ALWAYS | 129 | 4 | 4 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 7 | 87.50 |
ALWAYS | 299 | 6 | 5 | 83.33 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 492 | 4 | 4 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
107 |
|
unreachable |
114 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
0 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
305 |
0 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
477 |
1 |
1 |
479 |
1 |
1 |
486 |
1 |
1 |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
504 |
1 |
1 |
510 |
|
unreachable |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
Cond Coverage for Module :
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 116 | 75 | 64.66 |
Logical | 116 | 75 | 64.66 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 1 | 0 | Unreachable | |
0 | 1 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Unreachable | |
0 | 0 | 1 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T11,T18 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 162
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T5 |
0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T5,T18 |
1 | 1 | Covered | T1,T2,T5 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T41,T42 |
1 | 1 | Covered | T1,T2,T5 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Not Covered | |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Not Covered | |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Not Covered | |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T5 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T5 |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Not Covered | |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Cond Coverage for Module :
tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,SramBusBankAW=12,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 124 | 91 | 73.39 |
Logical | 124 | 91 | 73.39 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T13,T14,T15 |
1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Covered | T13,T14,T15 |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | Covered | T13,T14,T15 |
1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T11,T18 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (tl_i.a_opcode != Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T4,T6 |
0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T18,T23 |
1 | 1 | Covered | T1,T4,T6 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T4,T6 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T4,T6 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T4,T6 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T18,T43,T44 |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T43,T44 |
1 | 1 | Covered | T1,T4,T6 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T6 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T18,T43,T44 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T5,T45,T46 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Not Covered | |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T45,T46 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
Cond Coverage for Module :
tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,SramBusBankAW=17,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,EnableReadback=0,DataXorAddr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 128 | 101 | 78.91 |
Logical | 128 | 101 | 78.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T10,T21,T22 |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Covered | T10,T21,T22 |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Covered | T10,T21,T22 |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1- | Status | Tests |
0 | Covered | T4,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T7 |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T7 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T7,T20 |
0 | 1 | Covered | T4,T7,T20 |
1 | 0 | Covered | T4,T7,T47 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
-1- | Status | Tests |
0 | Covered | T4,T7,T20 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T7,T47 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (tl_i.a_opcode != Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T6,T7 |
0 | 0 | 0 | 0 | 0 | 1 | Covered | T10,T22 |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T4,T7,T47 |
0 | 0 | 0 | 1 | 0 | 0 | Covered | T45,T48,T49 |
0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T7,T20 |
1 | 1 | Covered | T4,T6,T7 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T50 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T6,T7 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T6,T7 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T7 |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T51,T52,T53 |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T45,T48,T49 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T6,T7 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T51,T52,T53 |
1 | 1 | Covered | T4,T6,T7 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T6,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T45,T48,T49 |
1 | 1 | 1 | Covered | T45,T48,T49 |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T51,T52,T53 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T45,T54,T55 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T6,T7 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T4,T6,T7 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T6,T7 |
1 | 1 | 0 | Covered | T45,T48,T49 |
1 | 1 | 1 | Covered | T4,T6,T7 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T6,T7 |
1 | Not Covered | |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T4,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T7 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T7 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T45,T48,T49 |
1 | 1 | Covered | T4,T6,T7 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
Branch Coverage for Module :
tlul_adapter_sram
| Line No. | Total | Covered | Percent |
Branches |
|
30 |
29 |
96.67 |
TERNARY |
144 |
2 |
2 |
100.00 |
TERNARY |
341 |
2 |
2 |
100.00 |
TERNARY |
347 |
3 |
2 |
66.67 |
TERNARY |
393 |
2 |
2 |
100.00 |
TERNARY |
531 |
2 |
2 |
100.00 |
IF |
129 |
3 |
3 |
100.00 |
IF |
281 |
4 |
4 |
100.00 |
IF |
301 |
3 |
3 |
100.00 |
IF |
362 |
2 |
2 |
100.00 |
IF |
426 |
2 |
2 |
100.00 |
IF |
438 |
2 |
2 |
100.00 |
IF |
496 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 341 ((vld_rd_rsp & (~d_error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ?
-2-: 347 (vld_rd_rsp) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T4,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 393 (tl_i_int.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 if ((!rst_ni))
-2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T13,T10,T21 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 281 if (reqfifo_rvalid)
-2-: 282 if (reqfifo_rdata.error)
-3-: 285 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T45,T48,T49 |
1 |
0 |
1 |
Covered |
T1,T4,T6 |
1 |
0 |
0 |
Covered |
T1,T2,T5 |
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if (reqfifo_rvalid)
-2-: 302 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T4,T6 |
1 |
0 |
Covered |
T1,T2,T5 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 362 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 426 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 438 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 496 if ((|sramreqfifo_rdata.mask))
-2-: 498 if (DataXorAddr)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T6,T7 |
1 |
0 |
Covered |
T1,T4,T6 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_sram
Assertion Details
AddrOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
DataIntgOptions_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3135 |
3135 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
3 |
3 |
0 |
0 |
T4 |
3 |
3 |
0 |
0 |
T5 |
3 |
3 |
0 |
0 |
T6 |
3 |
3 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T11 |
3 |
3 |
0 |
0 |
T16 |
3 |
3 |
0 |
0 |
T17 |
3 |
3 |
0 |
0 |
ReqOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
SramDwHasByteGranularity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3135 |
3135 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
3 |
3 |
0 |
0 |
T4 |
3 |
3 |
0 |
0 |
T5 |
3 |
3 |
0 |
0 |
T6 |
3 |
3 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T11 |
3 |
3 |
0 |
0 |
T16 |
3 |
3 |
0 |
0 |
T17 |
3 |
3 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3135 |
3135 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
3 |
3 |
0 |
0 |
T4 |
3 |
3 |
0 |
0 |
T5 |
3 |
3 |
0 |
0 |
T6 |
3 |
3 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T11 |
3 |
3 |
0 |
0 |
T16 |
3 |
3 |
0 |
0 |
T17 |
3 |
3 |
0 |
0 |
TlOutKnownIfFifoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
TlOutValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
WdataOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
WeOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
WmaskOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
1179232578 |
0 |
0 |
T1 |
6873 |
6645 |
0 |
0 |
T2 |
656130 |
655839 |
0 |
0 |
T3 |
3771 |
3564 |
0 |
0 |
T4 |
360732 |
360690 |
0 |
0 |
T5 |
10152 |
9870 |
0 |
0 |
T6 |
134328 |
134133 |
0 |
0 |
T7 |
515373 |
515214 |
0 |
0 |
T11 |
1156065 |
1156020 |
0 |
0 |
T16 |
9936 |
9729 |
0 |
0 |
T17 |
118449 |
118065 |
0 |
0 |
adapterNoReadOrWrite
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3135 |
3135 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
3 |
3 |
0 |
0 |
T4 |
3 |
3 |
0 |
0 |
T5 |
3 |
3 |
0 |
0 |
T6 |
3 |
3 |
0 |
0 |
T7 |
3 |
3 |
0 |
0 |
T11 |
3 |
3 |
0 |
0 |
T16 |
3 |
3 |
0 |
0 |
T17 |
3 |
3 |
0 |
0 |
rvalidHighReqFifoEmpty
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181939199 |
7394132 |
0 |
0 |
T1 |
2291 |
16 |
0 |
0 |
T2 |
218710 |
0 |
0 |
0 |
T3 |
1257 |
0 |
0 |
0 |
T4 |
240488 |
43049 |
0 |
0 |
T5 |
6768 |
24 |
0 |
0 |
T6 |
89552 |
21385 |
0 |
0 |
T7 |
343582 |
18848 |
0 |
0 |
T11 |
770710 |
0 |
0 |
0 |
T12 |
1017 |
0 |
0 |
0 |
T16 |
6624 |
0 |
0 |
0 |
T17 |
78966 |
20756 |
0 |
0 |
T18 |
101013 |
18825 |
0 |
0 |
T23 |
516939 |
1007 |
0 |
0 |
T24 |
0 |
10114 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T38 |
0 |
25506 |
0 |
0 |
T51 |
0 |
500 |
0 |
0 |
T52 |
0 |
16687 |
0 |
0 |
T56 |
0 |
41168 |
0 |
0 |
rvalidHighWhenRspFifoFull
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1181303225 |
7387930 |
0 |
0 |
T1 |
2291 |
16 |
0 |
0 |
T2 |
218710 |
0 |
0 |
0 |
T3 |
1257 |
0 |
0 |
0 |
T4 |
240488 |
43049 |
0 |
0 |
T5 |
6768 |
24 |
0 |
0 |
T6 |
89552 |
21385 |
0 |
0 |
T7 |
343582 |
18848 |
0 |
0 |
T11 |
770710 |
0 |
0 |
0 |
T12 |
1017 |
0 |
0 |
0 |
T16 |
6624 |
0 |
0 |
0 |
T17 |
78966 |
20756 |
0 |
0 |
T18 |
101013 |
18825 |
0 |
0 |
T23 |
516939 |
1007 |
0 |
0 |
T24 |
0 |
10114 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T38 |
0 |
25506 |
0 |
0 |
T51 |
0 |
500 |
0 |
0 |
T52 |
0 |
16687 |
0 |
0 |
T56 |
0 |
41168 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_to_prog_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 68 | 63 | 92.65 |
CONT_ASSIGN | 107 | 0 | 0 | |
CONT_ASSIGN | 114 | 0 | 0 | |
ALWAYS | 129 | 3 | 3 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 6 | 75.00 |
ALWAYS | 299 | 6 | 5 | 83.33 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 0 | 0 | |
CONT_ASSIGN | 477 | 0 | 0 | |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 0 | 0 | |
ALWAYS | 492 | 4 | 2 | 50.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
107 |
|
unreachable |
114 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
|
unreachable |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
162 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
0 |
1 |
285 |
1 |
1 |
286 |
0 |
1 |
289 |
1 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
0 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
|
unreachable |
477 |
|
unreachable |
479 |
1 |
1 |
486 |
|
unreachable |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
0 |
1 |
504 |
|
unreachable |
510 |
0 |
1 |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
620 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_prog_fifo
| Total | Covered | Percent |
Conditions | 116 | 75 | 64.66 |
Logical | 116 | 75 | 64.66 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 1 | 0 | Unreachable | |
0 | 1 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 1 | 0 | Unreachable | |
0 | 0 | 1 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T11,T18 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 162
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T5 |
0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T5,T18 |
1 | 1 | Covered | T1,T2,T5 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T41,T42 |
1 | 1 | Covered | T1,T2,T5 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Not Covered | |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Not Covered | |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Not Covered | |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T5 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T5 |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Not Covered | |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_to_prog_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
28 |
20 |
71.43 |
TERNARY |
144 |
2 |
2 |
100.00 |
TERNARY |
341 |
2 |
1 |
50.00 |
TERNARY |
347 |
3 |
1 |
33.33 |
TERNARY |
393 |
2 |
2 |
100.00 |
TERNARY |
531 |
2 |
1 |
50.00 |
IF |
129 |
2 |
2 |
100.00 |
IF |
281 |
4 |
2 |
50.00 |
IF |
301 |
3 |
2 |
66.67 |
IF |
362 |
2 |
2 |
100.00 |
IF |
426 |
2 |
2 |
100.00 |
IF |
438 |
2 |
2 |
100.00 |
IF |
496 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 341 ((vld_rd_rsp & (~d_error))) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ?
-2-: 347 (vld_rd_rsp) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 393 (tl_i_int.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 if ((!rst_ni))
-2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Unreachable |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 281 if (reqfifo_rvalid)
-2-: 282 if (reqfifo_rdata.error)
-3-: 285 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Not Covered |
|
1 |
0 |
1 |
Not Covered |
|
1 |
0 |
0 |
Covered |
T1,T2,T5 |
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if (reqfifo_rvalid)
-2-: 302 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Not Covered |
|
1 |
0 |
Covered |
T1,T2,T5 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 362 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 426 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 438 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 496 if ((|sramreqfifo_rdata.mask))
-2-: 498 if (DataXorAddr)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Unreachable |
|
1 |
0 |
Not Covered |
|
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_to_prog_fifo
Assertion Details
AddrOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
DataIntgOptions_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
SramDwHasByteGranularity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
TlOutValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WdataOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WeOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WmaskOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
adapterNoReadOrWrite
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
0 |
0 |
0 |
rvalidHighWhenRspFifoFull
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_to_rd_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 72 | 69 | 95.83 |
CONT_ASSIGN | 107 | 0 | 0 | |
CONT_ASSIGN | 114 | 0 | 0 | |
ALWAYS | 129 | 4 | 4 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 6 | 75.00 |
ALWAYS | 299 | 6 | 5 | 83.33 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 492 | 4 | 4 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
107 |
|
unreachable |
114 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
0 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
0 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
305 |
0 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
477 |
1 |
1 |
479 |
1 |
1 |
486 |
1 |
1 |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
504 |
|
unreachable |
510 |
1 |
1 |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
620 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_to_rd_fifo
| Total | Covered | Percent |
Conditions | 124 | 91 | 73.39 |
Logical | 124 | 91 | 73.39 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T13,T14,T15 |
1 | 0 | 0 | 0 | Unreachable | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Covered | T13,T14,T15 |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | Covered | T13,T14,T15 |
1 | 0 | 0 | 0 | 0 | Unreachable | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T11,T18 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (tl_i.a_opcode != Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T4,T6 |
0 | 0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T1,T4,T6 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T18,T23 |
1 | 1 | Covered | T1,T4,T6 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T6 |
1 | 0 | Covered | T1,T6,T7 |
1 | 1 | Covered | T1,T4,T6 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T4,T6 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T4,T6 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T6 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T18,T43,T44 |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T43,T44 |
1 | 1 | Covered | T1,T4,T6 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T4,T6 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Covered | T18,T43,T44 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T5,T45,T46 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T4,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T4,T6 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T4,T6 |
1 | Not Covered | |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T4,T6 |
1 | 1 | Not Covered | |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T45,T46 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T6 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T6 |
Branch Coverage for Instance : tb.dut.u_to_rd_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
29 |
25 |
86.21 |
TERNARY |
144 |
2 |
2 |
100.00 |
TERNARY |
341 |
2 |
2 |
100.00 |
TERNARY |
347 |
3 |
2 |
66.67 |
TERNARY |
393 |
2 |
2 |
100.00 |
TERNARY |
531 |
2 |
2 |
100.00 |
IF |
129 |
3 |
3 |
100.00 |
IF |
281 |
4 |
2 |
50.00 |
IF |
301 |
3 |
2 |
66.67 |
IF |
362 |
2 |
2 |
100.00 |
IF |
426 |
2 |
2 |
100.00 |
IF |
438 |
2 |
2 |
100.00 |
IF |
496 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 341 ((vld_rd_rsp & (~d_error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ?
-2-: 347 (vld_rd_rsp) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T4,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 393 (tl_i_int.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 if ((!rst_ni))
-2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T13,T14,T15 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 281 if (reqfifo_rvalid)
-2-: 282 if (reqfifo_rdata.error)
-3-: 285 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Not Covered |
|
1 |
0 |
1 |
Covered |
T1,T4,T6 |
1 |
0 |
0 |
Not Covered |
|
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if (reqfifo_rvalid)
-2-: 302 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T4,T6 |
1 |
0 |
Not Covered |
|
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 362 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 426 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 438 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 496 if ((|sramreqfifo_rdata.mask))
-2-: 498 if (DataXorAddr)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Unreachable |
|
1 |
0 |
Covered |
T1,T4,T6 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_to_rd_fifo
Assertion Details
AddrOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
DataIntgOptions_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
SramDwHasByteGranularity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
TlOutValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WdataOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WeOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WmaskOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
adapterNoReadOrWrite
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
3330095 |
0 |
0 |
T1 |
2291 |
16 |
0 |
0 |
T2 |
218710 |
0 |
0 |
0 |
T3 |
1257 |
0 |
0 |
0 |
T4 |
120244 |
26672 |
0 |
0 |
T5 |
3384 |
24 |
0 |
0 |
T6 |
44776 |
5313 |
0 |
0 |
T7 |
171791 |
1995 |
0 |
0 |
T11 |
385355 |
0 |
0 |
0 |
T16 |
3312 |
0 |
0 |
0 |
T17 |
39483 |
4064 |
0 |
0 |
T18 |
0 |
2257 |
0 |
0 |
T23 |
0 |
1007 |
0 |
0 |
T24 |
0 |
10114 |
0 |
0 |
T38 |
0 |
9152 |
0 |
0 |
rvalidHighWhenRspFifoFull
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393343759 |
3323893 |
0 |
0 |
T1 |
2291 |
16 |
0 |
0 |
T2 |
218710 |
0 |
0 |
0 |
T3 |
1257 |
0 |
0 |
0 |
T4 |
120244 |
26672 |
0 |
0 |
T5 |
3384 |
24 |
0 |
0 |
T6 |
44776 |
5313 |
0 |
0 |
T7 |
171791 |
1995 |
0 |
0 |
T11 |
385355 |
0 |
0 |
0 |
T16 |
3312 |
0 |
0 |
0 |
T17 |
39483 |
4064 |
0 |
0 |
T18 |
0 |
2257 |
0 |
0 |
T23 |
0 |
1007 |
0 |
0 |
T24 |
0 |
10114 |
0 |
0 |
T38 |
0 |
9152 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
| Line No. | Total | Covered | Percent |
TOTAL | | 71 | 69 | 97.18 |
CONT_ASSIGN | 107 | 0 | 0 | |
CONT_ASSIGN | 114 | 0 | 0 | |
ALWAYS | 129 | 4 | 4 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 7 | 87.50 |
ALWAYS | 299 | 6 | 5 | 83.33 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 492 | 4 | 4 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
107 |
|
unreachable |
114 |
|
unreachable |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
156 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
0 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
305 |
0 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
477 |
1 |
1 |
479 |
1 |
1 |
486 |
1 |
1 |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
504 |
1 |
1 |
510 |
|
unreachable |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
| Total | Covered | Percent |
Conditions | 128 | 101 | 78.91 |
Logical | 128 | 101 | 78.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T10,T21,T22 |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Covered | T10,T21,T22 |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Covered | T10,T21,T22 |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1- | Status | Tests |
0 | Covered | T4,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T7 |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T7 |
LINE 144
SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T7,T20 |
0 | 1 | Covered | T4,T7,T20 |
1 | 0 | Covered | T4,T7,T47 |
LINE 144
SUB-EXPRESSION (tl_i.a_mask != '1)
---------1---------
-1- | Status | Tests |
0 | Covered | T4,T7,T20 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_size != 2'h2)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T7,T47 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION (tl_i.a_opcode != Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T4,T6,T7 |
0 | 0 | 0 | 0 | 0 | 1 | Covered | T10,T22 |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T4,T7,T47 |
0 | 0 | 0 | 1 | 0 | 0 | Covered | T45,T48,T49 |
0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T7,T20 |
1 | 1 | Covered | T4,T6,T7 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T50 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T4,T6,T7 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T6,T7 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T6,T7 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T6,T7 |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T51,T52,T53 |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T45,T48,T49 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T6,T7 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T51,T52,T53 |
1 | 1 | Covered | T4,T6,T7 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T6,T7 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T45,T48,T49 |
1 | 1 | 1 | Covered | T45,T48,T49 |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Covered | T51,T52,T53 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T45,T54,T55 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T6,T7 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T45,T48,T49 |
1 | 0 | Covered | T4,T6,T7 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T6,T7 |
1 | 1 | 0 | Covered | T45,T48,T49 |
1 | 1 | 1 | Covered | T4,T6,T7 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T4,T6,T7 |
1 | Not Covered | |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T7 |
1 | 1 | Not Covered | |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T4,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T7 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T7 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T45,T48,T49 |
1 | 1 | Covered | T4,T6,T7 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T7 |
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
| Line No. | Total | Covered | Percent |
Branches |
|
29 |
26 |
89.66 |
TERNARY |
144 |
2 |
2 |
100.00 |
TERNARY |
341 |
2 |
2 |
100.00 |
TERNARY |
347 |
3 |
2 |
66.67 |
TERNARY |
393 |
2 |
2 |
100.00 |
TERNARY |
531 |
2 |
2 |
100.00 |
IF |
129 |
3 |
3 |
100.00 |
IF |
281 |
4 |
3 |
75.00 |
IF |
301 |
3 |
2 |
66.67 |
IF |
362 |
2 |
2 |
100.00 |
IF |
426 |
2 |
2 |
100.00 |
IF |
438 |
2 |
2 |
100.00 |
IF |
496 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T4,T6,T7 |
LineNo. Expression
-1-: 341 ((vld_rd_rsp & (~d_error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ?
-2-: 347 (vld_rd_rsp) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T4,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 393 (tl_i_int.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 if ((!rst_ni))
-2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T10,T21,T22 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 281 if (reqfifo_rvalid)
-2-: 282 if (reqfifo_rdata.error)
-3-: 285 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T45,T48,T49 |
1 |
0 |
1 |
Covered |
T4,T6,T7 |
1 |
0 |
0 |
Not Covered |
|
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if (reqfifo_rvalid)
-2-: 302 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T6,T7 |
1 |
0 |
Not Covered |
|
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 362 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 426 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 438 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 496 if ((|sramreqfifo_rdata.mask))
-2-: 498 if (DataXorAddr)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T6,T7 |
1 |
0 |
Unreachable |
|
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
Assertion Details
AddrOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
DataIntgOptions_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
SramDwHasByteGranularity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
TlOutValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WdataOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WeOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
WmaskOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
393077526 |
0 |
0 |
T1 |
2291 |
2215 |
0 |
0 |
T2 |
218710 |
218613 |
0 |
0 |
T3 |
1257 |
1188 |
0 |
0 |
T4 |
120244 |
120230 |
0 |
0 |
T5 |
3384 |
3290 |
0 |
0 |
T6 |
44776 |
44711 |
0 |
0 |
T7 |
171791 |
171738 |
0 |
0 |
T11 |
385355 |
385340 |
0 |
0 |
T16 |
3312 |
3243 |
0 |
0 |
T17 |
39483 |
39355 |
0 |
0 |
adapterNoReadOrWrite
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1045 |
1045 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
4064037 |
0 |
0 |
T4 |
120244 |
16377 |
0 |
0 |
T5 |
3384 |
0 |
0 |
0 |
T6 |
44776 |
16072 |
0 |
0 |
T7 |
171791 |
16853 |
0 |
0 |
T11 |
385355 |
0 |
0 |
0 |
T12 |
1017 |
0 |
0 |
0 |
T16 |
3312 |
0 |
0 |
0 |
T17 |
39483 |
16692 |
0 |
0 |
T18 |
101013 |
16568 |
0 |
0 |
T23 |
516939 |
0 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T38 |
0 |
16354 |
0 |
0 |
T51 |
0 |
500 |
0 |
0 |
T52 |
0 |
16687 |
0 |
0 |
T56 |
0 |
41168 |
0 |
0 |
rvalidHighWhenRspFifoFull
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393979733 |
4064037 |
0 |
0 |
T4 |
120244 |
16377 |
0 |
0 |
T5 |
3384 |
0 |
0 |
0 |
T6 |
44776 |
16072 |
0 |
0 |
T7 |
171791 |
16853 |
0 |
0 |
T11 |
385355 |
0 |
0 |
0 |
T12 |
1017 |
0 |
0 |
0 |
T16 |
3312 |
0 |
0 |
0 |
T17 |
39483 |
16692 |
0 |
0 |
T18 |
101013 |
16568 |
0 |
0 |
T23 |
516939 |
0 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T38 |
0 |
16354 |
0 |
0 |
T51 |
0 |
500 |
0 |
0 |
T52 |
0 |
16687 |
0 |
0 |
T56 |
0 |
41168 |
0 |
0 |