Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1575918932	1572310104	0	0
CheckNGreaterZero_A	4180	4180	0	0
GntImpliesReady_A	1575918932	403090964	0	0
GntImpliesValid_A	1575918932	403090964	0	0
GrantKnown_A	1575918932	1572310104	0	0
IdxKnown_A	1575918932	1572310104	0	0
IndexIsCorrect_A	1575918932	403090964	0	0
NoReadyValidNoGrant_A	1575918932	179439643	0	0
Priority_A	1575918932	427489867	0	0
ReadyAndValidImplyGrant_A	1575918932	403090964	0	0
ReqAndReadyImplyGrant_A	1575918932	403090964	0	0
ReqImpliesValid_A	1575918932	427489867	0	0
ValidKnown_A	1575918932	1572310104	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	1572310104	0	0
T1	9164	8860	0	0
T2	874840	874452	0	0
T3	5028	4752	0	0
T4	480976	480920	0	0
T5	13536	13160	0	0
T6	179104	178844	0	0
T7	687164	686952	0	0
T11	1541420	1541360	0	0
T16	13248	12972	0	0
T17	157932	157420	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4180	4180	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	403090964	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	86156	0	0
T5	13536	998	0	0
T6	179104	39500	0	0
T7	687164	254024	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	41580	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	403090964	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	86156	0	0
T5	13536	998	0	0
T6	179104	39500	0	0
T7	687164	254024	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	41580	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	1572310104	0	0
T1	9164	8860	0	0
T2	874840	874452	0	0
T3	5028	4752	0	0
T4	480976	480920	0	0
T5	13536	13160	0	0
T6	179104	178844	0	0
T7	687164	686952	0	0
T11	1541420	1541360	0	0
T16	13248	12972	0	0
T17	157932	157420	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	1572310104	0	0
T1	9164	8860	0	0
T2	874840	874452	0	0
T3	5028	4752	0	0
T4	480976	480920	0	0
T5	13536	13160	0	0
T6	179104	178844	0	0
T7	687164	686952	0	0
T11	1541420	1541360	0	0
T16	13248	12972	0	0
T17	157932	157420	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	403090964	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	86156	0	0
T5	13536	998	0	0
T6	179104	39500	0	0
T7	687164	254024	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	41580	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	179439643	0	0
T1	9164	306	0	0
T2	874840	256	0	0
T3	5028	256	0	0
T4	480976	2538668	0	0
T5	13536	332	0	0
T6	179104	52312	0	0
T7	687164	68882	0	0
T11	1541420	2109952	0	0
T16	13248	256	0	0
T17	157932	65392	0	0
T18	0	62110	0	0
T23	0	850	0	0
T24	0	4786	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	427489867	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	663662	0	0
T5	13536	998	0	0
T6	179104	49914	0	0
T7	687164	279450	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	52808	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	403090964	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	86156	0	0
T5	13536	998	0	0
T6	179104	39500	0	0
T7	687164	254024	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	41580	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	403090964	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	86156	0	0
T5	13536	998	0	0
T6	179104	39500	0	0
T7	687164	254024	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	41580	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	427489867	0	0
T1	9164	1310	0	0
T2	874840	380222	0	0
T3	5028	584	0	0
T4	480976	663662	0	0
T5	13536	998	0	0
T6	179104	49914	0	0
T7	687164	279450	0	0
T11	1541420	514654	0	0
T12	0	442	0	0
T16	13248	64	0	0
T17	157932	52808	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575918932	1572310104	0	0
T1	9164	8860	0	0
T2	874840	874452	0	0
T3	5028	4752	0	0
T4	480976	480920	0	0
T5	13536	13160	0	0
T6	179104	178844	0	0
T7	687164	686952	0	0
T11	1541420	1541360	0	0
T16	13248	12972	0	0
T17	157932	157420	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393979733	393077526	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	393979733	109634054	0	0
GntImpliesValid_A	393979733	109634054	0	0
GrantKnown_A	393979733	393077526	0	0
IdxKnown_A	393979733	393077526	0	0
IndexIsCorrect_A	393979733	109634054	0	0
NoReadyValidNoGrant_A	393979733	46796049	0	0
Priority_A	393979733	115978619	0	0
ReadyAndValidImplyGrant_A	393979733	109634054	0	0
ReqAndReadyImplyGrant_A	393979733	109634054	0	0
ReqImpliesValid_A	393979733	115978619	0	0
ValidKnown_A	393979733	393077526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634054	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634054	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634054	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	46796049	0	0
T1	2291	133	0	0
T2	218710	128	0	0
T3	1257	128	0	0
T4	120244	659047	0	0
T5	3384	128	0	0
T6	44776	13489	0	0
T7	171791	17619	0	0
T11	385355	530688	0	0
T16	3312	128	0	0
T17	39483	21875	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	115978619	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	172815	0	0
T5	3384	230	0	0
T6	44776	13506	0	0
T7	171791	63103	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	15631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634054	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634054	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	115978619	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	172815	0	0
T5	3384	230	0	0
T6	44776	13506	0	0
T7	171791	63103	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	15631	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393979733	393077526	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	393979733	109634042	0	0
GntImpliesValid_A	393979733	109634042	0	0
GrantKnown_A	393979733	393077526	0	0
IdxKnown_A	393979733	393077526	0	0
IndexIsCorrect_A	393979733	109634042	0	0
NoReadyValidNoGrant_A	393979733	46796034	0	0
Priority_A	393979733	115978622	0	0
ReadyAndValidImplyGrant_A	393979733	109634042	0	0
ReqAndReadyImplyGrant_A	393979733	109634042	0	0
ReqImpliesValid_A	393979733	115978622	0	0
ValidKnown_A	393979733	393077526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634042	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634042	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634042	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	46796034	0	0
T1	2291	133	0	0
T2	218710	128	0	0
T3	1257	128	0	0
T4	120244	659047	0	0
T5	3384	128	0	0
T6	44776	13489	0	0
T7	171791	17619	0	0
T11	385355	530688	0	0
T16	3312	128	0	0
T17	39483	21875	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	115978622	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	172815	0	0
T5	3384	230	0	0
T6	44776	13506	0	0
T7	171791	63103	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	15631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634042	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	109634042	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	22644	0	0
T5	3384	230	0	0
T6	44776	10459	0	0
T7	171791	55821	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	12328	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	115978622	0	0
T1	2291	312	0	0
T2	218710	109218	0	0
T3	1257	32	0	0
T4	120244	172815	0	0
T5	3384	230	0	0
T6	44776	13506	0	0
T7	171791	63103	0	0
T11	385355	129430	0	0
T16	3312	32	0	0
T17	39483	15631	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393979733	393077526	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	393979733	91911407	0	0
GntImpliesValid_A	393979733	91911407	0	0
GrantKnown_A	393979733	393077526	0	0
IdxKnown_A	393979733	393077526	0	0
IndexIsCorrect_A	393979733	91911407	0	0
NoReadyValidNoGrant_A	393979733	42923783	0	0
Priority_A	393979733	97766283	0	0
ReadyAndValidImplyGrant_A	393979733	91911407	0	0
ReqAndReadyImplyGrant_A	393979733	91911407	0	0
ReqImpliesValid_A	393979733	97766283	0	0
ValidKnown_A	393979733	393077526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911407	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911407	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911407	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	42923783	0	0
T1	2291	20	0	0
T2	218710	0	0	0
T3	1257	0	0	0
T4	120244	610287	0	0
T5	3384	38	0	0
T6	44776	12667	0	0
T7	171791	16822	0	0
T11	385355	524288	0	0
T16	3312	0	0	0
T17	39483	10821	0	0
T18	0	31055	0	0
T23	0	425	0	0
T24	0	2393	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	97766283	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	159016	0	0
T5	3384	269	0	0
T6	44776	11451	0	0
T7	171791	76622	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	10773	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911407	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911407	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	97766283	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	159016	0	0
T5	3384	269	0	0
T6	44776	11451	0	0
T7	171791	76622	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	10773	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393979733	393077526	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	393979733	91911461	0	0
GntImpliesValid_A	393979733	91911461	0	0
GrantKnown_A	393979733	393077526	0	0
IdxKnown_A	393979733	393077526	0	0
IndexIsCorrect_A	393979733	91911461	0	0
NoReadyValidNoGrant_A	393979733	42923777	0	0
Priority_A	393979733	97766343	0	0
ReadyAndValidImplyGrant_A	393979733	91911461	0	0
ReqAndReadyImplyGrant_A	393979733	91911461	0	0
ReqImpliesValid_A	393979733	97766343	0	0
ValidKnown_A	393979733	393077526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911461	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911461	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911461	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	42923777	0	0
T1	2291	20	0	0
T2	218710	0	0	0
T3	1257	0	0	0
T4	120244	610287	0	0
T5	3384	38	0	0
T6	44776	12667	0	0
T7	171791	16822	0	0
T11	385355	524288	0	0
T16	3312	0	0	0
T17	39483	10821	0	0
T18	0	31055	0	0
T23	0	425	0	0
T24	0	2393	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	97766343	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	159016	0	0
T5	3384	269	0	0
T6	44776	11451	0	0
T7	171791	76622	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	10773	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911461	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	91911461	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	20434	0	0
T5	3384	269	0	0
T6	44776	9291	0	0
T7	171791	71191	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	8462	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	97766343	0	0
T1	2291	343	0	0
T2	218710	80893	0	0
T3	1257	260	0	0
T4	120244	159016	0	0
T5	3384	269	0	0
T6	44776	11451	0	0
T7	171791	76622	0	0
T11	385355	127897	0	0
T12	0	221	0	0
T16	3312	0	0	0
T17	39483	10773	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393979733	393077526	0	0
T1	2291	2215	0	0
T2	218710	218613	0	0
T3	1257	1188	0	0
T4	120244	120230	0	0
T5	3384	3290	0	0
T6	44776	44711	0	0
T7	171791	171738	0	0
T11	385355	385340	0	0
T16	3312	3243	0	0
T17	39483	39355	0	0