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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 95.24 93.81 98.31 92.52 97.16 96.99 98.18


Total test records in report: 1260
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T1076 /workspace/coverage/default/42.flash_ctrl_disable.1069250915 Aug 10 07:41:57 PM PDT 24 Aug 10 07:42:19 PM PDT 24 16635300 ps
T1077 /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1744448616 Aug 10 07:37:44 PM PDT 24 Aug 10 07:38:15 PM PDT 24 44570000 ps
T1078 /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3230100415 Aug 10 07:41:27 PM PDT 24 Aug 10 07:46:26 PM PDT 24 23748503400 ps
T1079 /workspace/coverage/default/19.flash_ctrl_ro.795805496 Aug 10 07:39:34 PM PDT 24 Aug 10 07:41:40 PM PDT 24 1419990200 ps
T1080 /workspace/coverage/default/5.flash_ctrl_intr_rd.2054441128 Aug 10 07:35:35 PM PDT 24 Aug 10 07:38:02 PM PDT 24 13778582300 ps
T1081 /workspace/coverage/default/1.flash_ctrl_intr_wr.4056714428 Aug 10 07:34:10 PM PDT 24 Aug 10 07:35:15 PM PDT 24 2156757000 ps
T1082 /workspace/coverage/default/19.flash_ctrl_otp_reset.1687786674 Aug 10 07:39:33 PM PDT 24 Aug 10 07:41:47 PM PDT 24 623288000 ps
T1083 /workspace/coverage/default/30.flash_ctrl_connect.1791801970 Aug 10 07:41:00 PM PDT 24 Aug 10 07:41:16 PM PDT 24 15460400 ps
T1084 /workspace/coverage/default/22.flash_ctrl_prog_reset.2411598121 Aug 10 07:40:01 PM PDT 24 Aug 10 07:40:15 PM PDT 24 20822100 ps
T1085 /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.1693918493 Aug 10 07:39:34 PM PDT 24 Aug 10 07:53:55 PM PDT 24 140173604300 ps
T1086 /workspace/coverage/default/22.flash_ctrl_smoke.2148090014 Aug 10 07:39:57 PM PDT 24 Aug 10 07:42:25 PM PDT 24 122662900 ps
T1087 /workspace/coverage/default/13.flash_ctrl_prog_reset.1570613623 Aug 10 07:38:13 PM PDT 24 Aug 10 07:38:27 PM PDT 24 34646300 ps
T1088 /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1683645959 Aug 10 07:33:50 PM PDT 24 Aug 10 07:35:34 PM PDT 24 12045012900 ps
T1089 /workspace/coverage/default/12.flash_ctrl_intr_rd.235177003 Aug 10 07:37:53 PM PDT 24 Aug 10 07:41:24 PM PDT 24 9491299100 ps
T1090 /workspace/coverage/default/3.flash_ctrl_oversize_error.2429586913 Aug 10 07:34:43 PM PDT 24 Aug 10 07:37:34 PM PDT 24 4124827400 ps
T1091 /workspace/coverage/default/46.flash_ctrl_alert_test.3489902279 Aug 10 07:42:16 PM PDT 24 Aug 10 07:42:29 PM PDT 24 34191400 ps
T1092 /workspace/coverage/default/12.flash_ctrl_sec_info_access.265720500 Aug 10 07:37:58 PM PDT 24 Aug 10 07:39:09 PM PDT 24 803631200 ps
T1093 /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1235353805 Aug 10 07:38:14 PM PDT 24 Aug 10 07:39:07 PM PDT 24 10034496100 ps
T1094 /workspace/coverage/default/1.flash_ctrl_alert_test.847572631 Aug 10 07:34:16 PM PDT 24 Aug 10 07:34:30 PM PDT 24 83017400 ps
T1095 /workspace/coverage/default/6.flash_ctrl_rw_serr.1022251170 Aug 10 07:35:58 PM PDT 24 Aug 10 07:39:27 PM PDT 24 1489832500 ps
T1096 /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.752204985 Aug 10 07:36:28 PM PDT 24 Aug 10 07:37:48 PM PDT 24 10019609000 ps
T1097 /workspace/coverage/default/9.flash_ctrl_rw.2524165359 Aug 10 07:37:03 PM PDT 24 Aug 10 07:45:52 PM PDT 24 7040526100 ps
T1098 /workspace/coverage/default/43.flash_ctrl_sec_info_access.1584534572 Aug 10 07:42:04 PM PDT 24 Aug 10 07:43:07 PM PDT 24 614695800 ps
T1099 /workspace/coverage/default/15.flash_ctrl_re_evict.1364828192 Aug 10 07:38:40 PM PDT 24 Aug 10 07:39:16 PM PDT 24 197236200 ps
T1100 /workspace/coverage/default/48.flash_ctrl_otp_reset.1478755575 Aug 10 07:42:20 PM PDT 24 Aug 10 07:44:30 PM PDT 24 227670500 ps
T1101 /workspace/coverage/default/34.flash_ctrl_rw_evict.2942696821 Aug 10 07:41:16 PM PDT 24 Aug 10 07:41:48 PM PDT 24 31852700 ps
T1102 /workspace/coverage/default/25.flash_ctrl_otp_reset.2264303372 Aug 10 07:40:19 PM PDT 24 Aug 10 07:42:32 PM PDT 24 42858400 ps
T1103 /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3288432004 Aug 10 07:39:29 PM PDT 24 Aug 10 07:39:43 PM PDT 24 36660600 ps
T1104 /workspace/coverage/default/12.flash_ctrl_otp_reset.1548367277 Aug 10 07:37:53 PM PDT 24 Aug 10 07:40:05 PM PDT 24 37705000 ps
T1105 /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.192820224 Aug 10 07:37:03 PM PDT 24 Aug 10 07:39:34 PM PDT 24 5974068100 ps
T1106 /workspace/coverage/default/16.flash_ctrl_phy_arb.1220949134 Aug 10 07:38:48 PM PDT 24 Aug 10 07:46:07 PM PDT 24 90559800 ps
T1107 /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.4006524293 Aug 10 07:34:06 PM PDT 24 Aug 10 07:36:27 PM PDT 24 15997963400 ps
T1108 /workspace/coverage/default/1.flash_ctrl_smoke.3081089505 Aug 10 07:34:01 PM PDT 24 Aug 10 07:35:17 PM PDT 24 36353400 ps
T356 /workspace/coverage/default/20.flash_ctrl_disable.2330507389 Aug 10 07:39:47 PM PDT 24 Aug 10 07:40:09 PM PDT 24 11372000 ps
T1109 /workspace/coverage/default/9.flash_ctrl_ro_derr.1331663781 Aug 10 07:37:03 PM PDT 24 Aug 10 07:39:38 PM PDT 24 9471155400 ps
T1110 /workspace/coverage/default/13.flash_ctrl_connect.1871331046 Aug 10 07:38:13 PM PDT 24 Aug 10 07:38:27 PM PDT 24 41707600 ps
T1111 /workspace/coverage/default/5.flash_ctrl_invalid_op.2970735499 Aug 10 07:35:29 PM PDT 24 Aug 10 07:36:52 PM PDT 24 16176012600 ps
T1112 /workspace/coverage/default/13.flash_ctrl_otp_reset.4253340721 Aug 10 07:38:05 PM PDT 24 Aug 10 07:39:57 PM PDT 24 41198800 ps
T1113 /workspace/coverage/default/0.flash_ctrl_integrity.1792337540 Aug 10 07:33:50 PM PDT 24 Aug 10 07:43:27 PM PDT 24 30163803100 ps
T93 /workspace/coverage/default/27.flash_ctrl_prog_reset.2349425709 Aug 10 07:40:31 PM PDT 24 Aug 10 07:40:45 PM PDT 24 33764200 ps
T50 /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.152565359 Aug 10 07:34:12 PM PDT 24 Aug 10 07:34:35 PM PDT 24 706014300 ps
T1114 /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.841396444 Aug 10 07:42:20 PM PDT 24 Aug 10 07:44:57 PM PDT 24 22860329000 ps
T322 /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2134827371 Aug 10 07:40:59 PM PDT 24 Aug 10 07:41:31 PM PDT 24 83466200 ps
T1115 /workspace/coverage/default/31.flash_ctrl_smoke.612903400 Aug 10 07:41:01 PM PDT 24 Aug 10 07:43:05 PM PDT 24 43062400 ps
T1116 /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3327459926 Aug 10 07:38:40 PM PDT 24 Aug 10 07:41:02 PM PDT 24 5664431700 ps
T70 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1618560006 Aug 10 07:28:12 PM PDT 24 Aug 10 07:28:43 PM PDT 24 423254200 ps
T244 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2225492562 Aug 10 07:28:45 PM PDT 24 Aug 10 07:28:58 PM PDT 24 14745600 ps
T245 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1226152321 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 92517400 ps
T122 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1598911301 Aug 10 07:28:51 PM PDT 24 Aug 10 07:29:07 PM PDT 24 123035100 ps
T123 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3020177755 Aug 10 07:28:23 PM PDT 24 Aug 10 07:28:40 PM PDT 24 40793900 ps
T125 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2566372677 Aug 10 07:29:02 PM PDT 24 Aug 10 07:29:18 PM PDT 24 127215700 ps
T71 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1227402917 Aug 10 07:28:37 PM PDT 24 Aug 10 07:28:52 PM PDT 24 225873800 ps
T72 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1983756949 Aug 10 07:28:28 PM PDT 24 Aug 10 07:28:48 PM PDT 24 143394900 ps
T246 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2257029834 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 15297300 ps
T124 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1804525006 Aug 10 07:28:50 PM PDT 24 Aug 10 07:35:21 PM PDT 24 196033400 ps
T1117 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.41845581 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:17 PM PDT 24 92540500 ps
T209 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2509775154 Aug 10 07:28:39 PM PDT 24 Aug 10 07:35:10 PM PDT 24 1302593400 ps
T1118 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1534815832 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:45 PM PDT 24 40589400 ps
T1119 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1546676457 Aug 10 07:28:32 PM PDT 24 Aug 10 07:28:48 PM PDT 24 13326300 ps
T1120 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2931931658 Aug 10 07:28:49 PM PDT 24 Aug 10 07:29:05 PM PDT 24 13950700 ps
T231 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.500178528 Aug 10 07:28:13 PM PDT 24 Aug 10 07:28:33 PM PDT 24 230703900 ps
T221 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2096801270 Aug 10 07:28:10 PM PDT 24 Aug 10 07:28:30 PM PDT 24 743614900 ps
T298 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2513693359 Aug 10 07:29:09 PM PDT 24 Aug 10 07:29:22 PM PDT 24 15817700 ps
T232 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1719750867 Aug 10 07:28:36 PM PDT 24 Aug 10 07:28:54 PM PDT 24 348534800 ps
T227 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1964522703 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:31 PM PDT 24 56141000 ps
T1121 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4162936564 Aug 10 07:28:43 PM PDT 24 Aug 10 07:28:57 PM PDT 24 33729000 ps
T233 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1341619583 Aug 10 07:28:15 PM PDT 24 Aug 10 07:28:33 PM PDT 24 179832800 ps
T1122 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3916735147 Aug 10 07:28:49 PM PDT 24 Aug 10 07:29:02 PM PDT 24 11556700 ps
T211 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.363419966 Aug 10 07:28:45 PM PDT 24 Aug 10 07:29:05 PM PDT 24 99608700 ps
T300 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3433050752 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:21 PM PDT 24 16633500 ps
T1123 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3587070527 Aug 10 07:28:26 PM PDT 24 Aug 10 07:28:42 PM PDT 24 38137500 ps
T234 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1678555722 Aug 10 07:28:43 PM PDT 24 Aug 10 07:28:59 PM PDT 24 34630400 ps
T1124 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3268676775 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:29 PM PDT 24 15571900 ps
T299 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1263953787 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:21 PM PDT 24 17914100 ps
T235 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1088518696 Aug 10 07:28:38 PM PDT 24 Aug 10 07:28:55 PM PDT 24 73702700 ps
T301 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3223278677 Aug 10 07:28:09 PM PDT 24 Aug 10 07:28:22 PM PDT 24 44171700 ps
T210 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1589101098 Aug 10 07:28:39 PM PDT 24 Aug 10 07:41:20 PM PDT 24 907259400 ps
T1125 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.551779640 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:45 PM PDT 24 15232500 ps
T236 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.219395875 Aug 10 07:29:04 PM PDT 24 Aug 10 07:29:22 PM PDT 24 99058500 ps
T222 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.462614875 Aug 10 07:28:36 PM PDT 24 Aug 10 07:28:55 PM PDT 24 99089700 ps
T1126 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3392985209 Aug 10 07:28:54 PM PDT 24 Aug 10 07:29:10 PM PDT 24 23333400 ps
T393 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2736692587 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:47 PM PDT 24 37801200 ps
T1127 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1853916845 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 29188400 ps
T302 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3553240673 Aug 10 07:29:11 PM PDT 24 Aug 10 07:29:25 PM PDT 24 44495000 ps
T223 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.390537960 Aug 10 07:28:45 PM PDT 24 Aug 10 07:29:06 PM PDT 24 339222400 ps
T224 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2912091526 Aug 10 07:28:12 PM PDT 24 Aug 10 07:28:32 PM PDT 24 306483000 ps
T303 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1578906647 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:21 PM PDT 24 17180200 ps
T237 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2057902359 Aug 10 07:28:24 PM PDT 24 Aug 10 07:28:42 PM PDT 24 69639200 ps
T238 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.478324716 Aug 10 07:28:32 PM PDT 24 Aug 10 07:28:50 PM PDT 24 333886900 ps
T1128 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1066393105 Aug 10 07:28:15 PM PDT 24 Aug 10 07:28:53 PM PDT 24 644134400 ps
T1129 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2350983549 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:44 PM PDT 24 37061600 ps
T1130 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1889063422 Aug 10 07:29:07 PM PDT 24 Aug 10 07:29:20 PM PDT 24 25843600 ps
T297 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1393227679 Aug 10 07:28:17 PM PDT 24 Aug 10 07:36:01 PM PDT 24 917225500 ps
T239 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2055887582 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:46 PM PDT 24 36947300 ps
T1131 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.90122602 Aug 10 07:28:43 PM PDT 24 Aug 10 07:28:59 PM PDT 24 17299600 ps
T276 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.666782278 Aug 10 07:28:44 PM PDT 24 Aug 10 07:29:03 PM PDT 24 865951900 ps
T251 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.32906906 Aug 10 07:28:19 PM PDT 24 Aug 10 07:28:37 PM PDT 24 97345700 ps
T277 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.421145006 Aug 10 07:28:36 PM PDT 24 Aug 10 07:36:15 PM PDT 24 1619592500 ps
T278 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3591155418 Aug 10 07:28:26 PM PDT 24 Aug 10 07:29:12 PM PDT 24 101691000 ps
T1132 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3535566845 Aug 10 07:28:15 PM PDT 24 Aug 10 07:28:30 PM PDT 24 43981300 ps
T252 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2926935259 Aug 10 07:28:33 PM PDT 24 Aug 10 07:36:09 PM PDT 24 368674300 ps
T344 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2259436371 Aug 10 07:28:46 PM PDT 24 Aug 10 07:36:26 PM PDT 24 661788600 ps
T1133 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.735930111 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:43 PM PDT 24 34526300 ps
T1134 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3779082791 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:22 PM PDT 24 203360900 ps
T1135 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.545600817 Aug 10 07:28:37 PM PDT 24 Aug 10 07:28:54 PM PDT 24 245748900 ps
T1136 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.988033064 Aug 10 07:28:44 PM PDT 24 Aug 10 07:29:01 PM PDT 24 62506800 ps
T1137 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1377383917 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:31 PM PDT 24 117344400 ps
T1138 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.616515384 Aug 10 07:28:59 PM PDT 24 Aug 10 07:29:13 PM PDT 24 16435800 ps
T1139 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3519187909 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:14 PM PDT 24 28628900 ps
T1140 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3439059377 Aug 10 07:28:38 PM PDT 24 Aug 10 07:28:55 PM PDT 24 113431000 ps
T1141 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3247532812 Aug 10 07:28:13 PM PDT 24 Aug 10 07:28:43 PM PDT 24 31115500 ps
T1142 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2117236968 Aug 10 07:28:18 PM PDT 24 Aug 10 07:29:04 PM PDT 24 2484023800 ps
T226 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1878691825 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:31 PM PDT 24 52746700 ps
T1143 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.736880902 Aug 10 07:28:36 PM PDT 24 Aug 10 07:28:52 PM PDT 24 29329300 ps
T1144 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3616229023 Aug 10 07:28:09 PM PDT 24 Aug 10 07:28:25 PM PDT 24 25737300 ps
T1145 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1796152852 Aug 10 07:29:00 PM PDT 24 Aug 10 07:29:19 PM PDT 24 170613600 ps
T1146 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.832594525 Aug 10 07:28:52 PM PDT 24 Aug 10 07:29:09 PM PDT 24 65067100 ps
T1147 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2780778537 Aug 10 07:28:37 PM PDT 24 Aug 10 07:28:51 PM PDT 24 17197200 ps
T1148 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1710418650 Aug 10 07:28:14 PM PDT 24 Aug 10 07:28:28 PM PDT 24 35301000 ps
T1149 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1391163730 Aug 10 07:29:02 PM PDT 24 Aug 10 07:29:18 PM PDT 24 311094400 ps
T1150 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.17515442 Aug 10 07:28:16 PM PDT 24 Aug 10 07:29:09 PM PDT 24 1791111300 ps
T1151 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2959774702 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:21 PM PDT 24 14665600 ps
T1152 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2551612175 Aug 10 07:28:51 PM PDT 24 Aug 10 07:29:07 PM PDT 24 39270700 ps
T1153 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.201153457 Aug 10 07:28:45 PM PDT 24 Aug 10 07:28:59 PM PDT 24 16808100 ps
T243 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1173283928 Aug 10 07:28:52 PM PDT 24 Aug 10 07:29:11 PM PDT 24 226508400 ps
T1154 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2149135584 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:29 PM PDT 24 30602600 ps
T247 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2152560970 Aug 10 07:28:30 PM PDT 24 Aug 10 07:28:49 PM PDT 24 109148500 ps
T1155 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4197917507 Aug 10 07:28:25 PM PDT 24 Aug 10 07:28:43 PM PDT 24 45498900 ps
T279 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.549858968 Aug 10 07:28:23 PM PDT 24 Aug 10 07:28:40 PM PDT 24 612626000 ps
T1156 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2656967125 Aug 10 07:28:55 PM PDT 24 Aug 10 07:29:10 PM PDT 24 19164900 ps
T349 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.323835308 Aug 10 07:28:44 PM PDT 24 Aug 10 07:35:14 PM PDT 24 671744000 ps
T1157 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2414185112 Aug 10 07:28:33 PM PDT 24 Aug 10 07:28:48 PM PDT 24 19102700 ps
T1158 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3983829986 Aug 10 07:28:38 PM PDT 24 Aug 10 07:28:55 PM PDT 24 38151800 ps
T280 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1738264717 Aug 10 07:28:52 PM PDT 24 Aug 10 07:29:11 PM PDT 24 415827400 ps
T1159 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4040118059 Aug 10 07:29:07 PM PDT 24 Aug 10 07:29:21 PM PDT 24 25987200 ps
T1160 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.38521827 Aug 10 07:28:50 PM PDT 24 Aug 10 07:29:04 PM PDT 24 21843500 ps
T1161 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.778713970 Aug 10 07:28:39 PM PDT 24 Aug 10 07:28:57 PM PDT 24 58232700 ps
T1162 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2273851362 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:33 PM PDT 24 22900500 ps
T1163 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2553142825 Aug 10 07:28:28 PM PDT 24 Aug 10 07:28:46 PM PDT 24 35626000 ps
T254 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3065040383 Aug 10 07:28:43 PM PDT 24 Aug 10 07:41:29 PM PDT 24 883929700 ps
T1164 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1696163965 Aug 10 07:29:00 PM PDT 24 Aug 10 07:29:14 PM PDT 24 49203800 ps
T242 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.755523835 Aug 10 07:28:39 PM PDT 24 Aug 10 07:28:56 PM PDT 24 148197300 ps
T1165 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4138160940 Aug 10 07:28:11 PM PDT 24 Aug 10 07:28:24 PM PDT 24 56387000 ps
T342 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1191468366 Aug 10 07:28:54 PM PDT 24 Aug 10 07:36:28 PM PDT 24 1413994200 ps
T1166 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4059769801 Aug 10 07:28:35 PM PDT 24 Aug 10 07:28:53 PM PDT 24 40336800 ps
T1167 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4165037613 Aug 10 07:28:39 PM PDT 24 Aug 10 07:28:55 PM PDT 24 14923900 ps
T1168 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3214682953 Aug 10 07:28:30 PM PDT 24 Aug 10 07:28:48 PM PDT 24 842685500 ps
T1169 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2899564453 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:31 PM PDT 24 432706000 ps
T283 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.94847617 Aug 10 07:28:42 PM PDT 24 Aug 10 07:29:00 PM PDT 24 348288200 ps
T339 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2942879667 Aug 10 07:28:28 PM PDT 24 Aug 10 07:43:17 PM PDT 24 368378800 ps
T228 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2599249599 Aug 10 07:28:10 PM PDT 24 Aug 10 07:28:23 PM PDT 24 30370900 ps
T1170 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2872059199 Aug 10 07:28:15 PM PDT 24 Aug 10 07:28:29 PM PDT 24 17648700 ps
T1171 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1327387024 Aug 10 07:28:28 PM PDT 24 Aug 10 07:28:42 PM PDT 24 17095500 ps
T248 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.70100809 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:47 PM PDT 24 116395900 ps
T250 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2829515605 Aug 10 07:28:43 PM PDT 24 Aug 10 07:29:00 PM PDT 24 45748200 ps
T253 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.229328524 Aug 10 07:28:19 PM PDT 24 Aug 10 07:28:39 PM PDT 24 65111800 ps
T1172 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1243965960 Aug 10 07:28:39 PM PDT 24 Aug 10 07:28:55 PM PDT 24 42393200 ps
T281 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2883719036 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:47 PM PDT 24 63661800 ps
T282 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2328066930 Aug 10 07:28:46 PM PDT 24 Aug 10 07:29:07 PM PDT 24 198479100 ps
T1173 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1940711760 Aug 10 07:28:36 PM PDT 24 Aug 10 07:28:56 PM PDT 24 212175400 ps
T1174 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3061276802 Aug 10 07:29:10 PM PDT 24 Aug 10 07:29:23 PM PDT 24 18337700 ps
T343 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3650096410 Aug 10 07:28:17 PM PDT 24 Aug 10 07:40:58 PM PDT 24 3053860900 ps
T255 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1612944960 Aug 10 07:28:44 PM PDT 24 Aug 10 07:29:05 PM PDT 24 88748500 ps
T1175 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1646651314 Aug 10 07:28:49 PM PDT 24 Aug 10 07:29:07 PM PDT 24 89191800 ps
T345 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2109962332 Aug 10 07:28:55 PM PDT 24 Aug 10 07:41:30 PM PDT 24 343752800 ps
T249 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3111235187 Aug 10 07:28:11 PM PDT 24 Aug 10 07:28:31 PM PDT 24 190747400 ps
T1176 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3972274116 Aug 10 07:29:09 PM PDT 24 Aug 10 07:29:22 PM PDT 24 47968200 ps
T1177 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3595012174 Aug 10 07:28:37 PM PDT 24 Aug 10 07:28:50 PM PDT 24 29825600 ps
T1178 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.389226574 Aug 10 07:28:27 PM PDT 24 Aug 10 07:28:40 PM PDT 24 53738300 ps
T1179 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.646157881 Aug 10 07:28:24 PM PDT 24 Aug 10 07:28:38 PM PDT 24 96612600 ps
T1180 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.167850985 Aug 10 07:28:59 PM PDT 24 Aug 10 07:29:20 PM PDT 24 94891000 ps
T1181 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1565757410 Aug 10 07:28:11 PM PDT 24 Aug 10 07:28:24 PM PDT 24 16753100 ps
T1182 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.435886974 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:47 PM PDT 24 91620700 ps
T1183 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1666920534 Aug 10 07:28:42 PM PDT 24 Aug 10 07:28:56 PM PDT 24 19678800 ps
T1184 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1207471232 Aug 10 07:28:22 PM PDT 24 Aug 10 07:28:37 PM PDT 24 98134700 ps
T1185 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1479735841 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:33 PM PDT 24 23875300 ps
T1186 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2591697424 Aug 10 07:28:45 PM PDT 24 Aug 10 07:29:01 PM PDT 24 20003900 ps
T1187 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.363770997 Aug 10 07:28:27 PM PDT 24 Aug 10 07:28:42 PM PDT 24 25756400 ps
T1188 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.448354161 Aug 10 07:28:23 PM PDT 24 Aug 10 07:29:39 PM PDT 24 5342449900 ps
T347 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.795857004 Aug 10 07:28:30 PM PDT 24 Aug 10 07:43:29 PM PDT 24 894183800 ps
T1189 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1287056689 Aug 10 07:28:49 PM PDT 24 Aug 10 07:29:05 PM PDT 24 87810900 ps
T1190 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2756798403 Aug 10 07:28:10 PM PDT 24 Aug 10 07:28:26 PM PDT 24 91074600 ps
T1191 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3711164493 Aug 10 07:28:37 PM PDT 24 Aug 10 07:28:51 PM PDT 24 45029100 ps
T1192 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2355148366 Aug 10 07:28:42 PM PDT 24 Aug 10 07:28:56 PM PDT 24 14614800 ps
T1193 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1125631987 Aug 10 07:28:43 PM PDT 24 Aug 10 07:29:01 PM PDT 24 57317400 ps
T229 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2324676041 Aug 10 07:28:11 PM PDT 24 Aug 10 07:28:24 PM PDT 24 18208100 ps
T1194 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1779123928 Aug 10 07:29:11 PM PDT 24 Aug 10 07:29:25 PM PDT 24 15103100 ps
T1195 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3196012060 Aug 10 07:29:02 PM PDT 24 Aug 10 07:29:16 PM PDT 24 57074700 ps
T1196 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4196695283 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:22 PM PDT 24 30125100 ps
T1197 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3939601885 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:30 PM PDT 24 28876800 ps
T1198 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.283847933 Aug 10 07:28:39 PM PDT 24 Aug 10 07:28:52 PM PDT 24 17687900 ps
T340 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2926063279 Aug 10 07:28:53 PM PDT 24 Aug 10 07:35:22 PM PDT 24 689725500 ps
T348 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2204639530 Aug 10 07:28:39 PM PDT 24 Aug 10 07:43:36 PM PDT 24 671498800 ps
T284 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1295920908 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:18 PM PDT 24 61012400 ps
T1199 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2719344614 Aug 10 07:28:30 PM PDT 24 Aug 10 07:28:49 PM PDT 24 377922100 ps
T1200 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3458514061 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:33 PM PDT 24 56188700 ps
T1201 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3514712012 Aug 10 07:28:50 PM PDT 24 Aug 10 07:29:03 PM PDT 24 26852000 ps
T1202 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3590712289 Aug 10 07:28:49 PM PDT 24 Aug 10 07:29:06 PM PDT 24 93062300 ps
T1203 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.714809158 Aug 10 07:28:13 PM PDT 24 Aug 10 07:28:53 PM PDT 24 1337236300 ps
T1204 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3815095414 Aug 10 07:29:00 PM PDT 24 Aug 10 07:29:14 PM PDT 24 131719400 ps
T1205 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.888888898 Aug 10 07:28:16 PM PDT 24 Aug 10 07:29:16 PM PDT 24 2881842800 ps
T1206 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1606145605 Aug 10 07:28:55 PM PDT 24 Aug 10 07:29:12 PM PDT 24 25465700 ps
T1207 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3231658136 Aug 10 07:28:30 PM PDT 24 Aug 10 07:28:48 PM PDT 24 26422400 ps
T1208 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1229421245 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 16303000 ps
T1209 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3770908421 Aug 10 07:28:23 PM PDT 24 Aug 10 07:28:39 PM PDT 24 118851400 ps
T1210 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.300675849 Aug 10 07:28:14 PM PDT 24 Aug 10 07:28:29 PM PDT 24 22241600 ps
T1211 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2192002331 Aug 10 07:28:22 PM PDT 24 Aug 10 07:28:36 PM PDT 24 52134900 ps
T256 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3262196157 Aug 10 07:28:28 PM PDT 24 Aug 10 07:28:47 PM PDT 24 542445200 ps
T1212 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.891406866 Aug 10 07:28:23 PM PDT 24 Aug 10 07:28:43 PM PDT 24 313729500 ps
T346 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1399830158 Aug 10 07:28:13 PM PDT 24 Aug 10 07:34:42 PM PDT 24 1773001200 ps
T1213 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2993504418 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:43 PM PDT 24 16614800 ps
T1214 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1047947270 Aug 10 07:28:24 PM PDT 24 Aug 10 07:28:40 PM PDT 24 12955400 ps
T1215 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3905321298 Aug 10 07:28:38 PM PDT 24 Aug 10 07:28:52 PM PDT 24 18656500 ps
T1216 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1912399390 Aug 10 07:29:02 PM PDT 24 Aug 10 07:29:16 PM PDT 24 43343800 ps
T341 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1092407937 Aug 10 07:28:26 PM PDT 24 Aug 10 07:36:10 PM PDT 24 177969900 ps
T1217 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3399662407 Aug 10 07:28:14 PM PDT 24 Aug 10 07:35:56 PM PDT 24 657882000 ps
T1218 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.203778605 Aug 10 07:28:22 PM PDT 24 Aug 10 07:28:38 PM PDT 24 819557700 ps
T1219 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3040109309 Aug 10 07:28:49 PM PDT 24 Aug 10 07:29:06 PM PDT 24 304936100 ps
T1220 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3019872399 Aug 10 07:28:43 PM PDT 24 Aug 10 07:29:02 PM PDT 24 97854000 ps
T1221 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.912287252 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 43137800 ps
T1222 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1569954087 Aug 10 07:28:47 PM PDT 24 Aug 10 07:29:23 PM PDT 24 824230300 ps
T1223 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.872477762 Aug 10 07:28:23 PM PDT 24 Aug 10 07:29:17 PM PDT 24 439369200 ps
T1224 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2833609055 Aug 10 07:28:39 PM PDT 24 Aug 10 07:28:52 PM PDT 24 16658700 ps
T1225 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1064413990 Aug 10 07:28:47 PM PDT 24 Aug 10 07:29:00 PM PDT 24 11821000 ps
T1226 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1791006802 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:22 PM PDT 24 14739000 ps
T1227 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.312440661 Aug 10 07:29:10 PM PDT 24 Aug 10 07:29:23 PM PDT 24 18430800 ps
T1228 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.623794862 Aug 10 07:28:24 PM PDT 24 Aug 10 07:28:55 PM PDT 24 28903000 ps
T1229 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2026404420 Aug 10 07:28:28 PM PDT 24 Aug 10 07:28:48 PM PDT 24 65945500 ps
T1230 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2209841667 Aug 10 07:28:44 PM PDT 24 Aug 10 07:29:01 PM PDT 24 60770500 ps
T1231 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2500242298 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:22 PM PDT 24 267527000 ps
T1232 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.339697296 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 29591000 ps
T1233 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1332627747 Aug 10 07:28:26 PM PDT 24 Aug 10 07:29:38 PM PDT 24 15536215700 ps
T1234 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1102404734 Aug 10 07:29:01 PM PDT 24 Aug 10 07:29:15 PM PDT 24 47707700 ps
T1235 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1349195144 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:22 PM PDT 24 18002600 ps
T1236 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3754364395 Aug 10 07:28:27 PM PDT 24 Aug 10 07:28:43 PM PDT 24 125486500 ps
T1237 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2113859431 Aug 10 07:28:29 PM PDT 24 Aug 10 07:28:43 PM PDT 24 34842100 ps
T1238 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2340404964 Aug 10 07:28:46 PM PDT 24 Aug 10 07:28:59 PM PDT 24 13959500 ps
T1239 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2019945814 Aug 10 07:28:11 PM PDT 24 Aug 10 07:28:27 PM PDT 24 38433500 ps
T1240 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.38681438 Aug 10 07:28:37 PM PDT 24 Aug 10 07:28:54 PM PDT 24 183832900 ps
T1241 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1464216253 Aug 10 07:28:55 PM PDT 24 Aug 10 07:29:14 PM PDT 24 534357200 ps
T1242 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1303276696 Aug 10 07:28:25 PM PDT 24 Aug 10 07:28:43 PM PDT 24 68442800 ps
T1243 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3969905721 Aug 10 07:28:16 PM PDT 24 Aug 10 07:28:32 PM PDT 24 34717700 ps
T1244 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2377424782 Aug 10 07:28:14 PM PDT 24 Aug 10 07:28:28 PM PDT 24 80712600 ps
T1245 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1632657313 Aug 10 07:28:30 PM PDT 24 Aug 10 07:28:43 PM PDT 24 15191600 ps
T1246 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2176917866 Aug 10 07:28:36 PM PDT 24 Aug 10 07:28:49 PM PDT 24 23415200 ps
T1247 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3226013250 Aug 10 07:28:38 PM PDT 24 Aug 10 07:28:55 PM PDT 24 76500900 ps
T1248 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2086496587 Aug 10 07:28:17 PM PDT 24 Aug 10 07:28:34 PM PDT 24 542577400 ps
T1249 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2564867880 Aug 10 07:29:08 PM PDT 24 Aug 10 07:29:22 PM PDT 24 24571200 ps
T1250 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.55935319 Aug 10 07:28:23 PM PDT 24 Aug 10 07:28:39 PM PDT 24 108082100 ps
T1251 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3928791617 Aug 10 07:29:06 PM PDT 24 Aug 10 07:29:20 PM PDT 24 20270100 ps
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