Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.03	95.24	93.81	98.31	92.52	97.16	96.99	98.18

Total test records in report: 1260

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1252	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.622190483			Aug 10 07:28:42 PM PDT 24	Aug 10 07:28:58 PM PDT 24	435271700 ps
T230	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1139382154			Aug 10 07:28:22 PM PDT 24	Aug 10 07:28:36 PM PDT 24	59670600 ps
T1253	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1652615948			Aug 10 07:28:16 PM PDT 24	Aug 10 07:28:32 PM PDT 24	29670800 ps
T1254	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1694187551			Aug 10 07:28:39 PM PDT 24	Aug 10 07:28:54 PM PDT 24	13026400 ps
T1255	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.829248673			Aug 10 07:28:52 PM PDT 24	Aug 10 07:29:05 PM PDT 24	15068900 ps
T1256	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2108751792			Aug 10 07:28:26 PM PDT 24	Aug 10 07:29:17 PM PDT 24	4090881900 ps
T1257	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3608781384			Aug 10 07:28:23 PM PDT 24	Aug 10 07:36:04 PM PDT 24	308194700 ps
T1258	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2586529495			Aug 10 07:29:02 PM PDT 24	Aug 10 07:29:15 PM PDT 24	15187100 ps
T1259	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1268429749			Aug 10 07:28:36 PM PDT 24	Aug 10 07:28:52 PM PDT 24	21368400 ps
T1260	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4200828003			Aug 10 07:28:38 PM PDT 24	Aug 10 07:28:52 PM PDT 24	25078500 ps

Test location	/workspace/coverage/default/2.flash_ctrl_rw_serr.1235039659
Short name	T7
Test name
Test status
Simulation time	1752288100 ps
CPU time	217.09 seconds
Started	Aug 10 07:34:16 PM PDT 24
Finished	Aug 10 07:37:53 PM PDT 24
Peak memory	282568 kb
Host	smart-cbe4744f-754d-4837-bec0-95ea6d1dcf50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235039659 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.flash_ctrl_rw_serr.1235039659
Directory	/workspace/2.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.496738017
Short name	T24
Test name
Test status
Simulation time	28510650200 ps
CPU time	806.41 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 07:50:00 PM PDT 24
Peak memory	276096 kb
Host	smart-6c4ab663-6309-4055-a882-23027819aeda
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496738017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.496738017
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1025115118
Short name	T11
Test name
Test status
Simulation time	80153917500 ps
CPU time	906.91 seconds
Started	Aug 10 07:38:07 PM PDT 24
Finished	Aug 10 07:53:14 PM PDT 24
Peak memory	265580 kb
Host	smart-bc989f60-cea9-48a9-a495-771ad8808c69
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025115118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.1025115118
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1804525006
Short name	T124
Test name
Test status
Simulation time	196033400 ps
CPU time	390.55 seconds
Started	Aug 10 07:28:50 PM PDT 24
Finished	Aug 10 07:35:21 PM PDT 24
Peak memory	264336 kb
Host	smart-f0b925e0-7dd9-48bf-adaa-c87004c8775b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804525006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.1804525006
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2154062346
Short name	T115
Test name
Test status
Simulation time	5287413600 ps
CPU time	125.63 seconds
Started	Aug 10 07:41:29 PM PDT 24
Finished	Aug 10 07:43:34 PM PDT 24
Peak memory	261660 kb
Host	smart-9c30d793-4334-46db-9acf-00d81347f042
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154062346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ hw_sec_otp.2154062346
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.1985357556
Short name	T13
Test name
Test status
Simulation time	6534825300 ps
CPU time	4881.26 seconds
Started	Aug 10 07:33:59 PM PDT 24
Finished	Aug 10 08:55:21 PM PDT 24
Peak memory	291144 kb
Host	smart-642594d8-5559-4c28-95ab-f4575ac576ba
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985357556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1985357556
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.462614875
Short name	T222
Test name
Test status
Simulation time	99089700 ps
CPU time	18.44 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	272804 kb
Host	smart-db3fc820-904d-4d46-9fb3-45d1af6042a3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462614875 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.462614875
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.4159591811
Short name	T59
Test name
Test status
Simulation time	1423643800 ps
CPU time	368.14 seconds
Started	Aug 10 07:35:00 PM PDT 24
Finished	Aug 10 07:41:08 PM PDT 24
Peak memory	264008 kb
Host	smart-51feaa52-e9bc-455a-94d8-5bd20a8d25a0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4159591811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.4159591811
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.803171437
Short name	T18
Test name
Test status
Simulation time	1010164000 ps
CPU time	144.46 seconds
Started	Aug 10 07:35:16 PM PDT 24
Finished	Aug 10 07:37:41 PM PDT 24
Peak memory	282460 kb
Host	smart-7e800cbb-e6bc-41b7-b1f3-ca13cdf85cb5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803171437 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.803171437
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.2004560825
Short name	T65
Test name
Test status
Simulation time	70031600 ps
CPU time	130.94 seconds
Started	Aug 10 07:42:33 PM PDT 24
Finished	Aug 10 07:44:44 PM PDT 24
Peak memory	260556 kb
Host	smart-bc74e47f-78b9-42c9-8b1b-f15b12b7878d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004560825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.2004560825
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1589101098
Short name	T210
Test name
Test status
Simulation time	907259400 ps
CPU time	760.87 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:41:20 PM PDT 24
Peak memory	264276 kb
Host	smart-e72a1127-5710-4f50-9170-b321597aa51f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589101098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.1589101098
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.887983884
Short name	T4
Test name
Test status
Simulation time	14188929400 ps
CPU time	344.8 seconds
Started	Aug 10 07:36:16 PM PDT 24
Finished	Aug 10 07:42:01 PM PDT 24
Peak memory	293912 kb
Host	smart-4ba60911-86c4-43ab-852c-60c2dde70c90
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887983884 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.887983884
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.1556189363
Short name	T57
Test name
Test status
Simulation time	1479543800 ps
CPU time	74.8 seconds
Started	Aug 10 07:33:54 PM PDT 24
Finished	Aug 10 07:35:09 PM PDT 24
Peak memory	261172 kb
Host	smart-cee426a4-d168-4f7d-ad7b-452c535b12ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556189363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1556189363
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3223278677
Short name	T301
Test name
Test status
Simulation time	44171700 ps
CPU time	13.33 seconds
Started	Aug 10 07:28:09 PM PDT 24
Finished	Aug 10 07:28:22 PM PDT 24
Peak memory	261784 kb
Host	smart-3d351b6a-be89-429c-82f0-f2093e85da7e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223278677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3 223278677
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.2556107093
Short name	T101
Test name
Test status
Simulation time	40749646900 ps
CPU time	876.79 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:48:46 PM PDT 24
Peak memory	261924 kb
Host	smart-8b1b6df5-60f0-4995-b77a-2bc387d58cb5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556107093 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2556107093
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.4029073470
Short name	T179
Test name
Test status
Simulation time	148171600 ps
CPU time	112.33 seconds
Started	Aug 10 07:41:05 PM PDT 24
Finished	Aug 10 07:42:57 PM PDT 24
Peak memory	261844 kb
Host	smart-3497ce7c-c205-469e-83e6-4836469cc478
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029073470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o tp_reset.4029073470
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.2085185923
Short name	T96
Test name
Test status
Simulation time	58946300 ps
CPU time	131.16 seconds
Started	Aug 10 07:35:31 PM PDT 24
Finished	Aug 10 07:37:42 PM PDT 24
Peak memory	263888 kb
Host	smart-3f2d2446-19e9-4b05-86c6-5aa99afdc78f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085185923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot p_reset.2085185923
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.120183220
Short name	T147
Test name
Test status
Simulation time	15461900 ps
CPU time	13.86 seconds
Started	Aug 10 07:38:46 PM PDT 24
Finished	Aug 10 07:39:00 PM PDT 24
Peak memory	265420 kb
Host	smart-8cd3d173-ca3e-4ece-9b2b-e42ed5424814
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120183220 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.120183220
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_derr_detect.2968286215
Short name	T85
Test name
Test status
Simulation time	2503019300 ps
CPU time	200.24 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 07:37:38 PM PDT 24
Peak memory	281932 kb
Host	smart-d2c35c01-2f9d-44b7-94a8-6ba1bf2912d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968286215 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.2968286215
Directory	/workspace/2.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1631979541
Short name	T107
Test name
Test status
Simulation time	10033247600 ps
CPU time	109.82 seconds
Started	Aug 10 07:37:57 PM PDT 24
Finished	Aug 10 07:39:47 PM PDT 24
Peak memory	275924 kb
Host	smart-e3db6927-b8c8-438e-98d6-a5f108bca258
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631979541 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1631979541
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.3683568096
Short name	T169
Test name
Test status
Simulation time	2642502300 ps
CPU time	65.53 seconds
Started	Aug 10 07:41:12 PM PDT 24
Finished	Aug 10 07:42:18 PM PDT 24
Peak memory	263804 kb
Host	smart-5f7624ab-fa3e-467d-b4f9-d5c59077b943
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683568096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3683568096
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.894667014
Short name	T8
Test name
Test status
Simulation time	139911000 ps
CPU time	15.12 seconds
Started	Aug 10 07:34:21 PM PDT 24
Finished	Aug 10 07:34:36 PM PDT 24
Peak memory	261644 kb
Host	smart-798413f3-7c78-4ca4-b45a-425df689ce2d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894667014 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.894667014
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.390537960
Short name	T223
Test name
Test status
Simulation time	339222400 ps
CPU time	20.43 seconds
Started	Aug 10 07:28:45 PM PDT 24
Finished	Aug 10 07:29:06 PM PDT 24
Peak memory	264376 kb
Host	smart-024e6781-566b-4e19-a5d7-1eaf590d91dc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390537960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.390537960
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.4257231819
Short name	T28
Test name
Test status
Simulation time	40869500 ps
CPU time	31.13 seconds
Started	Aug 10 07:40:35 PM PDT 24
Finished	Aug 10 07:41:07 PM PDT 24
Peak memory	274252 kb
Host	smart-2374ec37-0dbe-4ef7-9b4b-405eea861d68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257231819 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.4257231819
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.2075351484
Short name	T396
Test name
Test status
Simulation time	112381000 ps
CPU time	13.45 seconds
Started	Aug 10 07:37:45 PM PDT 24
Finished	Aug 10 07:37:58 PM PDT 24
Peak memory	258944 kb
Host	smart-c601fe0a-5c7f-4d5d-a2c7-66578f2652ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075351484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 2075351484
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.471128350
Short name	T45
Test name
Test status
Simulation time	3381110000 ps
CPU time	22.54 seconds
Started	Aug 10 07:36:54 PM PDT 24
Finished	Aug 10 07:37:17 PM PDT 24
Peak memory	263080 kb
Host	smart-864b7815-f800-4211-a6a7-4182d47d90c3
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471128350 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.471128350
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.772310863
Short name	T184
Test name
Test status
Simulation time	260017988100 ps
CPU time	2465.17 seconds
Started	Aug 10 07:34:27 PM PDT 24
Finished	Aug 10 08:15:32 PM PDT 24
Peak memory	264744 kb
Host	smart-edebb080-5a20-4bdf-8e29-d127392a2384
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772310863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.flash_ctrl_host_ctrl_arb.772310863
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.4169655794
Short name	T910
Test name
Test status
Simulation time	66151300 ps
CPU time	131.96 seconds
Started	Aug 10 07:41:29 PM PDT 24
Finished	Aug 10 07:43:41 PM PDT 24
Peak memory	260648 kb
Host	smart-195fc833-e123-47bc-bf65-8098b8ee7315
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169655794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.4169655794
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.2723417386
Short name	T74
Test name
Test status
Simulation time	1396341700 ps
CPU time	72.71 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:35:21 PM PDT 24
Peak memory	261336 kb
Host	smart-739ae451-0ba2-43b4-9727-e74149238313
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723417386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2723417386
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.2349425709
Short name	T93
Test name
Test status
Simulation time	33764200 ps
CPU time	13.36 seconds
Started	Aug 10 07:40:31 PM PDT 24
Finished	Aug 10 07:40:45 PM PDT 24
Peak memory	259540 kb
Host	smart-4eafb4b3-3fda-405e-97ad-45646218b558
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349425709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.2349425709
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.3449934298
Short name	T148
Test name
Test status
Simulation time	1804032300 ps
CPU time	240.25 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 07:38:18 PM PDT 24
Peak memory	290168 kb
Host	smart-99d5e60e-b972-4259-af43-6467a8094dd4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449934298 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_derr.3449934298
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.2411394402
Short name	T319
Test name
Test status
Simulation time	75687700 ps
CPU time	36.24 seconds
Started	Aug 10 07:39:38 PM PDT 24
Finished	Aug 10 07:40:15 PM PDT 24
Peak memory	276640 kb
Host	smart-3e70db02-8274-4689-9846-02fc61d25d24
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411394402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_re_evict.2411394402
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1878691825
Short name	T226
Test name
Test status
Simulation time	52746700 ps
CPU time	13.62 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:31 PM PDT 24
Peak memory	263416 kb
Host	smart-409ef6fd-4d0c-458f-87a2-f7ef897d9cef
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878691825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_mem_partial_access.1878691825
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2566372677
Short name	T125
Test name
Test status
Simulation time	127215700 ps
CPU time	16.69 seconds
Started	Aug 10 07:29:02 PM PDT 24
Finished	Aug 10 07:29:18 PM PDT 24
Peak memory	264292 kb
Host	smart-3d74dba9-ccf9-468a-8c92-a1805d48bfa2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566372677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors. 2566372677
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.3444098801
Short name	T304
Test name
Test status
Simulation time	801862200 ps
CPU time	139.65 seconds
Started	Aug 10 07:40:07 PM PDT 24
Finished	Aug 10 07:42:27 PM PDT 24
Peak memory	295020 kb
Host	smart-96885738-57b9-4819-9f79-924fdd505f14
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444098801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_intr_rd.3444098801
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.29034945
Short name	T53
Test name
Test status
Simulation time	15730400 ps
CPU time	14.44 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:34:24 PM PDT 24
Peak memory	263640 kb
Host	smart-0f482002-b95a-403c-8790-e19b5360e5ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034945 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.29034945
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.1734461806
Short name	T389
Test name
Test status
Simulation time	3336140800 ps
CPU time	77.92 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:35:28 PM PDT 24
Peak memory	263348 kb
Host	smart-38ec943b-8741-4431-b504-2232e4a778de
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734461806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1734461806
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.4108160615
Short name	T193
Test name
Test status
Simulation time	10012489100 ps
CPU time	149.56 seconds
Started	Aug 10 07:33:57 PM PDT 24
Finished	Aug 10 07:36:26 PM PDT 24
Peak memory	385364 kb
Host	smart-bea07f92-7178-42dd-b1f7-f26d71442e90
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108160615 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.4108160615
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.3263882778
Short name	T290
Test name
Test status
Simulation time	79162200 ps
CPU time	134.41 seconds
Started	Aug 10 07:37:29 PM PDT 24
Finished	Aug 10 07:39:43 PM PDT 24
Peak memory	260620 kb
Host	smart-346e4bc8-2570-4c9f-af7a-9613ccdc1d9b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263882778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o tp_reset.3263882778
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.1587126742
Short name	T359
Test name
Test status
Simulation time	15315800 ps
CPU time	22.15 seconds
Started	Aug 10 07:39:22 PM PDT 24
Finished	Aug 10 07:39:45 PM PDT 24
Peak memory	274348 kb
Host	smart-47aab52f-c937-4554-94f8-99ba433993af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587126742 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.1587126742
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2109962332
Short name	T345
Test name
Test status
Simulation time	343752800 ps
CPU time	754.67 seconds
Started	Aug 10 07:28:55 PM PDT 24
Finished	Aug 10 07:41:30 PM PDT 24
Peak memory	264344 kb
Host	smart-68a714a1-fe5b-42a9-91eb-65f7d7a3bea5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109962332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.2109962332
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.152565359
Short name	T50
Test name
Test status
Simulation time	706014300 ps
CPU time	22.77 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:34:35 PM PDT 24
Peak memory	266088 kb
Host	smart-4f18a171-1b5f-4c02-bb7d-2458e5706cd6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152565359 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.152565359
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.3804652670
Short name	T104
Test name
Test status
Simulation time	810813000 ps
CPU time	38.79 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 07:35:25 PM PDT 24
Peak memory	263544 kb
Host	smart-91aeda90-202b-4c5d-b1e8-e8959999d21f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804652670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_fs_sup.3804652670
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.36561747
Short name	T121
Test name
Test status
Simulation time	15448200 ps
CPU time	13.95 seconds
Started	Aug 10 07:36:49 PM PDT 24
Finished	Aug 10 07:37:03 PM PDT 24
Peak memory	260680 kb
Host	smart-f7916f78-7138-47d9-aba0-5a13da0b8eff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36561747 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.36561747
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4287711333
Short name	T69
Test name
Test status
Simulation time	22172500 ps
CPU time	14.32 seconds
Started	Aug 10 07:33:58 PM PDT 24
Finished	Aug 10 07:34:12 PM PDT 24
Peak memory	277944 kb
Host	smart-fcd93384-baa9-4296-befe-c7f51b353b8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4287711333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4287711333
Directory	/workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.3268666790
Short name	T10
Test name
Test status
Simulation time	23827800 ps
CPU time	13.88 seconds
Started	Aug 10 07:33:59 PM PDT 24
Finished	Aug 10 07:34:13 PM PDT 24
Peak memory	262208 kb
Host	smart-b49eb82a-c420-498e-8552-598bbf4e0a41
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268666790 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3268666790
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.551653448
Short name	T36
Test name
Test status
Simulation time	13384295300 ps
CPU time	264.61 seconds
Started	Aug 10 07:37:51 PM PDT 24
Finished	Aug 10 07:42:16 PM PDT 24
Peak memory	290480 kb
Host	smart-dc7212da-a065-4c8f-b467-32a3ae8993d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551653448 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.551653448
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.4081417872
Short name	T78
Test name
Test status
Simulation time	13618366100 ps
CPU time	473.06 seconds
Started	Aug 10 07:35:00 PM PDT 24
Finished	Aug 10 07:42:53 PM PDT 24
Peak memory	275332 kb
Host	smart-20c9e408-dadd-4c77-bc92-d17de586ff15
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081417872 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.4081417872
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.339773880
Short name	T91
Test name
Test status
Simulation time	318171200 ps
CPU time	466.79 seconds
Started	Aug 10 07:34:05 PM PDT 24
Finished	Aug 10 07:41:52 PM PDT 24
Peak memory	282136 kb
Host	smart-ff50dac2-3353-4c79-b850-fe8f0441a36d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339773880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.339773880
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.500178528
Short name	T231
Test name
Test status
Simulation time	230703900 ps
CPU time	19.23 seconds
Started	Aug 10 07:28:13 PM PDT 24
Finished	Aug 10 07:28:33 PM PDT 24
Peak memory	262112 kb
Host	smart-1631c34e-3a1e-4033-972d-d4ed891e7809
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500178528 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.500178528
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3650096410
Short name	T343
Test name
Test status
Simulation time	3053860900 ps
CPU time	761.28 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:40:58 PM PDT 24
Peak memory	264332 kb
Host	smart-db1159f7-b6d5-4dc4-ab32-c92b9e6f5ede
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650096410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.3650096410
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1889063422
Short name	T1130
Test name
Test status
Simulation time	25843600 ps
CPU time	13.43 seconds
Started	Aug 10 07:29:07 PM PDT 24
Finished	Aug 10 07:29:20 PM PDT 24
Peak memory	261864 kb
Host	smart-446a097c-c6d8-4282-a157-4a78c642e978
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889063422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 1889063422
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.240280321
Short name	T43
Test name
Test status
Simulation time	986587800 ps
CPU time	162.55 seconds
Started	Aug 10 07:33:52 PM PDT 24
Finished	Aug 10 07:36:35 PM PDT 24
Peak memory	296152 kb
Host	smart-e2107325-2695-4587-a231-2a820278d8a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240280321 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.240280321
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.2390802258
Short name	T321
Test name
Test status
Simulation time	149337400 ps
CPU time	33.55 seconds
Started	Aug 10 07:37:45 PM PDT 24
Finished	Aug 10 07:38:18 PM PDT 24
Peak memory	276304 kb
Host	smart-da40a177-ab01-40d3-947a-8962d0ef996f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390802258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_rw_evict.2390802258
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.779782743
Short name	T786
Test name
Test status
Simulation time	45511800 ps
CPU time	13.76 seconds
Started	Aug 10 07:38:14 PM PDT 24
Finished	Aug 10 07:38:27 PM PDT 24
Peak memory	265260 kb
Host	smart-542e27e7-39f0-4e40-96e1-999b08f591c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779782743 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.779782743
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.3742978059
Short name	T144
Test name
Test status
Simulation time	977618400 ps
CPU time	76.38 seconds
Started	Aug 10 07:38:07 PM PDT 24
Finished	Aug 10 07:39:24 PM PDT 24
Peak memory	261216 kb
Host	smart-a8a890b0-5422-431e-8b9d-2393c762b421
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742978059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3 742978059
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3231959354
Short name	T798
Test name
Test status
Simulation time	86695200 ps
CPU time	13.61 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:34:23 PM PDT 24
Peak memory	265372 kb
Host	smart-f20d4500-d9f9-4b03-9027-a2ccd5635f12
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231959354 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3231959354
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2202562098
Short name	T268
Test name
Test status
Simulation time	10012296300 ps
CPU time	104.83 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:39:07 PM PDT 24
Peak memory	288424 kb
Host	smart-3d70ec08-489b-480c-af53-d044267c1b07
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202562098 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2202562098
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.2117478429
Short name	T129
Test name
Test status
Simulation time	42764000 ps
CPU time	13.51 seconds
Started	Aug 10 07:37:57 PM PDT 24
Finished	Aug 10 07:38:11 PM PDT 24
Peak memory	275484 kb
Host	smart-2d256d24-e1ee-4dad-a309-37d647a3cd00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117478429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2117478429
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2152560970
Short name	T247
Test name
Test status
Simulation time	109148500 ps
CPU time	19.11 seconds
Started	Aug 10 07:28:30 PM PDT 24
Finished	Aug 10 07:28:49 PM PDT 24
Peak memory	263604 kb
Host	smart-3c757ec4-f62d-4b1f-85ba-d99a85a1dc11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152560970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2 152560970
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.3358699258
Short name	T843
Test name
Test status
Simulation time	477161300 ps
CPU time	2544.84 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 08:16:16 PM PDT 24
Peak memory	265240 kb
Host	smart-c91140d0-2192-4c89-9f59-2fedcdc61559
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358699258 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.3358699258
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.1981372173
Short name	T594
Test name
Test status
Simulation time	4363909200 ps
CPU time	570.35 seconds
Started	Aug 10 07:33:52 PM PDT 24
Finished	Aug 10 07:43:23 PM PDT 24
Peak memory	319708 kb
Host	smart-29aba07e-eeaf-4617-b910-01b1f18f8665
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981372173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.1981372173
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.242013952
Short name	T128
Test name
Test status
Simulation time	543600948800 ps
CPU time	2094.94 seconds
Started	Aug 10 07:34:03 PM PDT 24
Finished	Aug 10 08:08:59 PM PDT 24
Peak memory	261096 kb
Host	smart-2300c5c8-52f5-4c98-98e3-8cc8b24f92a1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242013952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_hw_rma.242013952
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.1794350163
Short name	T134
Test name
Test status
Simulation time	1542132100 ps
CPU time	57.9 seconds
Started	Aug 10 07:38:27 PM PDT 24
Finished	Aug 10 07:39:25 PM PDT 24
Peak memory	264396 kb
Host	smart-a7b0d353-4601-4759-8f64-5d87e1818f66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794350163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1794350163
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.537493098
Short name	T386
Test name
Test status
Simulation time	1437043400 ps
CPU time	54.64 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:35:14 PM PDT 24
Peak memory	263852 kb
Host	smart-8526d05e-2cb6-45ee-9fd6-5151a8e71406
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537493098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.537493098
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.3951442894
Short name	T351
Test name
Test status
Simulation time	868685300 ps
CPU time	60.03 seconds
Started	Aug 10 07:42:13 PM PDT 24
Finished	Aug 10 07:43:13 PM PDT 24
Peak memory	264296 kb
Host	smart-db343f9d-ec97-492f-854c-3cfeaea3e2b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951442894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3951442894
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.909502947
Short name	T257
Test name
Test status
Simulation time	177820000 ps
CPU time	123.25 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:36:05 PM PDT 24
Peak memory	265908 kb
Host	smart-3ff220a4-0b4c-4206-a016-1ca093dee6b0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=909502947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.909502947
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.3397703413
Short name	T286
Test name
Test status
Simulation time	8856472400 ps
CPU time	139.21 seconds
Started	Aug 10 07:37:13 PM PDT 24
Finished	Aug 10 07:39:32 PM PDT 24
Peak memory	263976 kb
Host	smart-c2d69207-219d-45a9-9100-fbf298078515
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397703413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ hw_sec_otp.3397703413
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.3548921361
Short name	T174
Test name
Test status
Simulation time	100151087600 ps
CPU time	828.83 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:48:15 PM PDT 24
Peak memory	265060 kb
Host	smart-3f78b626-f5c2-46fa-acc0-a5fc4991edd0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548921361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.flash_ctrl_hw_rma_reset.3548921361
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.2214952449
Short name	T323
Test name
Test status
Simulation time	38948500 ps
CPU time	29.77 seconds
Started	Aug 10 07:39:23 PM PDT 24
Finished	Aug 10 07:39:53 PM PDT 24
Peak memory	276364 kb
Host	smart-f6383d0d-d2c5-4420-96a1-b643c0cd3912
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214952449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.2214952449
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.2770513965
Short name	T15
Test name
Test status
Simulation time	1111186200 ps
CPU time	4893.69 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 08:55:44 PM PDT 24
Peak memory	284592 kb
Host	smart-50912553-f39a-4e65-89bb-0567fd9a58c8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770513965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2770513965
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.363419966
Short name	T211
Test name
Test status
Simulation time	99608700 ps
CPU time	20.76 seconds
Started	Aug 10 07:28:45 PM PDT 24
Finished	Aug 10 07:29:05 PM PDT 24
Peak memory	264356 kb
Host	smart-32ed812f-9f54-469d-afbd-792ce3c2b71c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363419966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.363419966
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.518427966
Short name	T163
Test name
Test status
Simulation time	765918000 ps
CPU time	17.66 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:37 PM PDT 24
Peak memory	266132 kb
Host	smart-8acd435a-07eb-4831-be02-58febd955612
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518427966 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.518427966
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.4207287390
Short name	T164
Test name
Test status
Simulation time	895671100 ps
CPU time	23.09 seconds
Started	Aug 10 07:34:49 PM PDT 24
Finished	Aug 10 07:35:12 PM PDT 24
Peak memory	266344 kb
Host	smart-805a92b1-dbc7-40a7-82b2-a4ad8b266280
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207287390 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.4207287390
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.2103981213
Short name	T27
Test name
Test status
Simulation time	25353011300 ps
CPU time	90.77 seconds
Started	Aug 10 07:36:40 PM PDT 24
Finished	Aug 10 07:38:11 PM PDT 24
Peak memory	265844 kb
Host	smart-8ce59115-65dc-4761-bc20-f8530e869173
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103981213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_wr.2103981213
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3974150148
Short name	T860
Test name
Test status
Simulation time	30609500 ps
CPU time	13.51 seconds
Started	Aug 10 07:37:45 PM PDT 24
Finished	Aug 10 07:37:58 PM PDT 24
Peak memory	265316 kb
Host	smart-a8fb2c7d-7f65-4d0c-9e2a-a329ad028c02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974150148 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3974150148
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2926063279
Short name	T340
Test name
Test status
Simulation time	689725500 ps
CPU time	388.7 seconds
Started	Aug 10 07:28:53 PM PDT 24
Finished	Aug 10 07:35:22 PM PDT 24
Peak memory	264324 kb
Host	smart-d16e9396-06a3-461a-aab9-ca8450ee9ba1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926063279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr l_tl_intg_err.2926063279
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.2791848398
Short name	T208
Test name
Test status
Simulation time	84356800 ps
CPU time	13.85 seconds
Started	Aug 10 07:34:00 PM PDT 24
Finished	Aug 10 07:34:14 PM PDT 24
Peak memory	265448 kb
Host	smart-29a03025-3102-4eaf-b0f9-df9a1f9c0355
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791848398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.2791848398
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.2311277208
Short name	T378
Test name
Test status
Simulation time	3599634300 ps
CPU time	73.1 seconds
Started	Aug 10 07:33:58 PM PDT 24
Finished	Aug 10 07:35:11 PM PDT 24
Peak memory	265488 kb
Host	smart-eaeaeefc-47a9-4c6f-98da-90d9e8bfd607
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311277208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2311277208
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.229482608
Short name	T372
Test name
Test status
Simulation time	27595200 ps
CPU time	22.2 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:34:31 PM PDT 24
Peak memory	274200 kb
Host	smart-c7a742bd-1f74-4e5c-a866-de2e81c3986d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229482608 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.229482608
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.1850296573
Short name	T781
Test name
Test status
Simulation time	35826300 ps
CPU time	28.64 seconds
Started	Aug 10 07:37:16 PM PDT 24
Finished	Aug 10 07:37:45 PM PDT 24
Peak memory	274324 kb
Host	smart-789928cd-ceac-4b3c-b320-f5e104dc7ba4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850296573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_rw_evict.1850296573
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.510500614
Short name	T377
Test name
Test status
Simulation time	1817737300 ps
CPU time	75.79 seconds
Started	Aug 10 07:37:45 PM PDT 24
Finished	Aug 10 07:39:01 PM PDT 24
Peak memory	264332 kb
Host	smart-dd41a324-3006-4853-bd4e-ebaf843bb663
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510500614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.510500614
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.1138651237
Short name	T353
Test name
Test status
Simulation time	17407900 ps
CPU time	21.85 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:38:20 PM PDT 24
Peak memory	274244 kb
Host	smart-d716ab01-01fd-40ae-acd9-8ea721196959
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138651237 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.1138651237
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.681954223
Short name	T628
Test name
Test status
Simulation time	20941500 ps
CPU time	22.34 seconds
Started	Aug 10 07:38:28 PM PDT 24
Finished	Aug 10 07:38:51 PM PDT 24
Peak memory	274124 kb
Host	smart-db6be851-9adf-4d72-a6ac-f246c8b7f469
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681954223 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.681954223
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.191076642
Short name	T119
Test name
Test status
Simulation time	11324000 ps
CPU time	21.76 seconds
Started	Aug 10 07:38:39 PM PDT 24
Finished	Aug 10 07:39:01 PM PDT 24
Peak memory	274280 kb
Host	smart-32f55cdc-04e5-4d74-8c0b-a02e486ba44a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191076642 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.191076642
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.794337319
Short name	T357
Test name
Test status
Simulation time	10741700 ps
CPU time	21.95 seconds
Started	Aug 10 07:38:59 PM PDT 24
Finished	Aug 10 07:39:21 PM PDT 24
Peak memory	274260 kb
Host	smart-700a102b-8903-4691-b40f-e9f32cbb65cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794337319 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.794337319
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.4063382329
Short name	T752
Test name
Test status
Simulation time	42963100 ps
CPU time	113.44 seconds
Started	Aug 10 07:39:04 PM PDT 24
Finished	Aug 10 07:40:58 PM PDT 24
Peak memory	265732 kb
Host	smart-60108383-15b0-41f0-a2f5-d2669a133571
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063382329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o tp_reset.4063382329
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.2680949887
Short name	T355
Test name
Test status
Simulation time	38203300 ps
CPU time	21.73 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:40:01 PM PDT 24
Peak memory	274856 kb
Host	smart-24dc3633-95ce-4553-aacb-290cc4785e85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680949887 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.2680949887
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.3226352777
Short name	T37
Test name
Test status
Simulation time	792956600 ps
CPU time	126.78 seconds
Started	Aug 10 07:39:49 PM PDT 24
Finished	Aug 10 07:41:56 PM PDT 24
Peak memory	293800 kb
Host	smart-391ad468-cdc0-4a6d-a184-113a8a394eeb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226352777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_intr_rd.3226352777
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.636349075
Short name	T379
Test name
Test status
Simulation time	2559580200 ps
CPU time	65.88 seconds
Started	Aug 10 07:40:29 PM PDT 24
Finished	Aug 10 07:41:35 PM PDT 24
Peak memory	264240 kb
Host	smart-7aba3e8c-8529-4c35-8b03-9f5ec7ab9af7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636349075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.636349075
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.3449491796
Short name	T170
Test name
Test status
Simulation time	2252131100 ps
CPU time	75.17 seconds
Started	Aug 10 07:40:53 PM PDT 24
Finished	Aug 10 07:42:09 PM PDT 24
Peak memory	265684 kb
Host	smart-e4e43704-a1c7-456d-a439-22ca6d3c7302
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449491796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3449491796
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.3905332915
Short name	T199
Test name
Test status
Simulation time	117754700 ps
CPU time	29.53 seconds
Started	Aug 10 07:34:21 PM PDT 24
Finished	Aug 10 07:34:51 PM PDT 24
Peak memory	276236 kb
Host	smart-4bceaf66-e570-4e11-bf12-00d49f6d10a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905332915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.3905332915
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.2127732256
Short name	T196
Test name
Test status
Simulation time	3497662900 ps
CPU time	176.79 seconds
Started	Aug 10 07:35:36 PM PDT 24
Finished	Aug 10 07:38:33 PM PDT 24
Peak memory	283612 kb
Host	smart-27785b0d-9d38-48cd-b47e-5ac6cc6081e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2127732256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2127732256
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.791670049
Short name	T217
Test name
Test status
Simulation time	25144100 ps
CPU time	14.12 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:34:24 PM PDT 24
Peak memory	265688 kb
Host	smart-0bde809d-ab0b-430f-a236-302a1f450290
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=791670049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.791670049
Directory	/workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.38681438
Short name	T1240
Test name
Test status
Simulation time	183832900 ps
CPU time	16.61 seconds
Started	Aug 10 07:28:37 PM PDT 24
Finished	Aug 10 07:28:54 PM PDT 24
Peak memory	264312 kb
Host	smart-86dc27d6-3e6f-4e26-8a19-cd4601484be7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.38681438
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3065040383
Short name	T254
Test name
Test status
Simulation time	883929700 ps
CPU time	765.49 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:41:29 PM PDT 24
Peak memory	264288 kb
Host	smart-6c326569-23fa-466a-88ed-205180dfbf7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065040383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr l_tl_intg_err.3065040383
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.3424536276
Short name	T23
Test name
Test status
Simulation time	21504749200 ps
CPU time	2288.63 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 08:12:00 PM PDT 24
Peak memory	265676 kb
Host	smart-10d85c51-e893-4d78-b508-6cf69e6df0fb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3424536276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.3424536276
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.472531097
Short name	T738
Test name
Test status
Simulation time	1882609900 ps
CPU time	818.93 seconds
Started	Aug 10 07:33:52 PM PDT 24
Finished	Aug 10 07:47:31 PM PDT 24
Peak memory	273848 kb
Host	smart-96471f43-95e9-4e4c-a8ae-597694dc4507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472531097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.472531097
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.1625590535
Short name	T156
Test name
Test status
Simulation time	602769812600 ps
CPU time	2947.95 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 08:23:00 PM PDT 24
Peak memory	273916 kb
Host	smart-37476757-d623-4b66-9756-a87496e3a935
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625590535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.1625590535
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3972916320
Short name	T197
Test name
Test status
Simulation time	265193289100 ps
CPU time	2847.38 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 08:21:24 PM PDT 24
Peak memory	265684 kb
Host	smart-11f768c1-b774-490b-9043-80311b2334a5
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972916320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.flash_ctrl_host_ctrl_arb.3972916320
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1436234339
Short name	T165
Test name
Test status
Simulation time	875584600 ps
CPU time	22.63 seconds
Started	Aug 10 07:33:58 PM PDT 24
Finished	Aug 10 07:34:21 PM PDT 24
Peak memory	266092 kb
Host	smart-e4729da0-a07d-48c2-b467-a565f4024c62
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436234339 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1436234339
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.3922482110
Short name	T198
Test name
Test status
Simulation time	2483895800 ps
CPU time	170.75 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:36:42 PM PDT 24
Peak memory	282604 kb
Host	smart-9ffd8507-2bcc-4b20-99a4-6e24aa27f8dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3922482110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3922482110
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.2285293044
Short name	T185
Test name
Test status
Simulation time	256599301000 ps
CPU time	2714.55 seconds
Started	Aug 10 07:34:03 PM PDT 24
Finished	Aug 10 08:19:18 PM PDT 24
Peak memory	264552 kb
Host	smart-9ab8a04b-2f5d-49a0-afad-a3b787b70c76
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285293044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_host_ctrl_arb.2285293044
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.4026159399
Short name	T64
Test name
Test status
Simulation time	17667127800 ps
CPU time	683.23 seconds
Started	Aug 10 07:37:16 PM PDT 24
Finished	Aug 10 07:48:39 PM PDT 24
Peak memory	315224 kb
Host	smart-71a84000-a719-4915-84c3-76a5d03678fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026159399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.4026159399
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2074346099
Short name	T103
Test name
Test status
Simulation time	362693542500 ps
CPU time	2423.2 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 08:14:42 PM PDT 24
Peak memory	264512 kb
Host	smart-83748346-a166-4e9d-b0d3-1e46a767c27f
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074346099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.2074346099
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2414800215
Short name	T186
Test name
Test status
Simulation time	651747339100 ps
CPU time	1990.44 seconds
Started	Aug 10 07:34:58 PM PDT 24
Finished	Aug 10 08:08:08 PM PDT 24
Peak memory	264736 kb
Host	smart-6ed853cc-7a3e-4b3a-bd01-ef85003df576
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414800215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.2414800215
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1618560006
Short name	T70
Test name
Test status
Simulation time	423254200 ps
CPU time	31.29 seconds
Started	Aug 10 07:28:12 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	261872 kb
Host	smart-b73c5caf-da76-4977-bb37-14ad1088df5b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618560006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.1618560006
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.714809158
Short name	T1203
Test name
Test status
Simulation time	1337236300 ps
CPU time	40.35 seconds
Started	Aug 10 07:28:13 PM PDT 24
Finished	Aug 10 07:28:53 PM PDT 24
Peak memory	261860 kb
Host	smart-9d4e75a9-6507-4587-b071-03280d10d8b9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714809158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.flash_ctrl_csr_bit_bash.714809158
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3247532812
Short name	T1141
Test name
Test status
Simulation time	31115500 ps
CPU time	30.17 seconds
Started	Aug 10 07:28:13 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	261784 kb
Host	smart-0ed45c73-6d66-44d1-aa89-a5a49a130386
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247532812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.3247532812
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2096801270
Short name	T221
Test name
Test status
Simulation time	743614900 ps
CPU time	20.03 seconds
Started	Aug 10 07:28:10 PM PDT 24
Finished	Aug 10 07:28:30 PM PDT 24
Peak memory	272016 kb
Host	smart-db421714-8fc4-4786-84e7-ee132b1f8bc2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096801270 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.2096801270
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1710418650
Short name	T1148
Test name
Test status
Simulation time	35301000 ps
CPU time	14.67 seconds
Started	Aug 10 07:28:14 PM PDT 24
Finished	Aug 10 07:28:28 PM PDT 24
Peak memory	262296 kb
Host	smart-8343384b-ae2d-4bb4-9323-c0ec5d6d8cd7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710418650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1710418650
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2599249599
Short name	T228
Test name
Test status
Simulation time	30370900 ps
CPU time	13.51 seconds
Started	Aug 10 07:28:10 PM PDT 24
Finished	Aug 10 07:28:23 PM PDT 24
Peak memory	262776 kb
Host	smart-e73032b2-751f-4a5f-b7a7-4e9d71a08e7d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599249599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.2599249599
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4138160940
Short name	T1165
Test name
Test status
Simulation time	56387000 ps
CPU time	13.52 seconds
Started	Aug 10 07:28:11 PM PDT 24
Finished	Aug 10 07:28:24 PM PDT 24
Peak memory	261872 kb
Host	smart-54234e39-3979-4d9d-9f74-0c85a10aedb9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138160940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.4138160940
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2756798403
Short name	T1190
Test name
Test status
Simulation time	91074600 ps
CPU time	16.17 seconds
Started	Aug 10 07:28:10 PM PDT 24
Finished	Aug 10 07:28:26 PM PDT 24
Peak memory	253648 kb
Host	smart-dc036c91-b1de-4939-8b08-6bffbfe936aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756798403 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2756798403
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.300675849
Short name	T1210
Test name
Test status
Simulation time	22241600 ps
CPU time	15.64 seconds
Started	Aug 10 07:28:14 PM PDT 24
Finished	Aug 10 07:28:29 PM PDT 24
Peak memory	253684 kb
Host	smart-15c868e7-9633-4f81-b6db-94490633fe8a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300675849 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.300675849
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3111235187
Short name	T249
Test name
Test status
Simulation time	190747400 ps
CPU time	20.32 seconds
Started	Aug 10 07:28:11 PM PDT 24
Finished	Aug 10 07:28:31 PM PDT 24
Peak memory	264428 kb
Host	smart-c8b10d06-6681-44c3-81b7-1bcd170ba844
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111235187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3 111235187
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3399662407
Short name	T1217
Test name
Test status
Simulation time	657882000 ps
CPU time	462.1 seconds
Started	Aug 10 07:28:14 PM PDT 24
Finished	Aug 10 07:35:56 PM PDT 24
Peak memory	264336 kb
Host	smart-cba472e1-26b3-4dae-ad6d-c8a6538bc987
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399662407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _tl_intg_err.3399662407
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.888888898
Short name	T1205
Test name
Test status
Simulation time	2881842800 ps
CPU time	59.72 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:29:16 PM PDT 24
Peak memory	261884 kb
Host	smart-1135d069-12a1-4568-aa2a-ff84e4200548
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888888898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.flash_ctrl_csr_aliasing.888888898
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1066393105
Short name	T1128
Test name
Test status
Simulation time	644134400 ps
CPU time	37.35 seconds
Started	Aug 10 07:28:15 PM PDT 24
Finished	Aug 10 07:28:53 PM PDT 24
Peak memory	261924 kb
Host	smart-ebcec9ee-1fa1-47c3-ae64-5c712c835968
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066393105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.1066393105
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2736692587
Short name	T393
Test name
Test status
Simulation time	37801200 ps
CPU time	30.56 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:47 PM PDT 24
Peak memory	261816 kb
Host	smart-bc1b8faf-620f-449f-9b97-e739e374befe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736692587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_hw_reset.2736692587
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3458514061
Short name	T1200
Test name
Test status
Simulation time	56188700 ps
CPU time	16.95 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:33 PM PDT 24
Peak memory	271060 kb
Host	smart-d072d5f1-a8b1-47c6-ad61-d8270d3a4f34
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458514061 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3458514061
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2899564453
Short name	T1169
Test name
Test status
Simulation time	432706000 ps
CPU time	15.03 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:31 PM PDT 24
Peak memory	264224 kb
Host	smart-f635508a-6d43-4349-895b-7c2ef0d5353e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899564453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.2899564453
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2377424782
Short name	T1244
Test name
Test status
Simulation time	80712600 ps
CPU time	13.6 seconds
Started	Aug 10 07:28:14 PM PDT 24
Finished	Aug 10 07:28:28 PM PDT 24
Peak memory	261860 kb
Host	smart-f8ea8c66-1a6b-4d3a-b8ba-727cc46a2858
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377424782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2 377424782
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2324676041
Short name	T229
Test name
Test status
Simulation time	18208100 ps
CPU time	13.55 seconds
Started	Aug 10 07:28:11 PM PDT 24
Finished	Aug 10 07:28:24 PM PDT 24
Peak memory	263424 kb
Host	smart-6bc79b76-51b4-4686-adfb-5efd2c90067e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324676041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.2324676041
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1565757410
Short name	T1181
Test name
Test status
Simulation time	16753100 ps
CPU time	13.57 seconds
Started	Aug 10 07:28:11 PM PDT 24
Finished	Aug 10 07:28:24 PM PDT 24
Peak memory	261700 kb
Host	smart-f42f7eab-30f5-4464-a5bf-6dae2e1033e8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565757410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.1565757410
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2086496587
Short name	T1248
Test name
Test status
Simulation time	542577400 ps
CPU time	16.46 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:34 PM PDT 24
Peak memory	263436 kb
Host	smart-03d58819-1d9c-4622-b36a-db86cc3f9b4b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086496587 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2086496587
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2019945814
Short name	T1239
Test name
Test status
Simulation time	38433500 ps
CPU time	15.88 seconds
Started	Aug 10 07:28:11 PM PDT 24
Finished	Aug 10 07:28:27 PM PDT 24
Peak memory	253744 kb
Host	smart-e2a94335-06cc-4956-adf8-f8880671f312
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019945814 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2019945814
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3616229023
Short name	T1144
Test name
Test status
Simulation time	25737300 ps
CPU time	15.41 seconds
Started	Aug 10 07:28:09 PM PDT 24
Finished	Aug 10 07:28:25 PM PDT 24
Peak memory	253516 kb
Host	smart-b1ad0bf8-d9c0-48a1-8f59-4a2cdec25e6f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616229023 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3616229023
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2912091526
Short name	T224
Test name
Test status
Simulation time	306483000 ps
CPU time	19.81 seconds
Started	Aug 10 07:28:12 PM PDT 24
Finished	Aug 10 07:28:32 PM PDT 24
Peak memory	264408 kb
Host	smart-f8afea64-4f51-484b-b6e7-82f2e8d0e30a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912091526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2 912091526
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1399830158
Short name	T346
Test name
Test status
Simulation time	1773001200 ps
CPU time	388.78 seconds
Started	Aug 10 07:28:13 PM PDT 24
Finished	Aug 10 07:34:42 PM PDT 24
Peak memory	264332 kb
Host	smart-e024b7b7-0dc8-47fa-a626-e9dd137a1906
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399830158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _tl_intg_err.1399830158
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.545600817
Short name	T1135
Test name
Test status
Simulation time	245748900 ps
CPU time	17.43 seconds
Started	Aug 10 07:28:37 PM PDT 24
Finished	Aug 10 07:28:54 PM PDT 24
Peak memory	264432 kb
Host	smart-f774dee5-1432-44d7-9f8c-7b62f6e1b456
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545600817 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.545600817
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1268429749
Short name	T1259
Test name
Test status
Simulation time	21368400 ps
CPU time	16.4 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	264256 kb
Host	smart-c13a4370-2d52-4444-8e85-f3ed10cc66c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268429749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.1268429749
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2833609055
Short name	T1224
Test name
Test status
Simulation time	16658700 ps
CPU time	13.56 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	261680 kb
Host	smart-dd3825d5-b307-4d32-b0c2-08dbc7cdeb3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833609055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 2833609055
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1719750867
Short name	T232
Test name
Test status
Simulation time	348534800 ps
CPU time	17.84 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:28:54 PM PDT 24
Peak memory	263224 kb
Host	smart-44ca79ac-11dd-4e20-afd3-11761dbf6032
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719750867 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1719750867
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2176917866
Short name	T1246
Test name
Test status
Simulation time	23415200 ps
CPU time	13.16 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:28:49 PM PDT 24
Peak memory	253704 kb
Host	smart-cf3cd62c-7088-4940-a061-24ea8115a711
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176917866 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2176917866
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.736880902
Short name	T1143
Test name
Test status
Simulation time	29329300 ps
CPU time	15.54 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	253732 kb
Host	smart-37a1ed5a-ad9e-4fe2-b0a9-040e26c7fb74
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736880902 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.736880902
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1088518696
Short name	T235
Test name
Test status
Simulation time	73702700 ps
CPU time	16.98 seconds
Started	Aug 10 07:28:38 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	264216 kb
Host	smart-896137da-8d05-4cad-b9b2-ae84e9e0daea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088518696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.1088518696
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2780778537
Short name	T1147
Test name
Test status
Simulation time	17197200 ps
CPU time	13.37 seconds
Started	Aug 10 07:28:37 PM PDT 24
Finished	Aug 10 07:28:51 PM PDT 24
Peak memory	261876 kb
Host	smart-07f1bd78-23e5-4ad7-882f-9d65a4dd547f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780778537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test. 2780778537
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3983829986
Short name	T1158
Test name
Test status
Simulation time	38151800 ps
CPU time	17.52 seconds
Started	Aug 10 07:28:38 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	262096 kb
Host	smart-78e6a18e-60ca-4e11-8db2-38be0b5d97f3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983829986 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3983829986
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4165037613
Short name	T1167
Test name
Test status
Simulation time	14923900 ps
CPU time	15.87 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	253644 kb
Host	smart-67fb45cf-c629-482f-a2f7-429d2ac5b776
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165037613 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.4165037613
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4200828003
Short name	T1260
Test name
Test status
Simulation time	25078500 ps
CPU time	13.41 seconds
Started	Aug 10 07:28:38 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	253712 kb
Host	smart-7639dfb0-0d70-476a-9678-955341accecc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200828003 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.4200828003
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3226013250
Short name	T1247
Test name
Test status
Simulation time	76500900 ps
CPU time	16.94 seconds
Started	Aug 10 07:28:38 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	264384 kb
Host	smart-ca5fb192-e414-4ed2-aca8-0c42c85ba347
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226013250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors. 3226013250
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2204639530
Short name	T348
Test name
Test status
Simulation time	671498800 ps
CPU time	897.27 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:43:36 PM PDT 24
Peak memory	264304 kb
Host	smart-98ee8208-def5-47d0-9c9c-b52a7f44194f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204639530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.2204639530
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2209841667
Short name	T1230
Test name
Test status
Simulation time	60770500 ps
CPU time	17.06 seconds
Started	Aug 10 07:28:44 PM PDT 24
Finished	Aug 10 07:29:01 PM PDT 24
Peak memory	272544 kb
Host	smart-ab128881-b6e0-4eb7-a0f4-395ffa78403d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209841667 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2209841667
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3439059377
Short name	T1140
Test name
Test status
Simulation time	113431000 ps
CPU time	17.61 seconds
Started	Aug 10 07:28:38 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	264216 kb
Host	smart-d2a50851-0cdf-4ba0-8057-a1823818fda2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439059377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.3439059377
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3905321298
Short name	T1215
Test name
Test status
Simulation time	18656500 ps
CPU time	13.48 seconds
Started	Aug 10 07:28:38 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	261812 kb
Host	smart-2ff84d89-bb0a-4bfc-afce-e5d561b4b763
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905321298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 3905321298
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1569954087
Short name	T1222
Test name
Test status
Simulation time	824230300 ps
CPU time	35.98 seconds
Started	Aug 10 07:28:47 PM PDT 24
Finished	Aug 10 07:29:23 PM PDT 24
Peak memory	261876 kb
Host	smart-ffd1a816-0b74-43e0-9ae1-7531e952197c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569954087 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1569954087
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3711164493
Short name	T1191
Test name
Test status
Simulation time	45029100 ps
CPU time	13.57 seconds
Started	Aug 10 07:28:37 PM PDT 24
Finished	Aug 10 07:28:51 PM PDT 24
Peak memory	253692 kb
Host	smart-3af7b0ab-ccf6-476d-857a-fc9df8f8e4fc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711164493 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3711164493
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1243965960
Short name	T1172
Test name
Test status
Simulation time	42393200 ps
CPU time	15.62 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	253732 kb
Host	smart-ea76babe-0d55-4f94-a718-057273538d5d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243965960 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1243965960
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.755523835
Short name	T242
Test name
Test status
Simulation time	148197300 ps
CPU time	16.81 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:56 PM PDT 24
Peak memory	264372 kb
Host	smart-a5c4c598-0132-4cca-9086-0fa9fad8f853
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755523835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.755523835
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2509775154
Short name	T209
Test name
Test status
Simulation time	1302593400 ps
CPU time	391.2 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:35:10 PM PDT 24
Peak memory	264328 kb
Host	smart-6b4bb00d-7262-481f-99c4-61b7c3d6ab3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509775154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.2509775154
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.622190483
Short name	T1252
Test name
Test status
Simulation time	435271700 ps
CPU time	16.28 seconds
Started	Aug 10 07:28:42 PM PDT 24
Finished	Aug 10 07:28:58 PM PDT 24
Peak memory	272508 kb
Host	smart-fe90e745-d1a4-4e19-bdf6-64da2793af83
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622190483 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.622190483
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1125631987
Short name	T1193
Test name
Test status
Simulation time	57317400 ps
CPU time	17.15 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:29:01 PM PDT 24
Peak memory	264256 kb
Host	smart-8ba086a8-5574-433b-801f-02d0934323f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125631987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.1125631987
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1666920534
Short name	T1183
Test name
Test status
Simulation time	19678800 ps
CPU time	13.39 seconds
Started	Aug 10 07:28:42 PM PDT 24
Finished	Aug 10 07:28:56 PM PDT 24
Peak memory	261716 kb
Host	smart-9b126102-8f2f-4bc4-b5e5-4c5e3a3dae5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666920534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 1666920534
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.666782278
Short name	T276
Test name
Test status
Simulation time	865951900 ps
CPU time	19.03 seconds
Started	Aug 10 07:28:44 PM PDT 24
Finished	Aug 10 07:29:03 PM PDT 24
Peak memory	261896 kb
Host	smart-e95335c5-7f99-43ea-9fe1-2187a8c1dcc9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666782278 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.666782278
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4162936564
Short name	T1121
Test name
Test status
Simulation time	33729000 ps
CPU time	13.37 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:28:57 PM PDT 24
Peak memory	253716 kb
Host	smart-3b69e1e0-d72d-48a2-a29f-f8b284b3e174
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162936564 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.4162936564
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2355148366
Short name	T1192
Test name
Test status
Simulation time	14614800 ps
CPU time	13.14 seconds
Started	Aug 10 07:28:42 PM PDT 24
Finished	Aug 10 07:28:56 PM PDT 24
Peak memory	253660 kb
Host	smart-ccca4ac6-e674-41e9-b025-6fa34c4969d4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355148366 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.2355148366
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3019872399
Short name	T1220
Test name
Test status
Simulation time	97854000 ps
CPU time	18.93 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:29:02 PM PDT 24
Peak memory	272152 kb
Host	smart-3bfefc9d-6b72-4820-a9dc-dba0c259b9bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019872399 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3019872399
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1678555722
Short name	T234
Test name
Test status
Simulation time	34630400 ps
CPU time	16.4 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:28:59 PM PDT 24
Peak memory	261816 kb
Host	smart-81a56e1d-0129-496b-8143-bfb5c1c18556
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678555722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.1678555722
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2225492562
Short name	T244
Test name
Test status
Simulation time	14745600 ps
CPU time	13.56 seconds
Started	Aug 10 07:28:45 PM PDT 24
Finished	Aug 10 07:28:58 PM PDT 24
Peak memory	261860 kb
Host	smart-5fc5f6c5-4baf-439a-a7a8-a2959e46afb3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225492562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test. 2225492562
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.94847617
Short name	T283
Test name
Test status
Simulation time	348288200 ps
CPU time	17.93 seconds
Started	Aug 10 07:28:42 PM PDT 24
Finished	Aug 10 07:29:00 PM PDT 24
Peak memory	264376 kb
Host	smart-03d71823-c49a-4db7-9acc-41e51392b960
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94847617 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.94847617
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2591697424
Short name	T1186
Test name
Test status
Simulation time	20003900 ps
CPU time	15.28 seconds
Started	Aug 10 07:28:45 PM PDT 24
Finished	Aug 10 07:29:01 PM PDT 24
Peak memory	253584 kb
Host	smart-6c4a3b24-be24-42e0-b05d-caa802ab8fa2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591697424 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2591697424
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.90122602
Short name	T1131
Test name
Test status
Simulation time	17299600 ps
CPU time	16.23 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:28:59 PM PDT 24
Peak memory	253884 kb
Host	smart-d87cbe4c-d621-4fc7-8a46-949fc0937dac
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90122602 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.90122602
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.323835308
Short name	T349
Test name
Test status
Simulation time	671744000 ps
CPU time	389.44 seconds
Started	Aug 10 07:28:44 PM PDT 24
Finished	Aug 10 07:35:14 PM PDT 24
Peak memory	264308 kb
Host	smart-b624e8e3-4102-4683-b5d0-e858e0af384d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323835308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl _tl_intg_err.323835308
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1612944960
Short name	T255
Test name
Test status
Simulation time	88748500 ps
CPU time	20.52 seconds
Started	Aug 10 07:28:44 PM PDT 24
Finished	Aug 10 07:29:05 PM PDT 24
Peak memory	272576 kb
Host	smart-f24cfd38-22d7-44d7-8dbf-855c43305554
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612944960 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1612944960
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.988033064
Short name	T1136
Test name
Test status
Simulation time	62506800 ps
CPU time	16.7 seconds
Started	Aug 10 07:28:44 PM PDT 24
Finished	Aug 10 07:29:01 PM PDT 24
Peak memory	264224 kb
Host	smart-b05467e4-2e30-478c-979f-f91e174fe7b8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988033064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.flash_ctrl_csr_rw.988033064
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.201153457
Short name	T1153
Test name
Test status
Simulation time	16808100 ps
CPU time	13.29 seconds
Started	Aug 10 07:28:45 PM PDT 24
Finished	Aug 10 07:28:59 PM PDT 24
Peak memory	261832 kb
Host	smart-ee932b53-c302-4142-b8de-3846864495e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201153457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.201153457
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2328066930
Short name	T282
Test name
Test status
Simulation time	198479100 ps
CPU time	21.46 seconds
Started	Aug 10 07:28:46 PM PDT 24
Finished	Aug 10 07:29:07 PM PDT 24
Peak memory	261892 kb
Host	smart-cc65a007-56b7-414e-b7f2-6dbddd3dbeb2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328066930 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2328066930
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2340404964
Short name	T1238
Test name
Test status
Simulation time	13959500 ps
CPU time	13.6 seconds
Started	Aug 10 07:28:46 PM PDT 24
Finished	Aug 10 07:28:59 PM PDT 24
Peak memory	253616 kb
Host	smart-552ae061-dc65-4bd6-bd4f-00ad8b260db0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340404964 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2340404964
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1064413990
Short name	T1225
Test name
Test status
Simulation time	11821000 ps
CPU time	13.36 seconds
Started	Aug 10 07:28:47 PM PDT 24
Finished	Aug 10 07:29:00 PM PDT 24
Peak memory	253348 kb
Host	smart-0bdb271b-e773-4a69-8462-a1d0639d3af3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064413990 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1064413990
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2829515605
Short name	T250
Test name
Test status
Simulation time	45748200 ps
CPU time	16.69 seconds
Started	Aug 10 07:28:43 PM PDT 24
Finished	Aug 10 07:29:00 PM PDT 24
Peak memory	264428 kb
Host	smart-603f361f-612c-4e5b-a6b9-5f5a78f7314d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829515605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors. 2829515605
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2259436371
Short name	T344
Test name
Test status
Simulation time	661788600 ps
CPU time	459.92 seconds
Started	Aug 10 07:28:46 PM PDT 24
Finished	Aug 10 07:36:26 PM PDT 24
Peak memory	264276 kb
Host	smart-c421e51f-700f-4430-b633-4376df86cc54
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259436371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr l_tl_intg_err.2259436371
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1646651314
Short name	T1175
Test name
Test status
Simulation time	89191800 ps
CPU time	17.78 seconds
Started	Aug 10 07:28:49 PM PDT 24
Finished	Aug 10 07:29:07 PM PDT 24
Peak memory	277956 kb
Host	smart-2e03a300-380f-41e1-9d84-94cb701bc0f9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646651314 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1646651314
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3040109309
Short name	T1219
Test name
Test status
Simulation time	304936100 ps
CPU time	17.6 seconds
Started	Aug 10 07:28:49 PM PDT 24
Finished	Aug 10 07:29:06 PM PDT 24
Peak memory	262688 kb
Host	smart-36692260-cc54-4ef2-b1b2-9726d809575e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040109309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.3040109309
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3514712012
Short name	T1201
Test name
Test status
Simulation time	26852000 ps
CPU time	13.36 seconds
Started	Aug 10 07:28:50 PM PDT 24
Finished	Aug 10 07:29:03 PM PDT 24
Peak memory	261736 kb
Host	smart-83f56a58-e769-4d55-abdf-f2f82488c8c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514712012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 3514712012
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.832594525
Short name	T1146
Test name
Test status
Simulation time	65067100 ps
CPU time	17.12 seconds
Started	Aug 10 07:28:52 PM PDT 24
Finished	Aug 10 07:29:09 PM PDT 24
Peak memory	263204 kb
Host	smart-e741e38a-dfe3-4b7f-8b11-f09920ccc71a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832594525 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.832594525
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1287056689
Short name	T1189
Test name
Test status
Simulation time	87810900 ps
CPU time	15.93 seconds
Started	Aug 10 07:28:49 PM PDT 24
Finished	Aug 10 07:29:05 PM PDT 24
Peak memory	253680 kb
Host	smart-c4a1ef46-e705-40ee-86c0-a55d7d915f03
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287056689 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1287056689
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3916735147
Short name	T1122
Test name
Test status
Simulation time	11556700 ps
CPU time	13.15 seconds
Started	Aug 10 07:28:49 PM PDT 24
Finished	Aug 10 07:29:02 PM PDT 24
Peak memory	253704 kb
Host	smart-74f902a4-8c9c-458a-a82e-9c634021453a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916735147 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.3916735147
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1598911301
Short name	T122
Test name
Test status
Simulation time	123035100 ps
CPU time	15.91 seconds
Started	Aug 10 07:28:51 PM PDT 24
Finished	Aug 10 07:29:07 PM PDT 24
Peak memory	263648 kb
Host	smart-04b3fe60-e193-4aa5-a06b-d189abd0f5da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598911301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors. 1598911301
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3590712289
Short name	T1202
Test name
Test status
Simulation time	93062300 ps
CPU time	17.16 seconds
Started	Aug 10 07:28:49 PM PDT 24
Finished	Aug 10 07:29:06 PM PDT 24
Peak memory	263112 kb
Host	smart-5feeb95e-2e61-43c9-a7fe-e500cdcb30a5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590712289 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3590712289
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.38521827
Short name	T1160
Test name
Test status
Simulation time	21843500 ps
CPU time	14.03 seconds
Started	Aug 10 07:28:50 PM PDT 24
Finished	Aug 10 07:29:04 PM PDT 24
Peak memory	261732 kb
Host	smart-f6c32395-89fb-4bb1-a2ba-97056e83da2f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38521827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.flash_ctrl_csr_rw.38521827
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.829248673
Short name	T1255
Test name
Test status
Simulation time	15068900 ps
CPU time	13.51 seconds
Started	Aug 10 07:28:52 PM PDT 24
Finished	Aug 10 07:29:05 PM PDT 24
Peak memory	261832 kb
Host	smart-5c7350e9-5171-40b4-9010-34e60f7d6608
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829248673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.829248673
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1738264717
Short name	T280
Test name
Test status
Simulation time	415827400 ps
CPU time	18.68 seconds
Started	Aug 10 07:28:52 PM PDT 24
Finished	Aug 10 07:29:11 PM PDT 24
Peak memory	263200 kb
Host	smart-20a6261a-39bf-4f2b-aba7-bf41671190af
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738264717 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1738264717
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2931931658
Short name	T1120
Test name
Test status
Simulation time	13950700 ps
CPU time	15.73 seconds
Started	Aug 10 07:28:49 PM PDT 24
Finished	Aug 10 07:29:05 PM PDT 24
Peak memory	253736 kb
Host	smart-17f7a387-06af-4eb6-baba-6d478b873376
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931931658 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2931931658
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2551612175
Short name	T1152
Test name
Test status
Simulation time	39270700 ps
CPU time	15.87 seconds
Started	Aug 10 07:28:51 PM PDT 24
Finished	Aug 10 07:29:07 PM PDT 24
Peak memory	253648 kb
Host	smart-19da414b-d351-42e1-bb71-cdb58db48577
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551612175 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2551612175
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1173283928
Short name	T243
Test name
Test status
Simulation time	226508400 ps
CPU time	19.13 seconds
Started	Aug 10 07:28:52 PM PDT 24
Finished	Aug 10 07:29:11 PM PDT 24
Peak memory	264360 kb
Host	smart-b7fbdbe1-382c-4ee7-b220-c304763546e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173283928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 1173283928
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1796152852
Short name	T1145
Test name
Test status
Simulation time	170613600 ps
CPU time	19.13 seconds
Started	Aug 10 07:29:00 PM PDT 24
Finished	Aug 10 07:29:19 PM PDT 24
Peak memory	272516 kb
Host	smart-704aecd7-dbac-4f35-9e6b-246b263f3eab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796152852 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1796152852
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1391163730
Short name	T1149
Test name
Test status
Simulation time	311094400 ps
CPU time	16.53 seconds
Started	Aug 10 07:29:02 PM PDT 24
Finished	Aug 10 07:29:18 PM PDT 24
Peak memory	261736 kb
Host	smart-002cc956-73c7-44f3-af7b-42af598875d2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391163730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.1391163730
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2257029834
Short name	T246
Test name
Test status
Simulation time	15297300 ps
CPU time	13.47 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261740 kb
Host	smart-8f8305f4-02f2-405d-b8ad-52f32c94e09a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257029834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 2257029834
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.167850985
Short name	T1180
Test name
Test status
Simulation time	94891000 ps
CPU time	20.07 seconds
Started	Aug 10 07:28:59 PM PDT 24
Finished	Aug 10 07:29:20 PM PDT 24
Peak memory	261860 kb
Host	smart-cf8bff49-6801-408d-b074-ef3dfcb12ae7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167850985 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.167850985
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2656967125
Short name	T1156
Test name
Test status
Simulation time	19164900 ps
CPU time	15.51 seconds
Started	Aug 10 07:28:55 PM PDT 24
Finished	Aug 10 07:29:10 PM PDT 24
Peak memory	253648 kb
Host	smart-f6adf20e-322a-4ed6-b707-b71e8095bdae
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656967125 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2656967125
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1606145605
Short name	T1206
Test name
Test status
Simulation time	25465700 ps
CPU time	16.31 seconds
Started	Aug 10 07:28:55 PM PDT 24
Finished	Aug 10 07:29:12 PM PDT 24
Peak memory	253552 kb
Host	smart-b4e72dcc-bafd-4e03-9be8-16dee53e15e5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606145605 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1606145605
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1295920908
Short name	T284
Test name
Test status
Simulation time	61012400 ps
CPU time	17.72 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:18 PM PDT 24
Peak memory	263588 kb
Host	smart-eb560ec6-887d-4589-b81c-e7226c7953cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295920908 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1295920908
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1912399390
Short name	T1216
Test name
Test status
Simulation time	43343800 ps
CPU time	14.2 seconds
Started	Aug 10 07:29:02 PM PDT 24
Finished	Aug 10 07:29:16 PM PDT 24
Peak memory	261736 kb
Host	smart-ba69deb5-d445-47bc-9c4a-0cb6b1691476
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912399390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.1912399390
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1229421245
Short name	T1208
Test name
Test status
Simulation time	16303000 ps
CPU time	13.94 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261736 kb
Host	smart-5f4c57e9-7030-47a1-a0ce-f158cf470e9d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229421245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test. 1229421245
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.219395875
Short name	T236
Test name
Test status
Simulation time	99058500 ps
CPU time	18.07 seconds
Started	Aug 10 07:29:04 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261924 kb
Host	smart-8bf7beca-ecc4-4cd6-8a11-19a448d4b238
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219395875 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.219395875
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3392985209
Short name	T1126
Test name
Test status
Simulation time	23333400 ps
CPU time	15.65 seconds
Started	Aug 10 07:28:54 PM PDT 24
Finished	Aug 10 07:29:10 PM PDT 24
Peak memory	253720 kb
Host	smart-f6799f75-6b54-4a60-b19c-3c6603a3e081
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392985209 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3392985209
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.41845581
Short name	T1117
Test name
Test status
Simulation time	92540500 ps
CPU time	16.02 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:17 PM PDT 24
Peak memory	253612 kb
Host	smart-8b785071-c771-4b8e-9b8b-8c48e434a384
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845581 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.41845581
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1464216253
Short name	T1241
Test name
Test status
Simulation time	534357200 ps
CPU time	19.32 seconds
Started	Aug 10 07:28:55 PM PDT 24
Finished	Aug 10 07:29:14 PM PDT 24
Peak memory	264420 kb
Host	smart-b90fc9b9-92da-4317-a4c6-6c83e1f950c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464216253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 1464216253
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1191468366
Short name	T342
Test name
Test status
Simulation time	1413994200 ps
CPU time	454.14 seconds
Started	Aug 10 07:28:54 PM PDT 24
Finished	Aug 10 07:36:28 PM PDT 24
Peak memory	264336 kb
Host	smart-2d6641ba-4807-4300-a198-85668f7300bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191468366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.1191468366
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.17515442
Short name	T1150
Test name
Test status
Simulation time	1791111300 ps
CPU time	52.84 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:29:09 PM PDT 24
Peak memory	261820 kb
Host	smart-23001e67-9dc1-4255-8837-d0f69dcd7c3d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.17515442
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2117236968
Short name	T1142
Test name
Test status
Simulation time	2484023800 ps
CPU time	45.43 seconds
Started	Aug 10 07:28:18 PM PDT 24
Finished	Aug 10 07:29:04 PM PDT 24
Peak memory	261864 kb
Host	smart-b4910867-2f1f-46ad-9643-f12ee66da2a6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117236968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_bit_bash.2117236968
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2883719036
Short name	T281
Test name
Test status
Simulation time	63661800 ps
CPU time	30.8 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:47 PM PDT 24
Peak memory	261824 kb
Host	smart-3e812795-876f-4c73-aaa1-0ebb71238bea
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883719036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.2883719036
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.32906906
Short name	T251
Test name
Test status
Simulation time	97345700 ps
CPU time	18.07 seconds
Started	Aug 10 07:28:19 PM PDT 24
Finished	Aug 10 07:28:37 PM PDT 24
Peak memory	279128 kb
Host	smart-3fcaf015-7e7e-4a3c-b54e-09b22fbf7a7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.32906906
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1377383917
Short name	T1137
Test name
Test status
Simulation time	117344400 ps
CPU time	14.3 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:31 PM PDT 24
Peak memory	261740 kb
Host	smart-f5e9a5c4-f1da-42d1-8b6e-627f2bea7d67
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377383917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.1377383917
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2872059199
Short name	T1170
Test name
Test status
Simulation time	17648700 ps
CPU time	13.6 seconds
Started	Aug 10 07:28:15 PM PDT 24
Finished	Aug 10 07:28:29 PM PDT 24
Peak memory	261768 kb
Host	smart-e0effa8b-1ff9-47ab-82e4-e35f6a343079
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872059199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2 872059199
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2149135584
Short name	T1154
Test name
Test status
Simulation time	30602600 ps
CPU time	13.43 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:29 PM PDT 24
Peak memory	261868 kb
Host	smart-470a1a99-495e-471f-97a1-7f358aa7ae4f
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149135584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me m_walk.2149135584
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1341619583
Short name	T233
Test name
Test status
Simulation time	179832800 ps
CPU time	17.58 seconds
Started	Aug 10 07:28:15 PM PDT 24
Finished	Aug 10 07:28:33 PM PDT 24
Peak memory	263704 kb
Host	smart-6215cbbc-2f3a-4db7-82eb-491b709f76f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341619583 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1341619583
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1652615948
Short name	T1253
Test name
Test status
Simulation time	29670800 ps
CPU time	15.78 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:32 PM PDT 24
Peak memory	253680 kb
Host	smart-774909a7-a09c-418d-879f-692192e6aafa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652615948 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.1652615948
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2273851362
Short name	T1162
Test name
Test status
Simulation time	22900500 ps
CPU time	16.03 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:33 PM PDT 24
Peak memory	253620 kb
Host	smart-ce3c9904-30e6-4e35-9544-4f7bec9f1d03
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273851362 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2273851362
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3969905721
Short name	T1243
Test name
Test status
Simulation time	34717700 ps
CPU time	15.93 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:32 PM PDT 24
Peak memory	263584 kb
Host	smart-fdcdd217-eb67-4746-a097-bc427a8e236f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969905721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3 969905721
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4040118059
Short name	T1159
Test name
Test status
Simulation time	25987200 ps
CPU time	13.62 seconds
Started	Aug 10 07:29:07 PM PDT 24
Finished	Aug 10 07:29:21 PM PDT 24
Peak memory	261836 kb
Host	smart-635bbe8f-501c-47f8-98c3-94ffd06329f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040118059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test. 4040118059
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.616515384
Short name	T1138
Test name
Test status
Simulation time	16435800 ps
CPU time	13.48 seconds
Started	Aug 10 07:28:59 PM PDT 24
Finished	Aug 10 07:29:13 PM PDT 24
Peak memory	261724 kb
Host	smart-f897b128-45cf-4a9b-97d0-60a858d0f35e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616515384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.616515384
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1791006802
Short name	T1226
Test name
Test status
Simulation time	14739000 ps
CPU time	13.56 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261784 kb
Host	smart-9798cbb5-fdac-4c19-a71d-14871562acf0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791006802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 1791006802
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3196012060
Short name	T1195
Test name
Test status
Simulation time	57074700 ps
CPU time	13.7 seconds
Started	Aug 10 07:29:02 PM PDT 24
Finished	Aug 10 07:29:16 PM PDT 24
Peak memory	261748 kb
Host	smart-77e35900-50ea-442d-abc8-d07ca3d5ffce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196012060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test. 3196012060
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1349195144
Short name	T1235
Test name
Test status
Simulation time	18002600 ps
CPU time	13.45 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261776 kb
Host	smart-d06d8cca-4158-46ce-b7ca-729198466145
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349195144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test. 1349195144
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1853916845
Short name	T1127
Test name
Test status
Simulation time	29188400 ps
CPU time	13.83 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261812 kb
Host	smart-6cddc3b5-cf67-41de-af00-67c495cdf334
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853916845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test. 1853916845
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2586529495
Short name	T1258
Test name
Test status
Simulation time	15187100 ps
CPU time	13.4 seconds
Started	Aug 10 07:29:02 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261820 kb
Host	smart-055da177-8de3-485f-a053-be8b7b376951
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586529495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test. 2586529495
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1696163965
Short name	T1164
Test name
Test status
Simulation time	49203800 ps
CPU time	13.77 seconds
Started	Aug 10 07:29:00 PM PDT 24
Finished	Aug 10 07:29:14 PM PDT 24
Peak memory	261812 kb
Host	smart-67182b99-fe9c-42f5-a84c-0f040bf79b45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696163965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 1696163965
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1102404734
Short name	T1234
Test name
Test status
Simulation time	47707700 ps
CPU time	13.49 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261760 kb
Host	smart-a196bd7d-0d68-4fbd-80a1-7e7baa3ad2c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102404734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 1102404734
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2959774702
Short name	T1151
Test name
Test status
Simulation time	14665600 ps
CPU time	13.35 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:21 PM PDT 24
Peak memory	261872 kb
Host	smart-bcfd586d-cd04-46f4-b27a-d0d41259db7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959774702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test. 2959774702
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1332627747
Short name	T1233
Test name
Test status
Simulation time	15536215700 ps
CPU time	71.43 seconds
Started	Aug 10 07:28:26 PM PDT 24
Finished	Aug 10 07:29:38 PM PDT 24
Peak memory	261940 kb
Host	smart-afa606cf-c291-404c-8218-9625d78f0e8f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332627747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.1332627747
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2108751792
Short name	T1256
Test name
Test status
Simulation time	4090881900 ps
CPU time	51.04 seconds
Started	Aug 10 07:28:26 PM PDT 24
Finished	Aug 10 07:29:17 PM PDT 24
Peak memory	261864 kb
Host	smart-29258a6a-97b6-4e98-bc22-27fb7113aee8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108751792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.2108751792
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3591155418
Short name	T278
Test name
Test status
Simulation time	101691000 ps
CPU time	45.7 seconds
Started	Aug 10 07:28:26 PM PDT 24
Finished	Aug 10 07:29:12 PM PDT 24
Peak memory	261784 kb
Host	smart-05430420-c829-4487-8940-10ac160a867b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591155418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_hw_reset.3591155418
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.549858968
Short name	T279
Test name
Test status
Simulation time	612626000 ps
CPU time	16.77 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:28:40 PM PDT 24
Peak memory	271240 kb
Host	smart-467dc305-1fe3-48af-9ab8-fbf3e2b1d103
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549858968 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.549858968
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2057902359
Short name	T237
Test name
Test status
Simulation time	69639200 ps
CPU time	17.37 seconds
Started	Aug 10 07:28:24 PM PDT 24
Finished	Aug 10 07:28:42 PM PDT 24
Peak memory	261740 kb
Host	smart-11c8a3db-a0ed-45a0-8dd0-4f44d4c6b384
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057902359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_csr_rw.2057902359
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3939601885
Short name	T1197
Test name
Test status
Simulation time	28876800 ps
CPU time	13.56 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:30 PM PDT 24
Peak memory	261764 kb
Host	smart-4e3da16e-bafa-45d2-80a4-e8ce0157a17f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939601885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3 939601885
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1964522703
Short name	T227
Test name
Test status
Simulation time	56141000 ps
CPU time	14.09 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:31 PM PDT 24
Peak memory	263380 kb
Host	smart-6a9f65df-6cb1-4284-93b1-f12937c8812a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964522703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_mem_partial_access.1964522703
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3268676775
Short name	T1124
Test name
Test status
Simulation time	15571900 ps
CPU time	13.17 seconds
Started	Aug 10 07:28:16 PM PDT 24
Finished	Aug 10 07:28:29 PM PDT 24
Peak memory	261832 kb
Host	smart-f142531e-5f16-4e02-a154-f9df4f5d5327
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268676775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.3268676775
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.891406866
Short name	T1212
Test name
Test status
Simulation time	313729500 ps
CPU time	20.26 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	264340 kb
Host	smart-7cd3515d-e932-4f38-9d5e-97cca828fd0b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891406866 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.891406866
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1479735841
Short name	T1185
Test name
Test status
Simulation time	23875300 ps
CPU time	16.09 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:28:33 PM PDT 24
Peak memory	253820 kb
Host	smart-58652baf-667c-4849-9758-702727603959
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479735841 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1479735841
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3535566845
Short name	T1132
Test name
Test status
Simulation time	43981300 ps
CPU time	15.71 seconds
Started	Aug 10 07:28:15 PM PDT 24
Finished	Aug 10 07:28:30 PM PDT 24
Peak memory	253672 kb
Host	smart-7d2b44c9-7b64-4b4f-a33b-987689f8e28e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535566845 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3535566845
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.229328524
Short name	T253
Test name
Test status
Simulation time	65111800 ps
CPU time	19.92 seconds
Started	Aug 10 07:28:19 PM PDT 24
Finished	Aug 10 07:28:39 PM PDT 24
Peak memory	264408 kb
Host	smart-1fe1d5ba-0d36-40dd-904c-b4abd34c94ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229328524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.229328524
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1393227679
Short name	T297
Test name
Test status
Simulation time	917225500 ps
CPU time	463.86 seconds
Started	Aug 10 07:28:17 PM PDT 24
Finished	Aug 10 07:36:01 PM PDT 24
Peak memory	264364 kb
Host	smart-04f5ef4b-77d0-4bd2-ace6-14d0990c4265
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393227679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.1393227679
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.339697296
Short name	T1232
Test name
Test status
Simulation time	29591000 ps
CPU time	13.79 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261784 kb
Host	smart-0c22cc34-9249-4845-b4ff-20a994db31c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339697296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.339697296
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1263953787
Short name	T299
Test name
Test status
Simulation time	17914100 ps
CPU time	13.4 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:21 PM PDT 24
Peak memory	261792 kb
Host	smart-ed2e3d2a-b606-42a3-856f-66ccd5e7e193
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263953787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test. 1263953787
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3928791617
Short name	T1251
Test name
Test status
Simulation time	20270100 ps
CPU time	13.69 seconds
Started	Aug 10 07:29:06 PM PDT 24
Finished	Aug 10 07:29:20 PM PDT 24
Peak memory	261708 kb
Host	smart-56e21ef5-d6f3-4824-a9ef-8c5423e2aaed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928791617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test. 3928791617
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3519187909
Short name	T1139
Test name
Test status
Simulation time	28628900 ps
CPU time	13.28 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:14 PM PDT 24
Peak memory	261816 kb
Host	smart-f0eb09f0-9d6b-4dc5-94b3-2720014cd41a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519187909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test. 3519187909
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3553240673
Short name	T302
Test name
Test status
Simulation time	44495000 ps
CPU time	13.75 seconds
Started	Aug 10 07:29:11 PM PDT 24
Finished	Aug 10 07:29:25 PM PDT 24
Peak memory	262024 kb
Host	smart-8b71a910-597a-4ac2-93f7-3ef96c653a61
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553240673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 3553240673
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3061276802
Short name	T1174
Test name
Test status
Simulation time	18337700 ps
CPU time	13.56 seconds
Started	Aug 10 07:29:10 PM PDT 24
Finished	Aug 10 07:29:23 PM PDT 24
Peak memory	261844 kb
Host	smart-14c41ec1-2331-40c0-8bdf-4d90f77d3456
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061276802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 3061276802
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3815095414
Short name	T1204
Test name
Test status
Simulation time	131719400 ps
CPU time	13.7 seconds
Started	Aug 10 07:29:00 PM PDT 24
Finished	Aug 10 07:29:14 PM PDT 24
Peak memory	261876 kb
Host	smart-1c3d89e4-ce9c-485c-bd74-4b131ffee31c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815095414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 3815095414
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.912287252
Short name	T1221
Test name
Test status
Simulation time	43137800 ps
CPU time	13.69 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261808 kb
Host	smart-6f22e959-269f-4f20-8be3-3326c67c9c73
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912287252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.912287252
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1226152321
Short name	T245
Test name
Test status
Simulation time	92517400 ps
CPU time	13.54 seconds
Started	Aug 10 07:29:01 PM PDT 24
Finished	Aug 10 07:29:15 PM PDT 24
Peak memory	261836 kb
Host	smart-16a1148a-89d5-489f-b19f-a7ee42509546
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226152321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test. 1226152321
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.872477762
Short name	T1223
Test name
Test status
Simulation time	439369200 ps
CPU time	53.68 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:29:17 PM PDT 24
Peak memory	261888 kb
Host	smart-95a49034-a7a8-45af-9c33-a3997646419a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872477762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_aliasing.872477762
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.448354161
Short name	T1188
Test name
Test status
Simulation time	5342449900 ps
CPU time	76.3 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:29:39 PM PDT 24
Peak memory	261832 kb
Host	smart-f1bd354a-794d-400d-9fa6-f3817fe78abf
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448354161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_bit_bash.448354161
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.623794862
Short name	T1228
Test name
Test status
Simulation time	28903000 ps
CPU time	30.77 seconds
Started	Aug 10 07:28:24 PM PDT 24
Finished	Aug 10 07:28:55 PM PDT 24
Peak memory	261872 kb
Host	smart-3ff4cfc7-e538-4b8d-9198-c8d63a164b1b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623794862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_hw_reset.623794862
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4197917507
Short name	T1155
Test name
Test status
Simulation time	45498900 ps
CPU time	18.37 seconds
Started	Aug 10 07:28:25 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	272756 kb
Host	smart-a0844737-7b0d-46af-8823-1f7bcdab5fbb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197917507 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.4197917507
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1207471232
Short name	T1184
Test name
Test status
Simulation time	98134700 ps
CPU time	14.66 seconds
Started	Aug 10 07:28:22 PM PDT 24
Finished	Aug 10 07:28:37 PM PDT 24
Peak memory	264276 kb
Host	smart-6daf262f-5202-4db0-ba8c-a761c23c11e5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207471232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_csr_rw.1207471232
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.389226574
Short name	T1178
Test name
Test status
Simulation time	53738300 ps
CPU time	13.33 seconds
Started	Aug 10 07:28:27 PM PDT 24
Finished	Aug 10 07:28:40 PM PDT 24
Peak memory	261732 kb
Host	smart-a19d2f76-e708-4238-afa0-cc085711096d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389226574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.389226574
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1139382154
Short name	T230
Test name
Test status
Simulation time	59670600 ps
CPU time	13.45 seconds
Started	Aug 10 07:28:22 PM PDT 24
Finished	Aug 10 07:28:36 PM PDT 24
Peak memory	262668 kb
Host	smart-3b654a13-c7aa-4151-8f36-5c40ee66001d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139382154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.1139382154
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.646157881
Short name	T1179
Test name
Test status
Simulation time	96612600 ps
CPU time	13.36 seconds
Started	Aug 10 07:28:24 PM PDT 24
Finished	Aug 10 07:28:38 PM PDT 24
Peak memory	261820 kb
Host	smart-b996e129-1fea-44fe-a1a8-d88fd7f4e629
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646157881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem _walk.646157881
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.203778605
Short name	T1218
Test name
Test status
Simulation time	819557700 ps
CPU time	15.94 seconds
Started	Aug 10 07:28:22 PM PDT 24
Finished	Aug 10 07:28:38 PM PDT 24
Peak memory	263356 kb
Host	smart-73584aca-0c2d-4ccb-997d-b93930a41611
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203778605 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.203778605
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.363770997
Short name	T1187
Test name
Test status
Simulation time	25756400 ps
CPU time	15.76 seconds
Started	Aug 10 07:28:27 PM PDT 24
Finished	Aug 10 07:28:42 PM PDT 24
Peak memory	253676 kb
Host	smart-81ea97c8-ed6a-4921-88bb-0106c38d9cb3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363770997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.363770997
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.55935319
Short name	T1250
Test name
Test status
Simulation time	108082100 ps
CPU time	16.02 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:28:39 PM PDT 24
Peak memory	253680 kb
Host	smart-5e54c1a9-4f02-4b98-bc93-84aa81a22252
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55935319 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.55935319
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3770908421
Short name	T1209
Test name
Test status
Simulation time	118851400 ps
CPU time	15.86 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:28:39 PM PDT 24
Peak memory	264404 kb
Host	smart-cdfa34fd-b998-4b8e-a8d6-911ec49fb7c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770908421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3 770908421
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3608781384
Short name	T1257
Test name
Test status
Simulation time	308194700 ps
CPU time	460.41 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:36:04 PM PDT 24
Peak memory	264356 kb
Host	smart-11eb8b39-4365-4321-b8fe-ff21e48db08b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608781384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.3608781384
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2564867880
Short name	T1249
Test name
Test status
Simulation time	24571200 ps
CPU time	13.43 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261788 kb
Host	smart-e4feb046-d18e-429f-83c6-70fddac32f54
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564867880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 2564867880
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3433050752
Short name	T300
Test name
Test status
Simulation time	16633500 ps
CPU time	13.42 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:21 PM PDT 24
Peak memory	261780 kb
Host	smart-aec128c4-ac57-4f63-9fd6-360d28116188
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433050752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 3433050752
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3779082791
Short name	T1134
Test name
Test status
Simulation time	203360900 ps
CPU time	13.78 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261880 kb
Host	smart-be809e06-fe6b-4dfc-ac72-f725149207a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779082791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 3779082791
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.312440661
Short name	T1227
Test name
Test status
Simulation time	18430800 ps
CPU time	13.73 seconds
Started	Aug 10 07:29:10 PM PDT 24
Finished	Aug 10 07:29:23 PM PDT 24
Peak memory	262012 kb
Host	smart-dc2e1d0f-7f3d-4d56-89ad-4e847843dc04
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312440661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.312440661
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2513693359
Short name	T298
Test name
Test status
Simulation time	15817700 ps
CPU time	13.47 seconds
Started	Aug 10 07:29:09 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261768 kb
Host	smart-d692a881-9dde-436b-b472-c7ffef9263f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513693359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test. 2513693359
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1578906647
Short name	T303
Test name
Test status
Simulation time	17180200 ps
CPU time	13.51 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:21 PM PDT 24
Peak memory	261776 kb
Host	smart-449bd5c5-a94d-4f39-84e7-e5e3f7732a83
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578906647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 1578906647
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3972274116
Short name	T1176
Test name
Test status
Simulation time	47968200 ps
CPU time	13.48 seconds
Started	Aug 10 07:29:09 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261812 kb
Host	smart-d71f22f5-00ca-4f10-b6c1-16d26325837c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972274116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 3972274116
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4196695283
Short name	T1196
Test name
Test status
Simulation time	30125100 ps
CPU time	13.89 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261812 kb
Host	smart-7fa893b8-0e57-49d3-be0e-026058bccdfc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196695283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 4196695283
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2500242298
Short name	T1231
Test name
Test status
Simulation time	267527000 ps
CPU time	13.64 seconds
Started	Aug 10 07:29:08 PM PDT 24
Finished	Aug 10 07:29:22 PM PDT 24
Peak memory	261880 kb
Host	smart-eee0b589-02f8-4a69-bc69-e9137fb8237d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500242298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 2500242298
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1779123928
Short name	T1194
Test name
Test status
Simulation time	15103100 ps
CPU time	13.82 seconds
Started	Aug 10 07:29:11 PM PDT 24
Finished	Aug 10 07:29:25 PM PDT 24
Peak memory	261872 kb
Host	smart-a53d9986-4f36-4a0d-a1c4-2376a7eb4323
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779123928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test. 1779123928
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3231658136
Short name	T1207
Test name
Test status
Simulation time	26422400 ps
CPU time	17.78 seconds
Started	Aug 10 07:28:30 PM PDT 24
Finished	Aug 10 07:28:48 PM PDT 24
Peak memory	272596 kb
Host	smart-803180df-37d5-497b-9bcb-641134c95f03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231658136 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3231658136
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1303276696
Short name	T1242
Test name
Test status
Simulation time	68442800 ps
CPU time	17.45 seconds
Started	Aug 10 07:28:25 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	264252 kb
Host	smart-97bee264-a036-4517-988f-955a12feb2be
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303276696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.1303276696
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2192002331
Short name	T1211
Test name
Test status
Simulation time	52134900 ps
CPU time	13.4 seconds
Started	Aug 10 07:28:22 PM PDT 24
Finished	Aug 10 07:28:36 PM PDT 24
Peak memory	261880 kb
Host	smart-2b086760-f0c0-4a03-a4f7-0d2ceb456e81
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192002331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2 192002331
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.478324716
Short name	T238
Test name
Test status
Simulation time	333886900 ps
CPU time	18.22 seconds
Started	Aug 10 07:28:32 PM PDT 24
Finished	Aug 10 07:28:50 PM PDT 24
Peak memory	263920 kb
Host	smart-2dfa0b89-0efb-4711-967b-e5c2cef361bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478324716 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.478324716
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1047947270
Short name	T1214
Test name
Test status
Simulation time	12955400 ps
CPU time	15.86 seconds
Started	Aug 10 07:28:24 PM PDT 24
Finished	Aug 10 07:28:40 PM PDT 24
Peak memory	253748 kb
Host	smart-ddf6c85c-3706-48e7-a24d-3caf15c7e2bb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047947270 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.1047947270
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3587070527
Short name	T1123
Test name
Test status
Simulation time	38137500 ps
CPU time	15.44 seconds
Started	Aug 10 07:28:26 PM PDT 24
Finished	Aug 10 07:28:42 PM PDT 24
Peak memory	253704 kb
Host	smart-7be0cb73-cdcf-4e6e-9c8b-dc17ee268aa8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587070527 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3587070527
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3020177755
Short name	T123
Test name
Test status
Simulation time	40793900 ps
CPU time	16.66 seconds
Started	Aug 10 07:28:23 PM PDT 24
Finished	Aug 10 07:28:40 PM PDT 24
Peak memory	264356 kb
Host	smart-c33df13a-df43-4f88-be2a-2462e13d7dcb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020177755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3 020177755
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1092407937
Short name	T341
Test name
Test status
Simulation time	177969900 ps
CPU time	463.16 seconds
Started	Aug 10 07:28:26 PM PDT 24
Finished	Aug 10 07:36:10 PM PDT 24
Peak memory	262988 kb
Host	smart-48dde6e9-c46f-4da6-a542-bd74640cd5b6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092407937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _tl_intg_err.1092407937
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2719344614
Short name	T1199
Test name
Test status
Simulation time	377922100 ps
CPU time	19.39 seconds
Started	Aug 10 07:28:30 PM PDT 24
Finished	Aug 10 07:28:49 PM PDT 24
Peak memory	271208 kb
Host	smart-a371cc47-266a-4c63-99ae-e927112ef01c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719344614 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2719344614
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2055887582
Short name	T239
Test name
Test status
Simulation time	36947300 ps
CPU time	16.48 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:46 PM PDT 24
Peak memory	261812 kb
Host	smart-f6cd3a94-aa85-447e-986f-7f66f8d22cfd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055887582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.2055887582
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2113859431
Short name	T1237
Test name
Test status
Simulation time	34842100 ps
CPU time	13.43 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	261760 kb
Host	smart-3e9cbc9c-7805-41a4-ac62-ba2d5a46e9f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113859431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2 113859431
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2553142825
Short name	T1163
Test name
Test status
Simulation time	35626000 ps
CPU time	17.5 seconds
Started	Aug 10 07:28:28 PM PDT 24
Finished	Aug 10 07:28:46 PM PDT 24
Peak memory	262116 kb
Host	smart-45ef91c4-c73f-4ee3-9330-0afe155735cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553142825 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2553142825
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1534815832
Short name	T1118
Test name
Test status
Simulation time	40589400 ps
CPU time	15.79 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:45 PM PDT 24
Peak memory	253612 kb
Host	smart-2da84508-55f0-41e5-a251-428633d944ea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534815832 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.1534815832
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.551779640
Short name	T1125
Test name
Test status
Simulation time	15232500 ps
CPU time	15.77 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:45 PM PDT 24
Peak memory	253760 kb
Host	smart-62c93f5e-49d1-4a4a-b2ec-7964beb081e5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551779640 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.551779640
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.795857004
Short name	T347
Test name
Test status
Simulation time	894183800 ps
CPU time	899.05 seconds
Started	Aug 10 07:28:30 PM PDT 24
Finished	Aug 10 07:43:29 PM PDT 24
Peak memory	264412 kb
Host	smart-82cd6981-cc0d-490d-8974-afc8ed171f8b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795857004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ tl_intg_err.795857004
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.435886974
Short name	T1182
Test name
Test status
Simulation time	91620700 ps
CPU time	18.48 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:47 PM PDT 24
Peak memory	272540 kb
Host	smart-a6d9e253-27b4-42f6-9474-3b4038e89112
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435886974 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.435886974
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.735930111
Short name	T1133
Test name
Test status
Simulation time	34526300 ps
CPU time	14.07 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	264256 kb
Host	smart-7d2d50be-b11d-43d1-948f-7924993c9daf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735930111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_csr_rw.735930111
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2993504418
Short name	T1213
Test name
Test status
Simulation time	16614800 ps
CPU time	13.7 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	261820 kb
Host	smart-35006926-d9aa-48aa-98ac-9165f18fd8f2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993504418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2 993504418
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3754364395
Short name	T1236
Test name
Test status
Simulation time	125486500 ps
CPU time	15.93 seconds
Started	Aug 10 07:28:27 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	263216 kb
Host	smart-979980e1-8834-40f7-9235-dfb632c98849
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754364395 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3754364395
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2414185112
Short name	T1157
Test name
Test status
Simulation time	19102700 ps
CPU time	15.44 seconds
Started	Aug 10 07:28:33 PM PDT 24
Finished	Aug 10 07:28:48 PM PDT 24
Peak memory	253636 kb
Host	smart-1d6bf90e-7e60-417e-846e-01076f909e0a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414185112 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2414185112
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1546676457
Short name	T1119
Test name
Test status
Simulation time	13326300 ps
CPU time	15.5 seconds
Started	Aug 10 07:28:32 PM PDT 24
Finished	Aug 10 07:28:48 PM PDT 24
Peak memory	253640 kb
Host	smart-7d8f04c5-e5d5-4483-b0f8-2dc7acd2d3c2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546676457 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1546676457
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.70100809
Short name	T248
Test name
Test status
Simulation time	116395900 ps
CPU time	17.18 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:47 PM PDT 24
Peak memory	264560 kb
Host	smart-4528850c-cc5a-418e-aa60-1c667c84879f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70100809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.70100809
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2926935259
Short name	T252
Test name
Test status
Simulation time	368674300 ps
CPU time	455.98 seconds
Started	Aug 10 07:28:33 PM PDT 24
Finished	Aug 10 07:36:09 PM PDT 24
Peak memory	264300 kb
Host	smart-6a8c5082-997d-4cf6-9313-8fcf3c2a91c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926935259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.2926935259
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1983756949
Short name	T72
Test name
Test status
Simulation time	143394900 ps
CPU time	19.42 seconds
Started	Aug 10 07:28:28 PM PDT 24
Finished	Aug 10 07:28:48 PM PDT 24
Peak memory	272596 kb
Host	smart-1a9551f4-7e6a-4333-a92e-8ba8445259d5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983756949 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1983756949
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3214682953
Short name	T1168
Test name
Test status
Simulation time	842685500 ps
CPU time	17.7 seconds
Started	Aug 10 07:28:30 PM PDT 24
Finished	Aug 10 07:28:48 PM PDT 24
Peak memory	261860 kb
Host	smart-3ad7a6af-4874-475e-83f7-8d9ba678fc12
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214682953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.3214682953
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1327387024
Short name	T1171
Test name
Test status
Simulation time	17095500 ps
CPU time	13.64 seconds
Started	Aug 10 07:28:28 PM PDT 24
Finished	Aug 10 07:28:42 PM PDT 24
Peak memory	261788 kb
Host	smart-09e42889-6f95-4ba5-bfe4-177165842614
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327387024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1 327387024
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2026404420
Short name	T1229
Test name
Test status
Simulation time	65945500 ps
CPU time	19.62 seconds
Started	Aug 10 07:28:28 PM PDT 24
Finished	Aug 10 07:28:48 PM PDT 24
Peak memory	263244 kb
Host	smart-a4483b0f-d032-4190-9167-7fa2eec0fdae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026404420 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2026404420
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2350983549
Short name	T1129
Test name
Test status
Simulation time	37061600 ps
CPU time	15.59 seconds
Started	Aug 10 07:28:29 PM PDT 24
Finished	Aug 10 07:28:44 PM PDT 24
Peak memory	253612 kb
Host	smart-a870d184-fa41-487d-a778-729b97ea7380
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350983549 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2350983549
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1632657313
Short name	T1245
Test name
Test status
Simulation time	15191600 ps
CPU time	13.15 seconds
Started	Aug 10 07:28:30 PM PDT 24
Finished	Aug 10 07:28:43 PM PDT 24
Peak memory	253620 kb
Host	smart-4114a59c-d467-41be-9a05-3a0d6ecd5148
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632657313 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1632657313
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3262196157
Short name	T256
Test name
Test status
Simulation time	542445200 ps
CPU time	19 seconds
Started	Aug 10 07:28:28 PM PDT 24
Finished	Aug 10 07:28:47 PM PDT 24
Peak memory	264400 kb
Host	smart-05dd5c82-234a-4b04-89c7-22a53db78dbc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262196157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3 262196157
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2942879667
Short name	T339
Test name
Test status
Simulation time	368378800 ps
CPU time	888.84 seconds
Started	Aug 10 07:28:28 PM PDT 24
Finished	Aug 10 07:43:17 PM PDT 24
Peak memory	264328 kb
Host	smart-decb40c8-77c6-4150-bb80-54bbcaed3258
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942879667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.2942879667
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1227402917
Short name	T71
Test name
Test status
Simulation time	225873800 ps
CPU time	15.21 seconds
Started	Aug 10 07:28:37 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	264396 kb
Host	smart-6918773d-2a5e-4335-87ec-e4ab7d6c5b5e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227402917 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1227402917
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.778713970
Short name	T1161
Test name
Test status
Simulation time	58232700 ps
CPU time	17.81 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:57 PM PDT 24
Peak memory	264216 kb
Host	smart-686183c5-224e-4cfc-8cdc-c470172cdce9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778713970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_csr_rw.778713970
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.283847933
Short name	T1198
Test name
Test status
Simulation time	17687900 ps
CPU time	13.32 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:52 PM PDT 24
Peak memory	261736 kb
Host	smart-c95dbde2-f1fa-4b59-86e8-630e9a30a052
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283847933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.283847933
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4059769801
Short name	T1166
Test name
Test status
Simulation time	40336800 ps
CPU time	17.67 seconds
Started	Aug 10 07:28:35 PM PDT 24
Finished	Aug 10 07:28:53 PM PDT 24
Peak memory	263640 kb
Host	smart-5074d1cd-e7ee-4a3f-9dc5-a610dc4420c3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059769801 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.4059769801
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3595012174
Short name	T1177
Test name
Test status
Simulation time	29825600 ps
CPU time	13.03 seconds
Started	Aug 10 07:28:37 PM PDT 24
Finished	Aug 10 07:28:50 PM PDT 24
Peak memory	253664 kb
Host	smart-7dee1c7d-60c2-4d39-a456-a51284023f32
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595012174 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.3595012174
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1694187551
Short name	T1254
Test name
Test status
Simulation time	13026400 ps
CPU time	15.57 seconds
Started	Aug 10 07:28:39 PM PDT 24
Finished	Aug 10 07:28:54 PM PDT 24
Peak memory	253652 kb
Host	smart-1bbc6058-911c-4a47-934e-5c83051e83eb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694187551 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1694187551
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1940711760
Short name	T1173
Test name
Test status
Simulation time	212175400 ps
CPU time	19.82 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:28:56 PM PDT 24
Peak memory	263348 kb
Host	smart-3d3cd1df-7636-4c63-9706-466592fac284
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940711760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1 940711760
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.421145006
Short name	T277
Test name
Test status
Simulation time	1619592500 ps
CPU time	458.65 seconds
Started	Aug 10 07:28:36 PM PDT 24
Finished	Aug 10 07:36:15 PM PDT 24
Peak memory	264304 kb
Host	smart-db082589-ded0-4a25-b6e4-5843882ced2b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421145006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ tl_intg_err.421145006
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.3292223668
Short name	T693
Test name
Test status
Simulation time	42104300 ps
CPU time	13.89 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:34:16 PM PDT 24
Peak memory	258708 kb
Host	smart-bf82e4c2-751a-4a08-8a5b-a900106f8066
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292223668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3 292223668
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.2008185908
Short name	T402
Test name
Test status
Simulation time	42858900 ps
CPU time	15.65 seconds
Started	Aug 10 07:33:59 PM PDT 24
Finished	Aug 10 07:34:15 PM PDT 24
Peak memory	284992 kb
Host	smart-e37565df-b339-4bc0-9646-c9904c8b7b63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008185908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2008185908
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_derr_detect.3165880024
Short name	T674
Test name
Test status
Simulation time	2880093100 ps
CPU time	209.87 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 07:37:26 PM PDT 24
Peak memory	281532 kb
Host	smart-232f9edd-418c-4c70-99eb-36b29c608c51
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165880024 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.3165880024
Directory	/workspace/0.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.915557708
Short name	T1047
Test name
Test status
Simulation time	14980900 ps
CPU time	21.78 seconds
Started	Aug 10 07:33:57 PM PDT 24
Finished	Aug 10 07:34:19 PM PDT 24
Peak memory	274220 kb
Host	smart-1c6df3c6-2a6b-4c21-be9f-e046e2f3006e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915557708 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.915557708
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.289430142
Short name	T750
Test name
Test status
Simulation time	19061717600 ps
CPU time	609.2 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:44:00 PM PDT 24
Peak memory	263976 kb
Host	smart-f90713e7-3e33-42fd-b256-c32845a4cc61
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=289430142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.289430142
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.1641124473
Short name	T865
Test name
Test status
Simulation time	847811600 ps
CPU time	24.36 seconds
Started	Aug 10 07:33:50 PM PDT 24
Finished	Aug 10 07:34:15 PM PDT 24
Peak memory	263116 kb
Host	smart-68c6ae76-278f-4eb6-89d8-0c4826cc4f0c
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641124473 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.1641124473
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.335120572
Short name	T559
Test name
Test status
Simulation time	57748700 ps
CPU time	27.86 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:34:30 PM PDT 24
Peak memory	274108 kb
Host	smart-54f63ce6-4f53-48de-b129-9285e7b6f735
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335120572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_host_addr_infection.335120572
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.2145556235
Short name	T873
Test name
Test status
Simulation time	29873900 ps
CPU time	48.75 seconds
Started	Aug 10 07:33:43 PM PDT 24
Finished	Aug 10 07:34:33 PM PDT 24
Peak memory	265888 kb
Host	smart-ca129126-8f2b-4ab8-b65e-7bcb88c6e585
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2145556235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2145556235
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1285136694
Short name	T623
Test name
Test status
Simulation time	15386900 ps
CPU time	13.72 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 07:34:10 PM PDT 24
Peak memory	265260 kb
Host	smart-b560a906-55bc-4d7b-b957-b1065c6d581d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285136694 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1285136694
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.56788778
Short name	T853
Test name
Test status
Simulation time	376753930000 ps
CPU time	2301.17 seconds
Started	Aug 10 07:33:49 PM PDT 24
Finished	Aug 10 08:12:10 PM PDT 24
Peak memory	265632 kb
Host	smart-a3cde8ad-acce-4d12-82f2-354f9753b698
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56788778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_hw_rma.56788778
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.657813238
Short name	T993
Test name
Test status
Simulation time	40122180200 ps
CPU time	796.7 seconds
Started	Aug 10 07:33:45 PM PDT 24
Finished	Aug 10 07:47:02 PM PDT 24
Peak memory	261552 kb
Host	smart-9d249d41-a61b-4441-b393-85568ff5a80b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657813238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_hw_rma_reset.657813238
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1683645959
Short name	T1088
Test name
Test status
Simulation time	12045012900 ps
CPU time	103.71 seconds
Started	Aug 10 07:33:50 PM PDT 24
Finished	Aug 10 07:35:34 PM PDT 24
Peak memory	261308 kb
Host	smart-a4c6fbf7-13c0-4017-96d1-82820e4aed48
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683645959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.1683645959
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_integrity.1792337540
Short name	T1113
Test name
Test status
Simulation time	30163803100 ps
CPU time	576.44 seconds
Started	Aug 10 07:33:50 PM PDT 24
Finished	Aug 10 07:43:27 PM PDT 24
Peak memory	332056 kb
Host	smart-d8e3fc37-f368-4640-b6c4-dc884a1c8ae7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792337540 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_integrity.1792337540
Directory	/workspace/0.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.34439755
Short name	T17
Test name
Test status
Simulation time	7896920300 ps
CPU time	129.7 seconds
Started	Aug 10 07:33:52 PM PDT 24
Finished	Aug 10 07:36:02 PM PDT 24
Peak memory	285672 kb
Host	smart-da02cce8-5671-450a-b469-5fd95e2e2604
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ ctrl_intr_rd.34439755
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3090502466
Short name	T943
Test name
Test status
Simulation time	41119846800 ps
CPU time	304.76 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:38:56 PM PDT 24
Peak memory	290488 kb
Host	smart-616cb38e-8a5f-4c16-9572-2f97c765ca61
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090502466 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3090502466
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.2975621191
Short name	T791
Test name
Test status
Simulation time	2720234200 ps
CPU time	66.26 seconds
Started	Aug 10 07:33:54 PM PDT 24
Finished	Aug 10 07:35:00 PM PDT 24
Peak memory	261184 kb
Host	smart-4b32be52-7a9c-4093-8bc4-5bac6da5a846
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975621191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_intr_wr.2975621191
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.419540737
Short name	T431
Test name
Test status
Simulation time	24789856600 ps
CPU time	188.76 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:37:00 PM PDT 24
Peak memory	265580 kb
Host	smart-09a36681-6062-4dd7-86b2-4080ca99e3e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419 540737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.419540737
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.2922804565
Short name	T426
Test name
Test status
Simulation time	2310122900 ps
CPU time	80.3 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 07:35:16 PM PDT 24
Peak memory	261456 kb
Host	smart-ca33913d-eb36-4e05-b9fc-b5cb1237751d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922804565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2922804565
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3102497727
Short name	T527
Test name
Test status
Simulation time	26292800 ps
CPU time	13.62 seconds
Started	Aug 10 07:33:57 PM PDT 24
Finished	Aug 10 07:34:11 PM PDT 24
Peak memory	265396 kb
Host	smart-81642d4c-a8de-4263-bd86-d851daf49ee1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102497727 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3102497727
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.103305390
Short name	T935
Test name
Test status
Simulation time	8336388700 ps
CPU time	267.53 seconds
Started	Aug 10 07:33:53 PM PDT 24
Finished	Aug 10 07:38:21 PM PDT 24
Peak memory	274576 kb
Host	smart-789f1456-965c-4709-8123-2d14ca6736ed
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103305390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.103305390
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.3117186579
Short name	T666
Test name
Test status
Simulation time	124173700 ps
CPU time	133.86 seconds
Started	Aug 10 07:33:45 PM PDT 24
Finished	Aug 10 07:35:59 PM PDT 24
Peak memory	261576 kb
Host	smart-f1df4a27-96ee-4672-b2d2-d77c91ff53e0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117186579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot p_reset.3117186579
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.3608021572
Short name	T913
Test name
Test status
Simulation time	89243500 ps
CPU time	413.34 seconds
Started	Aug 10 07:33:46 PM PDT 24
Finished	Aug 10 07:40:39 PM PDT 24
Peak memory	263724 kb
Host	smart-9e3ec1dc-f234-4e91-9be9-17635e77a6d7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3608021572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3608021572
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1561125590
Short name	T632
Test name
Test status
Simulation time	26163800 ps
CPU time	14.11 seconds
Started	Aug 10 07:33:58 PM PDT 24
Finished	Aug 10 07:34:13 PM PDT 24
Peak memory	266156 kb
Host	smart-ce54cc47-092b-4f64-9ad4-049ecbfaee51
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561125590 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1561125590
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.1656622461
Short name	T401
Test name
Test status
Simulation time	5260362200 ps
CPU time	159.47 seconds
Started	Aug 10 07:33:57 PM PDT 24
Finished	Aug 10 07:36:37 PM PDT 24
Peak memory	261176 kb
Host	smart-9c2f8a4b-2bc5-4bbe-a80d-0a661b1ead65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656622461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.1656622461
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.948054499
Short name	T643
Test name
Test status
Simulation time	412538100 ps
CPU time	484.4 seconds
Started	Aug 10 07:33:46 PM PDT 24
Finished	Aug 10 07:41:51 PM PDT 24
Peak memory	284212 kb
Host	smart-eea4035e-fb7e-452c-92a3-b9e908d5d7d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948054499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.948054499
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.5143893
Short name	T212
Test name
Test status
Simulation time	1457437800 ps
CPU time	117.26 seconds
Started	Aug 10 07:33:46 PM PDT 24
Finished	Aug 10 07:35:44 PM PDT 24
Peak memory	263376 kb
Host	smart-739d4e02-bb0a-4624-b4e4-f2b80652d3a7
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=5143893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.5143893
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.589465322
Short name	T996
Test name
Test status
Simulation time	78863400 ps
CPU time	32.34 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 07:34:29 PM PDT 24
Peak memory	276240 kb
Host	smart-2a859638-8063-431f-ab6f-9339a5a8e8cb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589465322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_rd_intg.589465322
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.3600706220
Short name	T447
Test name
Test status
Simulation time	62406000 ps
CPU time	44.98 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 07:34:41 PM PDT 24
Peak memory	276404 kb
Host	smart-131380fc-59c5-4947-9643-68e0bbb57696
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600706220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_rd_ooo.3600706220
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.3648705033
Short name	T30
Test name
Test status
Simulation time	63198800 ps
CPU time	35.09 seconds
Started	Aug 10 07:33:57 PM PDT 24
Finished	Aug 10 07:34:32 PM PDT 24
Peak memory	276276 kb
Host	smart-be64f7c2-0791-44ee-937d-674a0d48565e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648705033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.3648705033
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.1908195656
Short name	T568
Test name
Test status
Simulation time	214050300 ps
CPU time	14.39 seconds
Started	Aug 10 07:33:52 PM PDT 24
Finished	Aug 10 07:34:06 PM PDT 24
Peak memory	259348 kb
Host	smart-7c9eef02-0d78-486f-9f14-a317a32e128e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1908195656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep .1908195656
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3401205416
Short name	T876
Test name
Test status
Simulation time	61140800 ps
CPU time	22.36 seconds
Started	Aug 10 07:33:50 PM PDT 24
Finished	Aug 10 07:34:13 PM PDT 24
Peak memory	266024 kb
Host	smart-596744b6-df0c-42f6-8fc1-62152ccd1705
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401205416 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3401205416
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3078718060
Short name	T436
Test name
Test status
Simulation time	79503400 ps
CPU time	23.29 seconds
Started	Aug 10 07:33:56 PM PDT 24
Finished	Aug 10 07:34:19 PM PDT 24
Peak memory	266020 kb
Host	smart-c7e3606e-e226-4fa9-ad31-1ef6899a1283
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078718060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.3078718060
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.1890282983
Short name	T188
Test name
Test status
Simulation time	41329561400 ps
CPU time	872.73 seconds
Started	Aug 10 07:33:59 PM PDT 24
Finished	Aug 10 07:48:32 PM PDT 24
Peak memory	262008 kb
Host	smart-cffe6f06-0f63-4617-acb3-a0d1f4ab06b7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890282983 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1890282983
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.1410778495
Short name	T405
Test name
Test status
Simulation time	963848200 ps
CPU time	105.48 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:35:36 PM PDT 24
Peak memory	281912 kb
Host	smart-87d2c1f3-d8ac-4f0c-ae9d-d7d2d8aacee4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410778495 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.1410778495
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.2102078041
Short name	T725
Test name
Test status
Simulation time	1037014100 ps
CPU time	126.99 seconds
Started	Aug 10 07:33:55 PM PDT 24
Finished	Aug 10 07:36:02 PM PDT 24
Peak memory	282572 kb
Host	smart-e31257a4-a978-440e-8cf2-e017aed60e3f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102078041 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2102078041
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_derr.1037199336
Short name	T884
Test name
Test status
Simulation time	6461106900 ps
CPU time	204.58 seconds
Started	Aug 10 07:33:55 PM PDT 24
Finished	Aug 10 07:37:20 PM PDT 24
Peak memory	288072 kb
Host	smart-9c97a735-0c20-445a-8e8e-d3827d531bbc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037199336 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_derr.1037199336
Directory	/workspace/0.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict.753478996
Short name	T802
Test name
Test status
Simulation time	82673800 ps
CPU time	32.27 seconds
Started	Aug 10 07:33:59 PM PDT 24
Finished	Aug 10 07:34:32 PM PDT 24
Peak memory	276376 kb
Host	smart-38475dfe-5110-42a4-bcae-3c59260fc610
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753478996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_rw_evict.753478996
Directory	/workspace/0.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.2407200313
Short name	T818
Test name
Test status
Simulation time	69116100 ps
CPU time	31.16 seconds
Started	Aug 10 07:34:00 PM PDT 24
Finished	Aug 10 07:34:31 PM PDT 24
Peak memory	268204 kb
Host	smart-8d41744d-c001-448e-b780-6f78ca540cf4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407200313 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.2407200313
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_serr.2353868487
Short name	T524
Test name
Test status
Simulation time	4032845900 ps
CPU time	215.98 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:37:27 PM PDT 24
Peak memory	296124 kb
Host	smart-67c6b50c-1da2-4caf-bfee-b727eda0b000
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353868487 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.flash_ctrl_rw_serr.2353868487
Directory	/workspace/0.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.426526970
Short name	T1052
Test name
Test status
Simulation time	3362145200 ps
CPU time	92.92 seconds
Started	Aug 10 07:33:50 PM PDT 24
Finished	Aug 10 07:35:23 PM PDT 24
Peak memory	265716 kb
Host	smart-6c75acee-20a0-47b5-9c3b-177afa8594f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426526970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_serr_address.426526970
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.2376373005
Short name	T600
Test name
Test status
Simulation time	666290300 ps
CPU time	67.91 seconds
Started	Aug 10 07:33:52 PM PDT 24
Finished	Aug 10 07:35:00 PM PDT 24
Peak memory	274396 kb
Host	smart-65ee24e2-4477-42ca-81cb-69c0fccac9c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376373005 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.2376373005
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.851037301
Short name	T366
Test name
Test status
Simulation time	37042900 ps
CPU time	150.6 seconds
Started	Aug 10 07:33:47 PM PDT 24
Finished	Aug 10 07:36:18 PM PDT 24
Peak memory	277420 kb
Host	smart-fcc6e52c-5d18-4680-97ad-78e71165f3a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851037301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.851037301
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.2131829644
Short name	T459
Test name
Test status
Simulation time	59520500 ps
CPU time	26.76 seconds
Started	Aug 10 07:33:46 PM PDT 24
Finished	Aug 10 07:34:12 PM PDT 24
Peak memory	260404 kb
Host	smart-8e43ba99-e3ab-4ff2-8f09-32a2270a8d5d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131829644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2131829644
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.2527022469
Short name	T875
Test name
Test status
Simulation time	319488500 ps
CPU time	463.88 seconds
Started	Aug 10 07:33:57 PM PDT 24
Finished	Aug 10 07:41:41 PM PDT 24
Peak memory	276132 kb
Host	smart-65cd2c51-8388-4772-bcd4-18770744e13c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527022469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres s_all.2527022469
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.4092255966
Short name	T408
Test name
Test status
Simulation time	23571700 ps
CPU time	27.59 seconds
Started	Aug 10 07:33:45 PM PDT 24
Finished	Aug 10 07:34:13 PM PDT 24
Peak memory	262996 kb
Host	smart-faf673cc-2649-438d-9db8-f40c3e7cbe34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092255966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4092255966
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.822937299
Short name	T1015
Test name
Test status
Simulation time	8797242700 ps
CPU time	191 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:37:03 PM PDT 24
Peak memory	260000 kb
Host	smart-6fe3ca69-535e-435e-ab55-05e30c9c7e52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822937299 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_wo.822937299
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.169312571
Short name	T9
Test name
Test status
Simulation time	81641000 ps
CPU time	15.17 seconds
Started	Aug 10 07:33:55 PM PDT 24
Finished	Aug 10 07:34:11 PM PDT 24
Peak memory	261472 kb
Host	smart-6916ce35-fcf3-4a1d-9f2b-ef757b51043f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169312571 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.169312571
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.1355190782
Short name	T387
Test name
Test status
Simulation time	296163500 ps
CPU time	15.51 seconds
Started	Aug 10 07:33:51 PM PDT 24
Finished	Aug 10 07:34:07 PM PDT 24
Peak memory	265752 kb
Host	smart-19570a77-3266-4293-b1e8-b2c3f412087e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1355190782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe ep.1355190782
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.2247110816
Short name	T21
Test name
Test status
Simulation time	13382400 ps
CPU time	13.63 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:34:23 PM PDT 24
Peak memory	266060 kb
Host	smart-99975a95-731f-4360-8b5a-c9cdbf8246ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247110816 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2247110816
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.847572631
Short name	T1094
Test name
Test status
Simulation time	83017400 ps
CPU time	14 seconds
Started	Aug 10 07:34:16 PM PDT 24
Finished	Aug 10 07:34:30 PM PDT 24
Peak memory	258800 kb
Host	smart-8b04beb5-c34a-47e2-942f-cde733965896
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847572631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.847572631
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.416978298
Short name	T1009
Test name
Test status
Simulation time	92673000 ps
CPU time	13.74 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:34:24 PM PDT 24
Peak memory	262264 kb
Host	smart-9fa27d99-4cab-41a6-9692-bde1d9085395
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416978298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. flash_ctrl_config_regwen.416978298
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.2588381737
Short name	T485
Test name
Test status
Simulation time	28026600 ps
CPU time	13.45 seconds
Started	Aug 10 07:34:06 PM PDT 24
Finished	Aug 10 07:34:20 PM PDT 24
Peak memory	284944 kb
Host	smart-2176a4ef-525e-4b5b-83aa-278d5c6aee7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588381737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2588381737
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_derr_detect.348400126
Short name	T556
Test name
Test status
Simulation time	1452642900 ps
CPU time	202.18 seconds
Started	Aug 10 07:34:11 PM PDT 24
Finished	Aug 10 07:37:33 PM PDT 24
Peak memory	281652 kb
Host	smart-4297b5c9-3c49-48f4-a827-a86581784483
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348400126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_derr_detect.348400126
Directory	/workspace/1.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.1322156049
Short name	T891
Test name
Test status
Simulation time	2754412100 ps
CPU time	476.39 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:41:58 PM PDT 24
Peak memory	263960 kb
Host	smart-835a7d56-535b-4161-becb-0b2e9f6431ac
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1322156049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1322156049
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.2914805257
Short name	T761
Test name
Test status
Simulation time	12056060000 ps
CPU time	2332.17 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 08:12:54 PM PDT 24
Peak memory	265736 kb
Host	smart-cd481345-5598-44da-ad91-38a1fd2fc458
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2914805257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2914805257
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.1925964103
Short name	T108
Test name
Test status
Simulation time	703907500 ps
CPU time	2291.41 seconds
Started	Aug 10 07:34:01 PM PDT 24
Finished	Aug 10 08:12:13 PM PDT 24
Peak memory	265244 kb
Host	smart-30d5df65-bf27-468d-9c2d-188f3114a429
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925964103 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1925964103
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.2146526000
Short name	T909
Test name
Test status
Simulation time	586171500 ps
CPU time	817.64 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:47:40 PM PDT 24
Peak memory	274092 kb
Host	smart-733c11e7-33f6-4bec-9184-ed6d99701829
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2146526000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2146526000
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.1756698617
Short name	T55
Test name
Test status
Simulation time	1589571900 ps
CPU time	21.44 seconds
Started	Aug 10 07:34:04 PM PDT 24
Finished	Aug 10 07:34:26 PM PDT 24
Peak memory	263196 kb
Host	smart-bdf027e5-0f4e-4c19-bb1f-587793253dfa
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756698617 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1756698617
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.573853755
Short name	T689
Test name
Test status
Simulation time	321195600 ps
CPU time	37.5 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:34:50 PM PDT 24
Peak memory	263556 kb
Host	smart-8929641b-f474-41bc-9a0b-da29293e29d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573853755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_fs_sup.573853755
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.1308676007
Short name	T79
Test name
Test status
Simulation time	203472503300 ps
CPU time	4635.87 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 08:51:19 PM PDT 24
Peak memory	265740 kb
Host	smart-d27a2b37-a636-46af-bf85-723d0f66beaf
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308676007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.1308676007
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.634907424
Short name	T291
Test name
Test status
Simulation time	31676400 ps
CPU time	30.44 seconds
Started	Aug 10 07:34:14 PM PDT 24
Finished	Aug 10 07:34:45 PM PDT 24
Peak memory	274088 kb
Host	smart-54bb1de8-34f9-4a3d-832d-ebb8220b0f68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634907424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_host_addr_infection.634907424
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.717736526
Short name	T888
Test name
Test status
Simulation time	10040418400 ps
CPU time	56.78 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:35:07 PM PDT 24
Peak memory	285008 kb
Host	smart-25b798a0-64a4-4f8a-a4f1-14f8b8724e71
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717736526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.717736526
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.195785725
Short name	T938
Test name
Test status
Simulation time	80130270900 ps
CPU time	826.38 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:47:49 PM PDT 24
Peak memory	264436 kb
Host	smart-46714f81-0cef-499e-9bce-f7a4eccc6ef1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195785725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_hw_rma_reset.195785725
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.4006524293
Short name	T1107
Test name
Test status
Simulation time	15997963400 ps
CPU time	140.68 seconds
Started	Aug 10 07:34:06 PM PDT 24
Finished	Aug 10 07:36:27 PM PDT 24
Peak memory	263732 kb
Host	smart-03279a04-8dc0-4dd9-b4fb-a36508dce953
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006524293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h w_sec_otp.4006524293
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_integrity.910497295
Short name	T149
Test name
Test status
Simulation time	68022094900 ps
CPU time	754.44 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:46:47 PM PDT 24
Peak memory	339428 kb
Host	smart-0a42e69c-8ffb-43c0-89a5-762a6c06c990
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910497295 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_integrity.910497295
Directory	/workspace/1.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.1151773353
Short name	T529
Test name
Test status
Simulation time	1397707000 ps
CPU time	220.07 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:37:51 PM PDT 24
Peak memory	292248 kb
Host	smart-9c7521c9-d7b5-4318-88dd-4bdc4558f0e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151773353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_intr_rd.1151773353
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2360428747
Short name	T1037
Test name
Test status
Simulation time	50834833100 ps
CPU time	271.08 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:38:40 PM PDT 24
Peak memory	292592 kb
Host	smart-aa7ac129-f7c6-4a44-baa6-80ab42bf18c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360428747 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2360428747
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.4056714428
Short name	T1081
Test name
Test status
Simulation time	2156757000 ps
CPU time	65.66 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:35:15 PM PDT 24
Peak memory	261144 kb
Host	smart-c15f4c97-e774-4c46-946c-05eaccff3a89
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056714428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_wr.4056714428
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2877580008
Short name	T494
Test name
Test status
Simulation time	49098356100 ps
CPU time	197.81 seconds
Started	Aug 10 07:34:07 PM PDT 24
Finished	Aug 10 07:37:25 PM PDT 24
Peak memory	260944 kb
Host	smart-63fac663-99ed-49b8-913e-70601eb54162
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287 7580008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2877580008
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2576230470
Short name	T549
Test name
Test status
Simulation time	24921000 ps
CPU time	13.72 seconds
Started	Aug 10 07:34:08 PM PDT 24
Finished	Aug 10 07:34:22 PM PDT 24
Peak memory	265376 kb
Host	smart-397f4006-526d-4311-a46a-22e15a1bf87c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576230470 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2576230470
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.829868038
Short name	T32
Test name
Test status
Simulation time	18000322900 ps
CPU time	135.2 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:36:17 PM PDT 24
Peak memory	265764 kb
Host	smart-81a0f75a-b38a-4f24-9c69-7513012b7b63
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829868038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.829868038
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.1871890163
Short name	T172
Test name
Test status
Simulation time	128666600 ps
CPU time	111.24 seconds
Started	Aug 10 07:34:01 PM PDT 24
Finished	Aug 10 07:35:52 PM PDT 24
Peak memory	261540 kb
Host	smart-893a45d7-e6f7-4d2c-8a71-61afa6ce9e54
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871890163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot p_reset.1871890163
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.1472644086
Short name	T511
Test name
Test status
Simulation time	1395710000 ps
CPU time	206.06 seconds
Started	Aug 10 07:34:11 PM PDT 24
Finished	Aug 10 07:37:37 PM PDT 24
Peak memory	282488 kb
Host	smart-1982cf27-6415-4164-93e0-59d4201b0138
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472644086 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1472644086
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.405277060
Short name	T158
Test name
Test status
Simulation time	743569700 ps
CPU time	495.45 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:42:18 PM PDT 24
Peak memory	263696 kb
Host	smart-518d3d6d-72b9-46e6-8634-b328f5508058
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=405277060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.405277060
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.2721495642
Short name	T411
Test name
Test status
Simulation time	40092200 ps
CPU time	13.59 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:34:26 PM PDT 24
Peak memory	259532 kb
Host	smart-273ee78f-0704-41d2-bf2e-8b027414d099
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721495642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_prog_reset.2721495642
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3425774499
Short name	T863
Test name
Test status
Simulation time	8157783400 ps
CPU time	142.39 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:36:25 PM PDT 24
Peak memory	263344 kb
Host	smart-5a6cda81-e3a3-4399-827e-c8b8f1407848
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3425774499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3425774499
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.1465919845
Short name	T51
Test name
Test status
Simulation time	119271500 ps
CPU time	31.57 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:34:41 PM PDT 24
Peak memory	276236 kb
Host	smart-c7513bdd-d098-40bd-983f-02124617956f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465919845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_rd_intg.1465919845
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.1733115289
Short name	T961
Test name
Test status
Simulation time	79778800 ps
CPU time	36.55 seconds
Started	Aug 10 07:34:08 PM PDT 24
Finished	Aug 10 07:34:44 PM PDT 24
Peak memory	278992 kb
Host	smart-38699222-741d-438e-bb80-3319e0f647ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733115289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.1733115289
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1546391086
Short name	T878
Test name
Test status
Simulation time	32359200 ps
CPU time	21.39 seconds
Started	Aug 10 07:34:08 PM PDT 24
Finished	Aug 10 07:34:29 PM PDT 24
Peak memory	265868 kb
Host	smart-7d066954-9aed-4fd8-9f45-5ff4a512e130
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546391086 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1546391086
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3074284832
Short name	T956
Test name
Test status
Simulation time	69303000 ps
CPU time	22.66 seconds
Started	Aug 10 07:34:11 PM PDT 24
Finished	Aug 10 07:34:33 PM PDT 24
Peak memory	266012 kb
Host	smart-fe80e680-523f-4edb-b3ca-1d92b2a1a612
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074284832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.3074284832
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.1662189448
Short name	T995
Test name
Test status
Simulation time	2255910800 ps
CPU time	121.39 seconds
Started	Aug 10 07:34:08 PM PDT 24
Finished	Aug 10 07:36:10 PM PDT 24
Peak memory	289972 kb
Host	smart-4e6fb8b2-15e1-4a5f-97fd-e75edbdf9964
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662189448 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_ro.1662189448
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.2046125354
Short name	T466
Test name
Test status
Simulation time	653292100 ps
CPU time	151.1 seconds
Started	Aug 10 07:34:08 PM PDT 24
Finished	Aug 10 07:36:39 PM PDT 24
Peak memory	282564 kb
Host	smart-9ffaa400-7329-418f-bfe9-4de78b98c658
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2046125354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2046125354
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.754631719
Short name	T787
Test name
Test status
Simulation time	2299885200 ps
CPU time	120.77 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:36:13 PM PDT 24
Peak memory	295720 kb
Host	smart-289d63a7-ef52-4695-b78f-257bce949992
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754631719 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.754631719
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.3233040182
Short name	T56
Test name
Test status
Simulation time	2931246700 ps
CPU time	512.07 seconds
Started	Aug 10 07:34:07 PM PDT 24
Finished	Aug 10 07:42:40 PM PDT 24
Peak memory	310724 kb
Host	smart-aabca066-b350-419d-87d0-76f2656dbc4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233040182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.flash_ctrl_rw.3233040182
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.653084732
Short name	T816
Test name
Test status
Simulation time	4889048700 ps
CPU time	205.5 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:37:38 PM PDT 24
Peak memory	291268 kb
Host	smart-cd14edbb-df4d-4f0f-a22c-ed882c2a77d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653084732 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_derr.653084732
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.617009725
Short name	T29
Test name
Test status
Simulation time	45424800 ps
CPU time	31.03 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:34:41 PM PDT 24
Peak memory	274328 kb
Host	smart-898d0936-4d97-4e8c-a3e0-f97617089d8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617009725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_rw_evict.617009725
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2409312510
Short name	T704
Test name
Test status
Simulation time	59008600 ps
CPU time	28.63 seconds
Started	Aug 10 07:34:07 PM PDT 24
Finished	Aug 10 07:34:36 PM PDT 24
Peak memory	268460 kb
Host	smart-1f0da71c-f87b-4c02-b32a-5801320fd0c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409312510 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2409312510
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_serr.3269977599
Short name	T452
Test name
Test status
Simulation time	16537561500 ps
CPU time	189.47 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:37:19 PM PDT 24
Peak memory	296160 kb
Host	smart-0311f2d3-d331-4347-b5b7-9eb32d6688c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269977599 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.flash_ctrl_rw_serr.3269977599
Directory	/workspace/1.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.4168068255
Short name	T484
Test name
Test status
Simulation time	4454578600 ps
CPU time	72.48 seconds
Started	Aug 10 07:34:10 PM PDT 24
Finished	Aug 10 07:35:23 PM PDT 24
Peak memory	264256 kb
Host	smart-dcb3ba9f-c8a1-4964-a3f9-11231eaaab10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4168068255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.4168068255
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.3176139050
Short name	T850
Test name
Test status
Simulation time	9870629700 ps
CPU time	89.75 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:35:38 PM PDT 24
Peak memory	266104 kb
Host	smart-304fc45a-7ddb-4444-9320-19e6384b15ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176139050 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.3176139050
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.3278541345
Short name	T716
Test name
Test status
Simulation time	480154100 ps
CPU time	52.02 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:35:02 PM PDT 24
Peak memory	274500 kb
Host	smart-4d81e75b-c091-40ed-834f-fec3aa3fb921
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278541345 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_serr_counter.3278541345
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.3081089505
Short name	T1108
Test name
Test status
Simulation time	36353400 ps
CPU time	75.26 seconds
Started	Aug 10 07:34:01 PM PDT 24
Finished	Aug 10 07:35:17 PM PDT 24
Peak memory	277292 kb
Host	smart-2d9e2fd3-aa1a-40a0-a92c-f70aee9e81fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081089505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3081089505
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.1942437921
Short name	T826
Test name
Test status
Simulation time	53724800 ps
CPU time	26.1 seconds
Started	Aug 10 07:34:01 PM PDT 24
Finished	Aug 10 07:34:28 PM PDT 24
Peak memory	260272 kb
Host	smart-ad6a24cc-3e07-4726-bfba-0fc2dd3754d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942437921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1942437921
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.2165446211
Short name	T932
Test name
Test status
Simulation time	515439900 ps
CPU time	662.73 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:45:15 PM PDT 24
Peak memory	282256 kb
Host	smart-9859a723-1a57-4ea1-a5e5-d770930dcb89
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165446211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres s_all.2165446211
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.359379914
Short name	T969
Test name
Test status
Simulation time	41836400 ps
CPU time	27.18 seconds
Started	Aug 10 07:34:02 PM PDT 24
Finished	Aug 10 07:34:30 PM PDT 24
Peak memory	262928 kb
Host	smart-7916f494-c817-4c5e-8870-c26c323a1b38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359379914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.359379914
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.59025996
Short name	T907
Test name
Test status
Simulation time	18643209700 ps
CPU time	200.34 seconds
Started	Aug 10 07:34:09 PM PDT 24
Finished	Aug 10 07:37:30 PM PDT 24
Peak memory	265852 kb
Host	smart-11a4fbfd-dd7d-468f-83d5-6ff5f036da93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59025996 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_wo.59025996
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.2875183539
Short name	T19
Test name
Test status
Simulation time	68336000 ps
CPU time	15.23 seconds
Started	Aug 10 07:34:08 PM PDT 24
Finished	Aug 10 07:34:23 PM PDT 24
Peak memory	265908 kb
Host	smart-17638ff0-1e70-4f75-8a80-7163c259193c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875183539 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2875183539
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.1491517757
Short name	T983
Test name
Test status
Simulation time	191033900 ps
CPU time	13.49 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:37:35 PM PDT 24
Peak memory	258700 kb
Host	smart-1445e891-1157-4343-8237-45e03426e2ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491517757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test. 1491517757
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.872171162
Short name	T561
Test name
Test status
Simulation time	91125700 ps
CPU time	16.15 seconds
Started	Aug 10 07:37:23 PM PDT 24
Finished	Aug 10 07:37:39 PM PDT 24
Peak memory	283572 kb
Host	smart-09343c86-37d7-4aa1-afbe-b26d6eafb70f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872171162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.872171162
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.1181819798
Short name	T630
Test name
Test status
Simulation time	19046400 ps
CPU time	22.28 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:37:44 PM PDT 24
Peak memory	274308 kb
Host	smart-5b870e90-3c99-4ccf-96d4-124e3f36acbc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181819798 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.1181819798
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1410283161
Short name	T265
Test name
Test status
Simulation time	46864200 ps
CPU time	13.3 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:37:35 PM PDT 24
Peak memory	265868 kb
Host	smart-67251351-ee70-46b2-8792-5b06b92d7c18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410283161 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1410283161
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2898903517
Short name	T475
Test name
Test status
Simulation time	420281378800 ps
CPU time	1235.95 seconds
Started	Aug 10 07:37:10 PM PDT 24
Finished	Aug 10 07:57:46 PM PDT 24
Peak memory	261628 kb
Host	smart-a7894f55-e9e0-41d1-90c8-08eacd4218b6
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898903517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.2898903517
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.2018338712
Short name	T1034
Test name
Test status
Simulation time	1520290900 ps
CPU time	206.82 seconds
Started	Aug 10 07:37:16 PM PDT 24
Finished	Aug 10 07:40:43 PM PDT 24
Peak memory	285896 kb
Host	smart-a21f46e9-2d7f-4625-bf0f-3170ff248d4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018338712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.2018338712
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3336838988
Short name	T110
Test name
Test status
Simulation time	49159412100 ps
CPU time	281.53 seconds
Started	Aug 10 07:37:13 PM PDT 24
Finished	Aug 10 07:41:55 PM PDT 24
Peak memory	294088 kb
Host	smart-bfbd1b20-f26b-4644-af3e-0828d9c79218
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336838988 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3336838988
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.1792044072
Short name	T538
Test name
Test status
Simulation time	4060956000 ps
CPU time	89.78 seconds
Started	Aug 10 07:37:14 PM PDT 24
Finished	Aug 10 07:38:43 PM PDT 24
Peak memory	263924 kb
Host	smart-fabc5842-1f2d-4865-a30d-6d3a0b3f34c5
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792044072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1 792044072
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3016581207
Short name	T557
Test name
Test status
Simulation time	26285300 ps
CPU time	13.54 seconds
Started	Aug 10 07:37:23 PM PDT 24
Finished	Aug 10 07:37:37 PM PDT 24
Peak memory	260812 kb
Host	smart-f20a9183-6f70-4725-ad85-43534c9df691
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016581207 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3016581207
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.1005686920
Short name	T858
Test name
Test status
Simulation time	2340325300 ps
CPU time	172.75 seconds
Started	Aug 10 07:37:13 PM PDT 24
Finished	Aug 10 07:40:06 PM PDT 24
Peak memory	264396 kb
Host	smart-2f8ff913-7df7-4b4b-8187-868e19ddcd16
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005686920 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.1005686920
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.25249067
Short name	T691
Test name
Test status
Simulation time	38205900 ps
CPU time	112.24 seconds
Started	Aug 10 07:37:08 PM PDT 24
Finished	Aug 10 07:39:01 PM PDT 24
Peak memory	260772 kb
Host	smart-d6845dc5-77cd-4bf9-a3d5-60d2ff250b49
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25249067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp _reset.25249067
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3250786239
Short name	T702
Test name
Test status
Simulation time	733755900 ps
CPU time	291.19 seconds
Started	Aug 10 07:37:08 PM PDT 24
Finished	Aug 10 07:41:59 PM PDT 24
Peak memory	263672 kb
Host	smart-eb88d987-5185-4657-9557-198b88b34a2c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3250786239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3250786239
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.1183774547
Short name	T819
Test name
Test status
Simulation time	82964600 ps
CPU time	15.47 seconds
Started	Aug 10 07:37:13 PM PDT 24
Finished	Aug 10 07:37:28 PM PDT 24
Peak memory	260652 kb
Host	smart-3469d553-b399-4b65-b740-86f079b9b226
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183774547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.flash_ctrl_prog_reset.1183774547
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.1593484522
Short name	T890
Test name
Test status
Simulation time	113267600 ps
CPU time	282.49 seconds
Started	Aug 10 07:37:10 PM PDT 24
Finished	Aug 10 07:41:52 PM PDT 24
Peak memory	282156 kb
Host	smart-43d604e4-36af-4162-95a4-d6e136645226
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593484522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1593484522
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.3524338920
Short name	T554
Test name
Test status
Simulation time	97071100 ps
CPU time	31.23 seconds
Started	Aug 10 07:37:12 PM PDT 24
Finished	Aug 10 07:37:44 PM PDT 24
Peak memory	274336 kb
Host	smart-6abdecaf-a66a-4ed8-9114-9cd40f0fcc15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524338920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.3524338920
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.1714396621
Short name	T608
Test name
Test status
Simulation time	503784700 ps
CPU time	112.38 seconds
Started	Aug 10 07:37:17 PM PDT 24
Finished	Aug 10 07:39:10 PM PDT 24
Peak memory	290788 kb
Host	smart-3d77d5a9-8610-45f5-93b8-3eb91dbe89f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714396621 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.flash_ctrl_ro.1714396621
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3801894973
Short name	T328
Test name
Test status
Simulation time	26237900 ps
CPU time	31.3 seconds
Started	Aug 10 07:37:16 PM PDT 24
Finished	Aug 10 07:37:47 PM PDT 24
Peak memory	276348 kb
Host	smart-348bd686-e9e0-4ad9-a9c1-5bb46df1aff0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801894973 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3801894973
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.3875116997
Short name	T988
Test name
Test status
Simulation time	2434319600 ps
CPU time	78.16 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:38:40 PM PDT 24
Peak memory	263752 kb
Host	smart-ccc49cd2-cb05-45a6-a41b-52b12b0e888e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875116997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3875116997
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.4158235542
Short name	T626
Test name
Test status
Simulation time	35111900 ps
CPU time	121.88 seconds
Started	Aug 10 07:37:08 PM PDT 24
Finished	Aug 10 07:39:10 PM PDT 24
Peak memory	278224 kb
Host	smart-0d055f73-6ae3-4e2c-96fb-3a5730a897ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158235542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.4158235542
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.4277755098
Short name	T814
Test name
Test status
Simulation time	2301910800 ps
CPU time	187.6 seconds
Started	Aug 10 07:37:13 PM PDT 24
Finished	Aug 10 07:40:20 PM PDT 24
Peak memory	265908 kb
Host	smart-c9b731bc-7703-4a74-9cde-bf5152a74cf9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277755098 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.4277755098
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.4261413707
Short name	T696
Test name
Test status
Simulation time	22574700 ps
CPU time	13.46 seconds
Started	Aug 10 07:37:44 PM PDT 24
Finished	Aug 10 07:37:58 PM PDT 24
Peak memory	283632 kb
Host	smart-dc4cf9bd-9315-49af-bd7c-06e7be5392ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261413707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.4261413707
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.3740553486
Short name	T465
Test name
Test status
Simulation time	43739800 ps
CPU time	20.63 seconds
Started	Aug 10 07:37:46 PM PDT 24
Finished	Aug 10 07:38:06 PM PDT 24
Peak memory	274292 kb
Host	smart-2b1437e4-6757-44c8-906f-117a071ff8e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740553486 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.3740553486
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1221862418
Short name	T944
Test name
Test status
Simulation time	10027971800 ps
CPU time	74.95 seconds
Started	Aug 10 07:37:44 PM PDT 24
Finished	Aug 10 07:38:59 PM PDT 24
Peak memory	301928 kb
Host	smart-688297a8-fea0-4abf-b6cb-e98a4f6d7d65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221862418 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1221862418
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.539361417
Short name	T588
Test name
Test status
Simulation time	51835300 ps
CPU time	13.38 seconds
Started	Aug 10 07:37:44 PM PDT 24
Finished	Aug 10 07:37:58 PM PDT 24
Peak memory	258856 kb
Host	smart-9d25f363-6422-4eba-94fc-a1b3f312aa33
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539361417 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.539361417
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.415993855
Short name	T607
Test name
Test status
Simulation time	160189208000 ps
CPU time	887.78 seconds
Started	Aug 10 07:37:30 PM PDT 24
Finished	Aug 10 07:52:18 PM PDT 24
Peak memory	264508 kb
Host	smart-9b491a2d-3f82-4425-8dff-f1e68f8043f2
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415993855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.flash_ctrl_hw_rma_reset.415993855
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.983025172
Short name	T1045
Test name
Test status
Simulation time	2177677100 ps
CPU time	150.13 seconds
Started	Aug 10 07:37:28 PM PDT 24
Finished	Aug 10 07:39:59 PM PDT 24
Peak memory	263432 kb
Host	smart-57c6d0ab-af90-43ed-953a-0d2ac9aadd7b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983025172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h w_sec_otp.983025172
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.103501138
Short name	T262
Test name
Test status
Simulation time	1272636400 ps
CPU time	127.01 seconds
Started	Aug 10 07:37:37 PM PDT 24
Finished	Aug 10 07:39:44 PM PDT 24
Peak memory	286176 kb
Host	smart-d08c2c47-5abb-4270-99af-af726f0b9c96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103501138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_intr_rd.103501138
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.441528966
Short name	T1065
Test name
Test status
Simulation time	12259869200 ps
CPU time	282.6 seconds
Started	Aug 10 07:37:37 PM PDT 24
Finished	Aug 10 07:42:20 PM PDT 24
Peak memory	285652 kb
Host	smart-3557bf85-0c17-4879-940f-ccadac8facf6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441528966 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.441528966
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.2697391887
Short name	T964
Test name
Test status
Simulation time	1946989500 ps
CPU time	79.78 seconds
Started	Aug 10 07:37:29 PM PDT 24
Finished	Aug 10 07:38:49 PM PDT 24
Peak memory	264132 kb
Host	smart-ae923be1-6ef7-4b78-802b-822bd24809d4
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697391887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2 697391887
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.713109933
Short name	T525
Test name
Test status
Simulation time	16875268500 ps
CPU time	171.27 seconds
Started	Aug 10 07:37:29 PM PDT 24
Finished	Aug 10 07:40:20 PM PDT 24
Peak memory	265772 kb
Host	smart-8fa9a1fd-5395-4746-a479-90d8766ecce5
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713109933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.713109933
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.3536860267
Short name	T214
Test name
Test status
Simulation time	121845500 ps
CPU time	242.14 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:41:25 PM PDT 24
Peak memory	263756 kb
Host	smart-e82caca7-da9a-48f5-9c6d-c9017e201c51
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3536860267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3536860267
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.1298773986
Short name	T671
Test name
Test status
Simulation time	8094873500 ps
CPU time	166.76 seconds
Started	Aug 10 07:37:36 PM PDT 24
Finished	Aug 10 07:40:23 PM PDT 24
Peak memory	265852 kb
Host	smart-c6a54382-c197-455e-98e0-387e41b7176c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298773986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.1298773986
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.3862133216
Short name	T759
Test name
Test status
Simulation time	72878500 ps
CPU time	475.76 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:45:18 PM PDT 24
Peak memory	283024 kb
Host	smart-69d276fa-afc7-455b-95dc-294813cdd239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862133216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3862133216
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.3466092720
Short name	T152
Test name
Test status
Simulation time	207737400 ps
CPU time	34.93 seconds
Started	Aug 10 07:37:44 PM PDT 24
Finished	Aug 10 07:38:19 PM PDT 24
Peak memory	274244 kb
Host	smart-45732c8e-009c-465c-a688-09d6b6f0fe37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466092720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_re_evict.3466092720
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.2617458127
Short name	T456
Test name
Test status
Simulation time	4374452200 ps
CPU time	140.88 seconds
Started	Aug 10 07:37:37 PM PDT 24
Finished	Aug 10 07:39:58 PM PDT 24
Peak memory	290732 kb
Host	smart-b5731878-bd12-4d48-9173-aa60af795d54
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617458127 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.2617458127
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.3399716165
Short name	T150
Test name
Test status
Simulation time	14990791100 ps
CPU time	496.67 seconds
Started	Aug 10 07:37:37 PM PDT 24
Finished	Aug 10 07:45:54 PM PDT 24
Peak memory	319692 kb
Host	smart-58555281-f377-4338-8f00-0edc34c1cb2b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399716165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.3399716165
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1744448616
Short name	T1077
Test name
Test status
Simulation time	44570000 ps
CPU time	30.76 seconds
Started	Aug 10 07:37:44 PM PDT 24
Finished	Aug 10 07:38:15 PM PDT 24
Peak memory	274180 kb
Host	smart-62bd412d-87be-48da-9740-a8daeec01d7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744448616 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1744448616
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.2617047453
Short name	T585
Test name
Test status
Simulation time	58140300 ps
CPU time	98.81 seconds
Started	Aug 10 07:37:22 PM PDT 24
Finished	Aug 10 07:39:01 PM PDT 24
Peak memory	276672 kb
Host	smart-a17672cc-9e5b-4412-a5dc-3da77e5607ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2617047453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2617047453
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.720271363
Short name	T951
Test name
Test status
Simulation time	2703862700 ps
CPU time	215.7 seconds
Started	Aug 10 07:37:30 PM PDT 24
Finished	Aug 10 07:41:06 PM PDT 24
Peak memory	265864 kb
Host	smart-5a0e736e-7c85-4856-b800-4261656dfbd9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720271363 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 11.flash_ctrl_wo.720271363
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.3573473339
Short name	T681
Test name
Test status
Simulation time	39687500 ps
CPU time	13.71 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:38:12 PM PDT 24
Peak memory	258876 kb
Host	smart-47145fc3-eeca-4967-be80-546b7a049066
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573473339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test. 3573473339
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.4100721433
Short name	T1063
Test name
Test status
Simulation time	26842700 ps
CPU time	13.92 seconds
Started	Aug 10 07:38:00 PM PDT 24
Finished	Aug 10 07:38:14 PM PDT 24
Peak memory	259096 kb
Host	smart-3bcc46a2-fd71-475a-8427-372d5f213647
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100721433 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.4100721433
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1304066601
Short name	T522
Test name
Test status
Simulation time	40129684400 ps
CPU time	881.29 seconds
Started	Aug 10 07:37:52 PM PDT 24
Finished	Aug 10 07:52:33 PM PDT 24
Peak memory	261452 kb
Host	smart-ff2cf5ba-4719-4e70-afd3-558ac7ad9c87
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304066601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 12.flash_ctrl_hw_rma_reset.1304066601
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.980736973
Short name	T117
Test name
Test status
Simulation time	1817571700 ps
CPU time	162.49 seconds
Started	Aug 10 07:37:52 PM PDT 24
Finished	Aug 10 07:40:35 PM PDT 24
Peak memory	261596 kb
Host	smart-507ef912-db85-4de1-b445-5a8a393e220f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980736973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h w_sec_otp.980736973
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.235177003
Short name	T1089
Test name
Test status
Simulation time	9491299100 ps
CPU time	211.22 seconds
Started	Aug 10 07:37:53 PM PDT 24
Finished	Aug 10 07:41:24 PM PDT 24
Peak memory	291624 kb
Host	smart-b222e71c-c5a1-4a1c-8f9b-7cf973f576c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235177003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas h_ctrl_intr_rd.235177003
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.3083950035
Short name	T520
Test name
Test status
Simulation time	1003073100 ps
CPU time	88.69 seconds
Started	Aug 10 07:37:52 PM PDT 24
Finished	Aug 10 07:39:21 PM PDT 24
Peak memory	261328 kb
Host	smart-44f750cd-ba23-49ee-bd71-4472ed86be2f
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083950035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3 083950035
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.103754576
Short name	T445
Test name
Test status
Simulation time	74981400 ps
CPU time	13.47 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:38:11 PM PDT 24
Peak memory	260752 kb
Host	smart-797ef2a0-ef08-410d-a546-96398a2c8ea0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103754576 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.103754576
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.2256894621
Short name	T921
Test name
Test status
Simulation time	8402623000 ps
CPU time	526.15 seconds
Started	Aug 10 07:37:51 PM PDT 24
Finished	Aug 10 07:46:37 PM PDT 24
Peak memory	275816 kb
Host	smart-b2e75fa6-d5bb-46d2-b114-09a3da962c57
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256894621 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.2256894621
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.1548367277
Short name	T1104
Test name
Test status
Simulation time	37705000 ps
CPU time	131.67 seconds
Started	Aug 10 07:37:53 PM PDT 24
Finished	Aug 10 07:40:05 PM PDT 24
Peak memory	261612 kb
Host	smart-c531443f-a4e7-4ce7-a6dd-fa587c7f035c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548367277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.1548367277
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.1453077741
Short name	T896
Test name
Test status
Simulation time	169712700 ps
CPU time	198.62 seconds
Started	Aug 10 07:37:53 PM PDT 24
Finished	Aug 10 07:41:12 PM PDT 24
Peak memory	263828 kb
Host	smart-2cb63635-3479-4d37-88b4-9c5b433811cc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1453077741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1453077741
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.2456766294
Short name	T957
Test name
Test status
Simulation time	717980800 ps
CPU time	20.01 seconds
Started	Aug 10 07:37:51 PM PDT 24
Finished	Aug 10 07:38:11 PM PDT 24
Peak memory	260708 kb
Host	smart-19fd7a18-9f8b-4851-b636-cc99a438e235
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456766294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.2456766294
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.1165223528
Short name	T726
Test name
Test status
Simulation time	188578300 ps
CPU time	936.8 seconds
Started	Aug 10 07:37:45 PM PDT 24
Finished	Aug 10 07:53:22 PM PDT 24
Peak memory	287524 kb
Host	smart-3d66cb95-c5d2-4e44-93a3-1d19385db6ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165223528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.1165223528
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.495039236
Short name	T729
Test name
Test status
Simulation time	226724300 ps
CPU time	32.84 seconds
Started	Aug 10 07:37:59 PM PDT 24
Finished	Aug 10 07:38:32 PM PDT 24
Peak memory	278384 kb
Host	smart-1bf2d2aa-73ef-4b8a-b722-15b14f3c6533
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495039236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_re_evict.495039236
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.2316709566
Short name	T747
Test name
Test status
Simulation time	641593300 ps
CPU time	143.43 seconds
Started	Aug 10 07:37:51 PM PDT 24
Finished	Aug 10 07:40:14 PM PDT 24
Peak memory	290716 kb
Host	smart-eaff8dd2-6714-4027-b621-abcd978bc55d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316709566 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_ro.2316709566
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.1059520283
Short name	T587
Test name
Test status
Simulation time	4797589400 ps
CPU time	632.92 seconds
Started	Aug 10 07:37:52 PM PDT 24
Finished	Aug 10 07:48:25 PM PDT 24
Peak memory	310300 kb
Host	smart-262ebff8-38ba-4b7c-ab51-b425f0e85e5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059520283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.flash_ctrl_rw.1059520283
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.3756210123
Short name	T940
Test name
Test status
Simulation time	63963100 ps
CPU time	31.2 seconds
Started	Aug 10 07:38:00 PM PDT 24
Finished	Aug 10 07:38:31 PM PDT 24
Peak memory	274288 kb
Host	smart-df4a08ac-1285-43c7-9ad5-bb1b76d833c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756210123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.3756210123
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2772770971
Short name	T1021
Test name
Test status
Simulation time	29241300 ps
CPU time	29.36 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:38:28 PM PDT 24
Peak memory	274332 kb
Host	smart-72d58e4f-3baa-4098-90e4-7007e83d02b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772770971 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2772770971
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.265720500
Short name	T1092
Test name
Test status
Simulation time	803631200 ps
CPU time	70.58 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:39:09 PM PDT 24
Peak memory	264440 kb
Host	smart-8766b295-4ae3-43fd-8866-19b90535db37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265720500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.265720500
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.2735828572
Short name	T490
Test name
Test status
Simulation time	204929800 ps
CPU time	124.17 seconds
Started	Aug 10 07:37:44 PM PDT 24
Finished	Aug 10 07:39:48 PM PDT 24
Peak memory	277256 kb
Host	smart-e457ee09-b267-401d-a51d-5e5117fd8d4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735828572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2735828572
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.4055453074
Short name	T543
Test name
Test status
Simulation time	22424867500 ps
CPU time	202.26 seconds
Started	Aug 10 07:37:52 PM PDT 24
Finished	Aug 10 07:41:15 PM PDT 24
Peak memory	265788 kb
Host	smart-d5721817-47f5-4f08-a11f-54ddcbf20eb0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055453074 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.flash_ctrl_wo.4055453074
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.4118885029
Short name	T461
Test name
Test status
Simulation time	26257400 ps
CPU time	13.68 seconds
Started	Aug 10 07:38:12 PM PDT 24
Finished	Aug 10 07:38:26 PM PDT 24
Peak memory	265768 kb
Host	smart-45f97366-9b0d-4ff5-a7be-1ac5173eca35
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118885029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 4118885029
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.1871331046
Short name	T1110
Test name
Test status
Simulation time	41707600 ps
CPU time	13.57 seconds
Started	Aug 10 07:38:13 PM PDT 24
Finished	Aug 10 07:38:27 PM PDT 24
Peak memory	283712 kb
Host	smart-f225b776-2780-4671-84e6-46d2b2fbcc54
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871331046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1871331046
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.103180233
Short name	T352
Test name
Test status
Simulation time	22643500 ps
CPU time	21.64 seconds
Started	Aug 10 07:38:13 PM PDT 24
Finished	Aug 10 07:38:35 PM PDT 24
Peak memory	274212 kb
Host	smart-aa63c331-049f-46b7-ac17-ca663575a76f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103180233 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.103180233
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1235353805
Short name	T1093
Test name
Test status
Simulation time	10034496100 ps
CPU time	53.03 seconds
Started	Aug 10 07:38:14 PM PDT 24
Finished	Aug 10 07:39:07 PM PDT 24
Peak memory	287080 kb
Host	smart-2df3e7ec-5876-4a08-8631-78897203e2a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235353805 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1235353805
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2744987615
Short name	T430
Test name
Test status
Simulation time	9697205300 ps
CPU time	77.03 seconds
Started	Aug 10 07:38:04 PM PDT 24
Finished	Aug 10 07:39:22 PM PDT 24
Peak memory	261276 kb
Host	smart-b5b671bf-308d-4566-b213-00a3b11260a2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744987615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.2744987615
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.2989576901
Short name	T259
Test name
Test status
Simulation time	13450673400 ps
CPU time	219.7 seconds
Started	Aug 10 07:38:17 PM PDT 24
Finished	Aug 10 07:41:56 PM PDT 24
Peak memory	295056 kb
Host	smart-673229ad-76be-4352-b93c-95b7d53891e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989576901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.2989576901
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.371908199
Short name	T591
Test name
Test status
Simulation time	50828105900 ps
CPU time	325.74 seconds
Started	Aug 10 07:38:12 PM PDT 24
Finished	Aug 10 07:43:38 PM PDT 24
Peak memory	285784 kb
Host	smart-9966938a-1456-4986-b9af-583a7be50c25
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371908199 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.371908199
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3844597442
Short name	T721
Test name
Test status
Simulation time	15523800 ps
CPU time	13.66 seconds
Started	Aug 10 07:38:16 PM PDT 24
Finished	Aug 10 07:38:30 PM PDT 24
Peak memory	265412 kb
Host	smart-e709dc63-5e28-41ff-b818-7fda80bf8240
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844597442 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3844597442
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.2237003475
Short name	T157
Test name
Test status
Simulation time	23501881600 ps
CPU time	282.98 seconds
Started	Aug 10 07:38:06 PM PDT 24
Finished	Aug 10 07:42:49 PM PDT 24
Peak memory	274044 kb
Host	smart-55f9b95f-3bfb-457b-8f4a-da16fab830dd
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237003475 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.2237003475
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.4253340721
Short name	T1112
Test name
Test status
Simulation time	41198800 ps
CPU time	112.18 seconds
Started	Aug 10 07:38:05 PM PDT 24
Finished	Aug 10 07:39:57 PM PDT 24
Peak memory	265576 kb
Host	smart-c8fc567d-3700-4028-aa7d-143f989aed7e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253340721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.4253340721
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.2187369274
Short name	T783
Test name
Test status
Simulation time	164357700 ps
CPU time	110.68 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:39:49 PM PDT 24
Peak memory	262984 kb
Host	smart-a41394c9-d302-404c-93f4-8f431e2d7394
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2187369274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2187369274
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.1570613623
Short name	T1087
Test name
Test status
Simulation time	34646300 ps
CPU time	13.88 seconds
Started	Aug 10 07:38:13 PM PDT 24
Finished	Aug 10 07:38:27 PM PDT 24
Peak memory	259552 kb
Host	smart-a3f58970-5384-4783-b415-ac6602159e54
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570613623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.1570613623
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.1707488518
Short name	T533
Test name
Test status
Simulation time	829447400 ps
CPU time	871.12 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:52:30 PM PDT 24
Peak memory	286060 kb
Host	smart-cf7531ef-3993-4a0b-9dc8-dd5dfed03c6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707488518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1707488518
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.3499779499
Short name	T902
Test name
Test status
Simulation time	233449200 ps
CPU time	34.88 seconds
Started	Aug 10 07:38:12 PM PDT 24
Finished	Aug 10 07:38:47 PM PDT 24
Peak memory	278416 kb
Host	smart-990422b7-d079-45bc-a075-257b13b255b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499779499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.3499779499
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.3137661605
Short name	T919
Test name
Test status
Simulation time	507284200 ps
CPU time	123.34 seconds
Started	Aug 10 07:38:07 PM PDT 24
Finished	Aug 10 07:40:10 PM PDT 24
Peak memory	282496 kb
Host	smart-513da7e9-3220-497f-a7e8-fc3c7accf8c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137661605 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.3137661605
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3767641528
Short name	T694
Test name
Test status
Simulation time	66136200 ps
CPU time	31.35 seconds
Started	Aug 10 07:38:16 PM PDT 24
Finished	Aug 10 07:38:48 PM PDT 24
Peak memory	274308 kb
Host	smart-90114941-56aa-4570-bfe5-972f4358c8ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767641528 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.3767641528
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.762129420
Short name	T777
Test name
Test status
Simulation time	1267811000 ps
CPU time	62.87 seconds
Started	Aug 10 07:38:14 PM PDT 24
Finished	Aug 10 07:39:17 PM PDT 24
Peak memory	263288 kb
Host	smart-e9903dab-135c-46af-a630-22c6e4799ade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762129420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.762129420
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.3455990534
Short name	T1
Test name
Test status
Simulation time	44011400 ps
CPU time	124.02 seconds
Started	Aug 10 07:37:58 PM PDT 24
Finished	Aug 10 07:40:02 PM PDT 24
Peak memory	270516 kb
Host	smart-26d87b87-74fe-421d-b6e1-66eb2666b96e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455990534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3455990534
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.3903565992
Short name	T642
Test name
Test status
Simulation time	4150271400 ps
CPU time	153.01 seconds
Started	Aug 10 07:38:05 PM PDT 24
Finished	Aug 10 07:40:38 PM PDT 24
Peak memory	261636 kb
Host	smart-d4945e59-38d8-4f0b-9509-75d182cb837c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903565992 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.flash_ctrl_wo.3903565992
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.2408627842
Short name	T551
Test name
Test status
Simulation time	35126300 ps
CPU time	13.64 seconds
Started	Aug 10 07:38:26 PM PDT 24
Finished	Aug 10 07:38:40 PM PDT 24
Peak memory	258840 kb
Host	smart-3e7796ff-3e46-4045-a417-6d088794dd8e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408627842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 2408627842
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.2114579413
Short name	T1036
Test name
Test status
Simulation time	14089500 ps
CPU time	13.28 seconds
Started	Aug 10 07:38:31 PM PDT 24
Finished	Aug 10 07:38:44 PM PDT 24
Peak memory	283536 kb
Host	smart-4d3d2a3c-a329-493d-8042-89c1b0f900b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114579413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2114579413
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2594428432
Short name	T140
Test name
Test status
Simulation time	10062180400 ps
CPU time	41.25 seconds
Started	Aug 10 07:38:31 PM PDT 24
Finished	Aug 10 07:39:12 PM PDT 24
Peak memory	267488 kb
Host	smart-96791437-708a-48d9-9554-a7e32322a04a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594428432 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2594428432
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2064745853
Short name	T975
Test name
Test status
Simulation time	25702200 ps
CPU time	13.41 seconds
Started	Aug 10 07:38:28 PM PDT 24
Finished	Aug 10 07:38:41 PM PDT 24
Peak memory	259072 kb
Host	smart-022ecb2a-c51b-41a0-b4b7-2ff09c124816
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064745853 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2064745853
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1711162354
Short name	T1035
Test name
Test status
Simulation time	80138971500 ps
CPU time	852.51 seconds
Started	Aug 10 07:38:19 PM PDT 24
Finished	Aug 10 07:52:32 PM PDT 24
Peak memory	264808 kb
Host	smart-93f902aa-6498-46ad-9889-ec97208a75fe
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711162354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.1711162354
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.926119800
Short name	T871
Test name
Test status
Simulation time	2268473100 ps
CPU time	47.05 seconds
Started	Aug 10 07:38:23 PM PDT 24
Finished	Aug 10 07:39:10 PM PDT 24
Peak memory	261184 kb
Host	smart-d665e4cd-8241-41ef-8eea-695699e25863
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926119800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_h w_sec_otp.926119800
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.384656215
Short name	T604
Test name
Test status
Simulation time	7984373300 ps
CPU time	184.19 seconds
Started	Aug 10 07:38:20 PM PDT 24
Finished	Aug 10 07:41:25 PM PDT 24
Peak memory	291672 kb
Host	smart-69c85138-8726-42c0-9cef-f777a9882e09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384656215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas h_ctrl_intr_rd.384656215
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1098501687
Short name	T968
Test name
Test status
Simulation time	13327325300 ps
CPU time	300.97 seconds
Started	Aug 10 07:38:22 PM PDT 24
Finished	Aug 10 07:43:23 PM PDT 24
Peak memory	285356 kb
Host	smart-5cae31ef-c9ee-4393-9760-3b785aca1da3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098501687 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1098501687
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.4207453733
Short name	T482
Test name
Test status
Simulation time	9718677300 ps
CPU time	98.06 seconds
Started	Aug 10 07:38:22 PM PDT 24
Finished	Aug 10 07:40:00 PM PDT 24
Peak memory	261288 kb
Host	smart-29779897-52d1-4455-9c25-39d0d6a646e9
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207453733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.4 207453733
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1129220091
Short name	T537
Test name
Test status
Simulation time	19768400 ps
CPU time	13.49 seconds
Started	Aug 10 07:38:28 PM PDT 24
Finished	Aug 10 07:38:42 PM PDT 24
Peak memory	265404 kb
Host	smart-6251f8bf-3efb-4520-be48-dd82a1506938
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129220091 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.1129220091
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.2612678432
Short name	T544
Test name
Test status
Simulation time	1839132700 ps
CPU time	152.64 seconds
Started	Aug 10 07:38:20 PM PDT 24
Finished	Aug 10 07:40:53 PM PDT 24
Peak memory	265796 kb
Host	smart-2d627670-100c-48ca-9b12-f8586175b861
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612678432 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2612678432
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.1267713290
Short name	T480
Test name
Test status
Simulation time	42513000 ps
CPU time	133.27 seconds
Started	Aug 10 07:38:21 PM PDT 24
Finished	Aug 10 07:40:34 PM PDT 24
Peak memory	261584 kb
Host	smart-0c0739c2-2527-4edd-b642-3b331bb5a7a1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267713290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o tp_reset.1267713290
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.3214281835
Short name	T143
Test name
Test status
Simulation time	3666524500 ps
CPU time	680.67 seconds
Started	Aug 10 07:38:14 PM PDT 24
Finished	Aug 10 07:49:35 PM PDT 24
Peak memory	263876 kb
Host	smart-0de2e65c-b80d-482f-aecc-e70d8414c6c4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3214281835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3214281835
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.3360439110
Short name	T1074
Test name
Test status
Simulation time	19331700 ps
CPU time	13.54 seconds
Started	Aug 10 07:38:21 PM PDT 24
Finished	Aug 10 07:38:34 PM PDT 24
Peak memory	259468 kb
Host	smart-f0a723b5-0233-463c-a778-8d8194c15f76
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360439110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.3360439110
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.3450688036
Short name	T724
Test name
Test status
Simulation time	417608700 ps
CPU time	1210.03 seconds
Started	Aug 10 07:38:13 PM PDT 24
Finished	Aug 10 07:58:23 PM PDT 24
Peak memory	288120 kb
Host	smart-7e0fc0ee-cc66-4219-a68e-ee592797a77f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450688036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3450688036
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.3476026230
Short name	T331
Test name
Test status
Simulation time	67873700 ps
CPU time	34.72 seconds
Started	Aug 10 07:38:29 PM PDT 24
Finished	Aug 10 07:39:03 PM PDT 24
Peak memory	276336 kb
Host	smart-d9f415ed-a432-47f0-9dce-56124a6f52c5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476026230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_re_evict.3476026230
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.568661877
Short name	T519
Test name
Test status
Simulation time	573842500 ps
CPU time	123.57 seconds
Started	Aug 10 07:38:19 PM PDT 24
Finished	Aug 10 07:40:23 PM PDT 24
Peak memory	282456 kb
Host	smart-43664412-3cd0-4b66-a754-a73bcc436479
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568661877 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.flash_ctrl_ro.568661877
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.1623116354
Short name	T695
Test name
Test status
Simulation time	11289884200 ps
CPU time	415.96 seconds
Started	Aug 10 07:38:20 PM PDT 24
Finished	Aug 10 07:45:16 PM PDT 24
Peak memory	321060 kb
Host	smart-0c374a1a-25f1-4ab6-8606-04c3c1c4b544
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623116354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.flash_ctrl_rw.1623116354
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3827234200
Short name	T827
Test name
Test status
Simulation time	41054900 ps
CPU time	31.21 seconds
Started	Aug 10 07:38:21 PM PDT 24
Finished	Aug 10 07:38:52 PM PDT 24
Peak memory	274260 kb
Host	smart-a8fda1de-4373-45f4-9719-097d4560607d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827234200 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3827234200
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.2694236757
Short name	T846
Test name
Test status
Simulation time	108453800 ps
CPU time	76.86 seconds
Started	Aug 10 07:38:16 PM PDT 24
Finished	Aug 10 07:39:33 PM PDT 24
Peak memory	276228 kb
Host	smart-17b06531-b892-4cbe-9b50-6565114d04bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694236757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.2694236757
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.3419125438
Short name	T542
Test name
Test status
Simulation time	4357715500 ps
CPU time	204.79 seconds
Started	Aug 10 07:38:22 PM PDT 24
Finished	Aug 10 07:41:46 PM PDT 24
Peak memory	265320 kb
Host	smart-f1050a22-7162-48e8-b469-36ce5a325ce7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419125438 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.3419125438
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.1599982429
Short name	T852
Test name
Test status
Simulation time	98817100 ps
CPU time	14.31 seconds
Started	Aug 10 07:38:49 PM PDT 24
Finished	Aug 10 07:39:03 PM PDT 24
Peak memory	265704 kb
Host	smart-a7cc1158-f055-4683-8df4-e06223cc8918
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599982429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 1599982429
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.4092162812
Short name	T1068
Test name
Test status
Simulation time	96261300 ps
CPU time	15.94 seconds
Started	Aug 10 07:38:46 PM PDT 24
Finished	Aug 10 07:39:02 PM PDT 24
Peak memory	283656 kb
Host	smart-0d856cb3-563e-4fe1-be2a-1033f89c6963
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092162812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.4092162812
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2517262151
Short name	T177
Test name
Test status
Simulation time	10036231700 ps
CPU time	52.44 seconds
Started	Aug 10 07:38:45 PM PDT 24
Finished	Aug 10 07:39:37 PM PDT 24
Peak memory	278340 kb
Host	smart-fdf46ffe-e551-464e-8935-d2380adb9d87
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517262151 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2517262151
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.860773691
Short name	T617
Test name
Test status
Simulation time	20881700 ps
CPU time	13.39 seconds
Started	Aug 10 07:38:45 PM PDT 24
Finished	Aug 10 07:38:59 PM PDT 24
Peak memory	260616 kb
Host	smart-65e5dd3c-f72c-4ba2-9538-377ac9b6e98f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860773691 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.860773691
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.3420964483
Short name	T612
Test name
Test status
Simulation time	80137345000 ps
CPU time	856.3 seconds
Started	Aug 10 07:38:35 PM PDT 24
Finished	Aug 10 07:52:52 PM PDT 24
Peak memory	264868 kb
Host	smart-5faa5185-ea56-4525-ad80-8172f66d19ff
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420964483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.flash_ctrl_hw_rma_reset.3420964483
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.3336732309
Short name	T1066
Test name
Test status
Simulation time	4364844600 ps
CPU time	120.28 seconds
Started	Aug 10 07:38:33 PM PDT 24
Finished	Aug 10 07:40:34 PM PDT 24
Peak memory	262372 kb
Host	smart-52c4a331-6ea9-4b35-af14-e1afa6569d09
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336732309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ hw_sec_otp.3336732309
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.3029493211
Short name	T497
Test name
Test status
Simulation time	1404659500 ps
CPU time	141.84 seconds
Started	Aug 10 07:38:34 PM PDT 24
Finished	Aug 10 07:40:56 PM PDT 24
Peak memory	295060 kb
Host	smart-44d2bc72-3c8b-4b08-8c58-1fe19a9cb0c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029493211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.3029493211
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3327459926
Short name	T1116
Test name
Test status
Simulation time	5664431700 ps
CPU time	142.07 seconds
Started	Aug 10 07:38:40 PM PDT 24
Finished	Aug 10 07:41:02 PM PDT 24
Peak memory	293832 kb
Host	smart-9d33e361-d4c7-46c1-a746-452860ee39e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327459926 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.3327459926
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.3332129208
Short name	T898
Test name
Test status
Simulation time	1697303100 ps
CPU time	68.36 seconds
Started	Aug 10 07:38:34 PM PDT 24
Finished	Aug 10 07:39:42 PM PDT 24
Peak memory	261216 kb
Host	smart-725c3551-e640-444b-9afb-670a0332c206
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332129208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3 332129208
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.1420889532
Short name	T836
Test name
Test status
Simulation time	1666876700 ps
CPU time	145.9 seconds
Started	Aug 10 07:38:33 PM PDT 24
Finished	Aug 10 07:40:59 PM PDT 24
Peak memory	264036 kb
Host	smart-c325543f-d550-4095-a70c-8e4e04574b74
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420889532 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1420889532
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.337807689
Short name	T95
Test name
Test status
Simulation time	128105900 ps
CPU time	130.96 seconds
Started	Aug 10 07:38:34 PM PDT 24
Finished	Aug 10 07:40:45 PM PDT 24
Peak memory	259920 kb
Host	smart-e480a7a7-847c-4d23-a3a6-c31a7f6246fd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337807689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot p_reset.337807689
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.845033821
Short name	T855
Test name
Test status
Simulation time	2930924700 ps
CPU time	344.46 seconds
Started	Aug 10 07:38:34 PM PDT 24
Finished	Aug 10 07:44:19 PM PDT 24
Peak memory	263848 kb
Host	smart-1ca2fde2-beb5-4a69-8f0d-f3e4952cca3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=845033821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.845033821
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.1183774636
Short name	T606
Test name
Test status
Simulation time	185691900 ps
CPU time	13.71 seconds
Started	Aug 10 07:38:40 PM PDT 24
Finished	Aug 10 07:38:54 PM PDT 24
Peak memory	265720 kb
Host	smart-3ca57f86-24ca-480c-805a-b46163f7be54
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183774636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.flash_ctrl_prog_reset.1183774636
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.3728551020
Short name	T77
Test name
Test status
Simulation time	9040704200 ps
CPU time	1830.88 seconds
Started	Aug 10 07:38:31 PM PDT 24
Finished	Aug 10 08:09:02 PM PDT 24
Peak memory	291252 kb
Host	smart-6c19f0ad-69f7-4f66-9d02-3b1bb4926c02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728551020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3728551020
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.1364828192
Short name	T1099
Test name
Test status
Simulation time	197236200 ps
CPU time	35.95 seconds
Started	Aug 10 07:38:40 PM PDT 24
Finished	Aug 10 07:39:16 PM PDT 24
Peak memory	274308 kb
Host	smart-6b19f567-a2aa-43a1-876a-195f2bcd0053
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364828192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.1364828192
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.4213301367
Short name	T6
Test name
Test status
Simulation time	5597290800 ps
CPU time	114.87 seconds
Started	Aug 10 07:38:34 PM PDT 24
Finished	Aug 10 07:40:29 PM PDT 24
Peak memory	290788 kb
Host	smart-d099d706-cbc7-4d9f-923c-6f5804cca9d4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213301367 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.flash_ctrl_ro.4213301367
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.1916174416
Short name	T547
Test name
Test status
Simulation time	3504968700 ps
CPU time	500.04 seconds
Started	Aug 10 07:38:34 PM PDT 24
Finished	Aug 10 07:46:54 PM PDT 24
Peak memory	319840 kb
Host	smart-d1a12314-081a-4350-92ab-a76aae80d8aa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916174416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.1916174416
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.3965208593
Short name	T648
Test name
Test status
Simulation time	28450400 ps
CPU time	29.15 seconds
Started	Aug 10 07:38:40 PM PDT 24
Finished	Aug 10 07:39:09 PM PDT 24
Peak memory	274356 kb
Host	smart-951a9a6d-2458-42bc-976e-0a10d8bb770d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965208593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_rw_evict.3965208593
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1896723062
Short name	T801
Test name
Test status
Simulation time	70352900 ps
CPU time	30.5 seconds
Started	Aug 10 07:38:40 PM PDT 24
Finished	Aug 10 07:39:11 PM PDT 24
Peak memory	274348 kb
Host	smart-38c666bc-17c8-4494-8897-847a201850b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896723062 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1896723062
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.2677391314
Short name	T823
Test name
Test status
Simulation time	6144495700 ps
CPU time	78.54 seconds
Started	Aug 10 07:38:45 PM PDT 24
Finished	Aug 10 07:40:04 PM PDT 24
Peak memory	264436 kb
Host	smart-4f67fcdf-6a88-4ee2-900c-aef0844de303
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677391314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2677391314
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.3292588259
Short name	T492
Test name
Test status
Simulation time	360239300 ps
CPU time	217.17 seconds
Started	Aug 10 07:38:27 PM PDT 24
Finished	Aug 10 07:42:05 PM PDT 24
Peak memory	278484 kb
Host	smart-620b8079-d74d-4efb-82af-d8156d02ef1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292588259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3292588259
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.182764802
Short name	T808
Test name
Test status
Simulation time	14794610600 ps
CPU time	210.5 seconds
Started	Aug 10 07:38:35 PM PDT 24
Finished	Aug 10 07:42:05 PM PDT 24
Peak memory	265896 kb
Host	smart-2126ccf8-2c3b-4339-90b9-91ec10110d7e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182764802 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 15.flash_ctrl_wo.182764802
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.27224439
Short name	T419
Test name
Test status
Simulation time	248832600 ps
CPU time	14.01 seconds
Started	Aug 10 07:39:00 PM PDT 24
Finished	Aug 10 07:39:14 PM PDT 24
Peak memory	265692 kb
Host	smart-445ed1b7-52dd-4ffe-b60c-347a3fec2a68
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27224439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.27224439
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.2930912928
Short name	T495
Test name
Test status
Simulation time	145756200 ps
CPU time	13.44 seconds
Started	Aug 10 07:38:59 PM PDT 24
Finished	Aug 10 07:39:13 PM PDT 24
Peak memory	283504 kb
Host	smart-22e6053c-4f81-4b38-9786-55763e3b192c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930912928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2930912928
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3477864062
Short name	T178
Test name
Test status
Simulation time	10012876100 ps
CPU time	86.27 seconds
Started	Aug 10 07:38:59 PM PDT 24
Finished	Aug 10 07:40:25 PM PDT 24
Peak memory	265884 kb
Host	smart-81bcdb71-7eb1-444b-ae41-0db5924266df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477864062 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3477864062
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3542700053
Short name	T516
Test name
Test status
Simulation time	26722900 ps
CPU time	13.87 seconds
Started	Aug 10 07:39:02 PM PDT 24
Finished	Aug 10 07:39:16 PM PDT 24
Peak memory	258884 kb
Host	smart-4b15c700-9e66-4486-b77f-1e672c268c03
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542700053 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3542700053
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2933099070
Short name	T756
Test name
Test status
Simulation time	40126620300 ps
CPU time	865.38 seconds
Started	Aug 10 07:38:46 PM PDT 24
Finished	Aug 10 07:53:11 PM PDT 24
Peak memory	262828 kb
Host	smart-d64030fc-dbab-44e2-b926-e5d5d5e297ae
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933099070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.flash_ctrl_hw_rma_reset.2933099070
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.1997882316
Short name	T479
Test name
Test status
Simulation time	7444015900 ps
CPU time	122.02 seconds
Started	Aug 10 07:38:45 PM PDT 24
Finished	Aug 10 07:40:47 PM PDT 24
Peak memory	263416 kb
Host	smart-ea19f379-ded6-46b5-9dd0-d7d97112f335
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997882316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.1997882316
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.112285561
Short name	T941
Test name
Test status
Simulation time	1845712100 ps
CPU time	280.46 seconds
Started	Aug 10 07:38:52 PM PDT 24
Finished	Aug 10 07:43:33 PM PDT 24
Peak memory	285696 kb
Host	smart-d8c90cf2-643b-4b67-b1d8-fd42f5b4ed70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112285561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas h_ctrl_intr_rd.112285561
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3958636078
Short name	T937
Test name
Test status
Simulation time	5733592500 ps
CPU time	133.87 seconds
Started	Aug 10 07:38:52 PM PDT 24
Finished	Aug 10 07:41:06 PM PDT 24
Peak memory	293336 kb
Host	smart-cfe7ec4e-e43f-41ab-91e0-e51523c1246d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958636078 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3958636078
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.2798968973
Short name	T838
Test name
Test status
Simulation time	6941409800 ps
CPU time	87.5 seconds
Started	Aug 10 07:38:52 PM PDT 24
Finished	Aug 10 07:40:20 PM PDT 24
Peak memory	261336 kb
Host	smart-1899d3e4-7c5c-4529-9622-0418c866b60a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798968973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2 798968973
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1301861896
Short name	T270
Test name
Test status
Simulation time	67492100 ps
CPU time	13.73 seconds
Started	Aug 10 07:38:58 PM PDT 24
Finished	Aug 10 07:39:12 PM PDT 24
Peak memory	265384 kb
Host	smart-aac50e00-eaad-4b09-a484-60af0aaa0297
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301861896 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1301861896
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.2905143061
Short name	T145
Test name
Test status
Simulation time	6558123600 ps
CPU time	531.76 seconds
Started	Aug 10 07:38:50 PM PDT 24
Finished	Aug 10 07:47:41 PM PDT 24
Peak memory	275028 kb
Host	smart-b1478a2b-e14a-4076-b7b2-7da1e1ba9de6
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905143061 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.2905143061
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.3187984042
Short name	T790
Test name
Test status
Simulation time	41445500 ps
CPU time	111.37 seconds
Started	Aug 10 07:38:46 PM PDT 24
Finished	Aug 10 07:40:37 PM PDT 24
Peak memory	260756 kb
Host	smart-dde37c50-4b0e-44b1-9768-42fb47b201b5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187984042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.3187984042
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.1220949134
Short name	T1106
Test name
Test status
Simulation time	90559800 ps
CPU time	439.49 seconds
Started	Aug 10 07:38:48 PM PDT 24
Finished	Aug 10 07:46:07 PM PDT 24
Peak memory	263780 kb
Host	smart-c0a11c19-d058-4782-87d4-e0dbb192a8b6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1220949134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.1220949134
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.3271477321
Short name	T618
Test name
Test status
Simulation time	85314800 ps
CPU time	13.94 seconds
Started	Aug 10 07:38:58 PM PDT 24
Finished	Aug 10 07:39:12 PM PDT 24
Peak memory	259972 kb
Host	smart-eba81a7a-e054-409d-8d07-82b377f97d75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271477321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.3271477321
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.319585378
Short name	T567
Test name
Test status
Simulation time	2329358600 ps
CPU time	1010.75 seconds
Started	Aug 10 07:38:47 PM PDT 24
Finished	Aug 10 07:55:38 PM PDT 24
Peak memory	287388 kb
Host	smart-1bc1b856-39eb-4e81-87a1-916d0027a7be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319585378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.319585378
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.380726528
Short name	T1026
Test name
Test status
Simulation time	254547500 ps
CPU time	35.53 seconds
Started	Aug 10 07:38:58 PM PDT 24
Finished	Aug 10 07:39:34 PM PDT 24
Peak memory	268212 kb
Host	smart-2dd1d9f8-e3a5-42f4-a989-90392baf9747
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380726528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_re_evict.380726528
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.416034653
Short name	T581
Test name
Test status
Simulation time	1023856700 ps
CPU time	105.61 seconds
Started	Aug 10 07:38:51 PM PDT 24
Finished	Aug 10 07:40:37 PM PDT 24
Peak memory	282456 kb
Host	smart-48adc3c8-37b0-4526-a3d7-d885b548a928
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416034653 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.flash_ctrl_ro.416034653
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.1313357190
Short name	T200
Test name
Test status
Simulation time	7277243400 ps
CPU time	638.56 seconds
Started	Aug 10 07:38:50 PM PDT 24
Finished	Aug 10 07:49:29 PM PDT 24
Peak memory	310364 kb
Host	smart-7a2be558-6865-4d57-928d-e5a7b90634c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313357190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.flash_ctrl_rw.1313357190
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2865285373
Short name	T326
Test name
Test status
Simulation time	200413300 ps
CPU time	27.73 seconds
Started	Aug 10 07:38:58 PM PDT 24
Finished	Aug 10 07:39:26 PM PDT 24
Peak memory	274260 kb
Host	smart-e93eb6d2-79fa-494e-80ae-e04ad9183778
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865285373 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2865285373
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.1982224633
Short name	T954
Test name
Test status
Simulation time	486570800 ps
CPU time	56.25 seconds
Started	Aug 10 07:38:59 PM PDT 24
Finished	Aug 10 07:39:55 PM PDT 24
Peak memory	265512 kb
Host	smart-1f8f7a70-b5ad-4601-84d6-37d36ab7b2a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982224633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1982224633
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.3813761033
Short name	T931
Test name
Test status
Simulation time	69254400 ps
CPU time	51.97 seconds
Started	Aug 10 07:38:47 PM PDT 24
Finished	Aug 10 07:39:39 PM PDT 24
Peak memory	271748 kb
Host	smart-5f531186-3ae3-4088-9cc0-bc5c0000221c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813761033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3813761033
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.2969326550
Short name	T609
Test name
Test status
Simulation time	46498626200 ps
CPU time	204.85 seconds
Started	Aug 10 07:38:53 PM PDT 24
Finished	Aug 10 07:42:17 PM PDT 24
Peak memory	265896 kb
Host	smart-1cbfd559-d172-4dff-a287-70ad8fe9a634
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969326550 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.2969326550
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.1164429217
Short name	T598
Test name
Test status
Simulation time	31123000 ps
CPU time	13.54 seconds
Started	Aug 10 07:39:17 PM PDT 24
Finished	Aug 10 07:39:31 PM PDT 24
Peak memory	258800 kb
Host	smart-47146768-9601-4d4b-a509-bd537b14806b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164429217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 1164429217
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.81391390
Short name	T708
Test name
Test status
Simulation time	22476800 ps
CPU time	16.05 seconds
Started	Aug 10 07:39:09 PM PDT 24
Finished	Aug 10 07:39:25 PM PDT 24
Peak memory	284920 kb
Host	smart-a50aa591-5d09-4296-af35-9645f7d99807
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81391390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.81391390
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.824802860
Short name	T102
Test name
Test status
Simulation time	10541000 ps
CPU time	21.71 seconds
Started	Aug 10 07:39:09 PM PDT 24
Finished	Aug 10 07:39:31 PM PDT 24
Peak memory	274224 kb
Host	smart-a4f130ed-4d8c-43d7-ba86-d1a7fa25f86c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824802860 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.824802860
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3622852090
Short name	T742
Test name
Test status
Simulation time	10011976300 ps
CPU time	122.08 seconds
Started	Aug 10 07:39:11 PM PDT 24
Finished	Aug 10 07:41:13 PM PDT 24
Peak memory	318380 kb
Host	smart-dd751adc-7bf8-4416-b439-853e6e386a47
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622852090 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3622852090
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3721033663
Short name	T621
Test name
Test status
Simulation time	18041000 ps
CPU time	13.45 seconds
Started	Aug 10 07:39:11 PM PDT 24
Finished	Aug 10 07:39:25 PM PDT 24
Peak memory	258884 kb
Host	smart-414ea3eb-61fe-4cdc-b0a1-aa0d2fa39508
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721033663 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3721033663
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.3113477110
Short name	T194
Test name
Test status
Simulation time	40121282100 ps
CPU time	800.98 seconds
Started	Aug 10 07:39:05 PM PDT 24
Finished	Aug 10 07:52:26 PM PDT 24
Peak memory	264764 kb
Host	smart-152e39d7-d724-4906-a563-256d7b532662
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113477110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.3113477110
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2042418952
Short name	T847
Test name
Test status
Simulation time	7103730000 ps
CPU time	130.12 seconds
Started	Aug 10 07:39:05 PM PDT 24
Finished	Aug 10 07:41:15 PM PDT 24
Peak memory	261200 kb
Host	smart-5b7274c7-c901-4936-9683-837c8f45fbd4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042418952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.2042418952
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.1168970900
Short name	T483
Test name
Test status
Simulation time	533709800 ps
CPU time	123.45 seconds
Started	Aug 10 07:39:05 PM PDT 24
Finished	Aug 10 07:41:08 PM PDT 24
Peak memory	292336 kb
Host	smart-e65d1769-4a9b-462d-8c26-df9af7e17ed1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168970900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_intr_rd.1168970900
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3163910000
Short name	T310
Test name
Test status
Simulation time	12885680000 ps
CPU time	283.61 seconds
Started	Aug 10 07:39:04 PM PDT 24
Finished	Aug 10 07:43:48 PM PDT 24
Peak memory	292784 kb
Host	smart-b69b7441-afe8-49f9-91b3-5d63a4df7be3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163910000 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3163910000
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.3053012191
Short name	T390
Test name
Test status
Simulation time	2146101500 ps
CPU time	67.82 seconds
Started	Aug 10 07:39:05 PM PDT 24
Finished	Aug 10 07:40:13 PM PDT 24
Peak memory	264388 kb
Host	smart-a2bb7009-7ac3-4151-a3fd-faf2c80e0a97
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053012191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3 053012191
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2567508929
Short name	T565
Test name
Test status
Simulation time	26784800 ps
CPU time	13.69 seconds
Started	Aug 10 07:39:11 PM PDT 24
Finished	Aug 10 07:39:25 PM PDT 24
Peak memory	260720 kb
Host	smart-04e163f8-dfc2-498c-9b5b-bfbfeffc30c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567508929 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2567508929
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.4165945292
Short name	T137
Test name
Test status
Simulation time	26049531200 ps
CPU time	414.78 seconds
Started	Aug 10 07:39:06 PM PDT 24
Finished	Aug 10 07:46:01 PM PDT 24
Peak memory	275396 kb
Host	smart-faef1c13-7c82-42cf-810e-9376f6b2e9a6
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165945292 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.4165945292
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.1086636932
Short name	T895
Test name
Test status
Simulation time	155036800 ps
CPU time	112.55 seconds
Started	Aug 10 07:39:04 PM PDT 24
Finished	Aug 10 07:40:57 PM PDT 24
Peak memory	263708 kb
Host	smart-42e47568-bf7d-4446-b083-111b6ba50e24
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1086636932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1086636932
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.4121934064
Short name	T260
Test name
Test status
Simulation time	2454823700 ps
CPU time	206 seconds
Started	Aug 10 07:39:04 PM PDT 24
Finished	Aug 10 07:42:30 PM PDT 24
Peak memory	265840 kb
Host	smart-425321dd-4981-4737-acb7-32a05936b2ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121934064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.4121934064
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.847175393
Short name	T949
Test name
Test status
Simulation time	552481000 ps
CPU time	447.12 seconds
Started	Aug 10 07:38:57 PM PDT 24
Finished	Aug 10 07:46:24 PM PDT 24
Peak memory	282004 kb
Host	smart-1f03020e-4a0a-47f5-b31e-0658421ef700
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847175393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.847175393
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.59574069
Short name	T440
Test name
Test status
Simulation time	217814500 ps
CPU time	35.4 seconds
Started	Aug 10 07:39:08 PM PDT 24
Finished	Aug 10 07:39:43 PM PDT 24
Peak memory	276684 kb
Host	smart-af7d4a59-3f09-4bf3-b49c-8a5394ef8c94
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59574069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_re_evict.59574069
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.3767549498
Short name	T558
Test name
Test status
Simulation time	1107651200 ps
CPU time	125.94 seconds
Started	Aug 10 07:39:06 PM PDT 24
Finished	Aug 10 07:41:13 PM PDT 24
Peak memory	290228 kb
Host	smart-cc662a57-51d5-4207-a1d7-caaf9adf0608
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767549498 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.flash_ctrl_ro.3767549498
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.4044848857
Short name	T203
Test name
Test status
Simulation time	7994443500 ps
CPU time	547.46 seconds
Started	Aug 10 07:39:06 PM PDT 24
Finished	Aug 10 07:48:14 PM PDT 24
Peak memory	314848 kb
Host	smart-e4d9a38f-796d-4f44-ac21-92cd40ed6a4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044848857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.flash_ctrl_rw.4044848857
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.4174545185
Short name	T327
Test name
Test status
Simulation time	40910300 ps
CPU time	31.74 seconds
Started	Aug 10 07:39:13 PM PDT 24
Finished	Aug 10 07:39:45 PM PDT 24
Peak memory	276376 kb
Host	smart-920cb59f-235d-47a5-a5a3-9760406b2aac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174545185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_rw_evict.4174545185
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2498069227
Short name	T1003
Test name
Test status
Simulation time	51768700 ps
CPU time	31.64 seconds
Started	Aug 10 07:39:11 PM PDT 24
Finished	Aug 10 07:39:43 PM PDT 24
Peak memory	276336 kb
Host	smart-f71c5704-d0e7-4d41-955a-1590fdfb808a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498069227 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2498069227
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.335727295
Short name	T595
Test name
Test status
Simulation time	4257421000 ps
CPU time	70.81 seconds
Started	Aug 10 07:39:10 PM PDT 24
Finished	Aug 10 07:40:21 PM PDT 24
Peak memory	264468 kb
Host	smart-cd535185-ef02-45a7-8811-6dc6bd84cef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335727295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.335727295
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.1991026391
Short name	T656
Test name
Test status
Simulation time	102592900 ps
CPU time	196.69 seconds
Started	Aug 10 07:38:59 PM PDT 24
Finished	Aug 10 07:42:16 PM PDT 24
Peak memory	273868 kb
Host	smart-f2ed943c-ccb2-4fd0-9ec3-893b275aa2dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991026391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1991026391
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.2580346009
Short name	T942
Test name
Test status
Simulation time	4454474500 ps
CPU time	141.03 seconds
Started	Aug 10 07:39:04 PM PDT 24
Finished	Aug 10 07:41:25 PM PDT 24
Peak memory	260584 kb
Host	smart-e37fa22c-61de-451d-889a-cea1d5510903
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580346009 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.flash_ctrl_wo.2580346009
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.2812346709
Short name	T718
Test name
Test status
Simulation time	102055800 ps
CPU time	13.7 seconds
Started	Aug 10 07:39:29 PM PDT 24
Finished	Aug 10 07:39:43 PM PDT 24
Peak memory	258784 kb
Host	smart-2b88504e-58f3-4b1c-895a-23fd6a7aa685
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812346709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 2812346709
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.1156923675
Short name	T760
Test name
Test status
Simulation time	25827800 ps
CPU time	15.87 seconds
Started	Aug 10 07:39:21 PM PDT 24
Finished	Aug 10 07:39:37 PM PDT 24
Peak memory	284920 kb
Host	smart-1765d042-64bd-4906-a7ba-1f8ce796104a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156923675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1156923675
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.615155654
Short name	T970
Test name
Test status
Simulation time	10138139600 ps
CPU time	42.11 seconds
Started	Aug 10 07:39:28 PM PDT 24
Finished	Aug 10 07:40:10 PM PDT 24
Peak memory	265864 kb
Host	smart-1d2123c4-4310-4ddc-9ea3-177520ccf998
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615155654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.615155654
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3637187705
Short name	T926
Test name
Test status
Simulation time	36326900 ps
CPU time	13.46 seconds
Started	Aug 10 07:39:28 PM PDT 24
Finished	Aug 10 07:39:42 PM PDT 24
Peak memory	260688 kb
Host	smart-1db7e245-e277-40bc-b364-b87ca289b97d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637187705 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3637187705
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3035202538
Short name	T127
Test name
Test status
Simulation time	190215967300 ps
CPU time	876.44 seconds
Started	Aug 10 07:39:17 PM PDT 24
Finished	Aug 10 07:53:54 PM PDT 24
Peak memory	261520 kb
Host	smart-a6028901-383e-45a5-a3be-374a6697a3b7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035202538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.3035202538
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2447106496
Short name	T792
Test name
Test status
Simulation time	7715278200 ps
CPU time	138.35 seconds
Started	Aug 10 07:39:20 PM PDT 24
Finished	Aug 10 07:41:38 PM PDT 24
Peak memory	261196 kb
Host	smart-32ae86df-e453-4cb3-b9a3-704aa1b7cdfc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447106496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ hw_sec_otp.2447106496
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.2765924085
Short name	T980
Test name
Test status
Simulation time	6431895900 ps
CPU time	189.85 seconds
Started	Aug 10 07:39:22 PM PDT 24
Finished	Aug 10 07:42:32 PM PDT 24
Peak memory	292276 kb
Host	smart-21e5bf9c-52e5-45e0-9c26-abe28f81d4c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765924085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_intr_rd.2765924085
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1234395326
Short name	T739
Test name
Test status
Simulation time	5784746800 ps
CPU time	132.58 seconds
Started	Aug 10 07:39:22 PM PDT 24
Finished	Aug 10 07:41:34 PM PDT 24
Peak memory	293920 kb
Host	smart-d74e2853-3786-49c4-93a1-1b45fd137f23
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234395326 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1234395326
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.3972011322
Short name	T155
Test name
Test status
Simulation time	18969026500 ps
CPU time	88.93 seconds
Started	Aug 10 07:39:19 PM PDT 24
Finished	Aug 10 07:40:48 PM PDT 24
Peak memory	263736 kb
Host	smart-c12a04ca-eb78-4ba6-adf1-cce21412e676
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972011322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3 972011322
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3288432004
Short name	T1103
Test name
Test status
Simulation time	36660600 ps
CPU time	13.37 seconds
Started	Aug 10 07:39:29 PM PDT 24
Finished	Aug 10 07:39:43 PM PDT 24
Peak memory	265336 kb
Host	smart-11ad81c0-497b-4cbf-92e4-fefe5fc70fe0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288432004 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3288432004
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.1170750286
Short name	T159
Test name
Test status
Simulation time	201878715500 ps
CPU time	306.76 seconds
Started	Aug 10 07:39:17 PM PDT 24
Finished	Aug 10 07:44:24 PM PDT 24
Peak memory	275336 kb
Host	smart-8613465a-9e5a-41b1-9127-1f681bdf4abb
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170750286 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.1170750286
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.1176456875
Short name	T768
Test name
Test status
Simulation time	47762200 ps
CPU time	131.11 seconds
Started	Aug 10 07:39:19 PM PDT 24
Finished	Aug 10 07:41:30 PM PDT 24
Peak memory	260524 kb
Host	smart-f061f7ba-c93d-4351-8b49-6cffa0f25c15
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176456875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.1176456875
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.3905932093
Short name	T498
Test name
Test status
Simulation time	6247680200 ps
CPU time	429.65 seconds
Started	Aug 10 07:39:17 PM PDT 24
Finished	Aug 10 07:46:26 PM PDT 24
Peak memory	263640 kb
Host	smart-24398450-527f-4f20-aae2-494f69531a10
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3905932093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3905932093
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.2689263641
Short name	T596
Test name
Test status
Simulation time	23605400 ps
CPU time	14.23 seconds
Started	Aug 10 07:39:24 PM PDT 24
Finished	Aug 10 07:39:38 PM PDT 24
Peak memory	265728 kb
Host	smart-23bd3637-b490-414b-8c01-aee5bc23dc8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689263641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.flash_ctrl_prog_reset.2689263641
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.4048840289
Short name	T90
Test name
Test status
Simulation time	28188300 ps
CPU time	128.97 seconds
Started	Aug 10 07:39:18 PM PDT 24
Finished	Aug 10 07:41:28 PM PDT 24
Peak memory	272676 kb
Host	smart-f2591f74-97e4-42ad-bc5a-639d9be3e38b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048840289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.4048840289
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.1660387625
Short name	T1007
Test name
Test status
Simulation time	92222400 ps
CPU time	34.86 seconds
Started	Aug 10 07:39:24 PM PDT 24
Finished	Aug 10 07:39:59 PM PDT 24
Peak memory	278396 kb
Host	smart-68e19ede-8951-4dce-b9c8-e9294d61535b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660387625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.1660387625
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.872394022
Short name	T204
Test name
Test status
Simulation time	584972900 ps
CPU time	106.95 seconds
Started	Aug 10 07:39:22 PM PDT 24
Finished	Aug 10 07:41:09 PM PDT 24
Peak memory	282384 kb
Host	smart-b9cdc685-d07a-48ea-ba35-38e81b97aadf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872394022 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.flash_ctrl_ro.872394022
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.2164408684
Short name	T624
Test name
Test status
Simulation time	39550805000 ps
CPU time	522.11 seconds
Started	Aug 10 07:39:25 PM PDT 24
Finished	Aug 10 07:48:07 PM PDT 24
Peak memory	310344 kb
Host	smart-d300ab68-7c79-4fc4-9136-b076a2215ad9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164408684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.2164408684
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.1189900005
Short name	T382
Test name
Test status
Simulation time	1827914400 ps
CPU time	81.85 seconds
Started	Aug 10 07:39:22 PM PDT 24
Finished	Aug 10 07:40:44 PM PDT 24
Peak memory	264164 kb
Host	smart-ccdde453-c7e8-465e-9df7-4878076f2789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189900005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1189900005
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.2667922293
Short name	T5
Test name
Test status
Simulation time	50786000 ps
CPU time	171.33 seconds
Started	Aug 10 07:39:18 PM PDT 24
Finished	Aug 10 07:42:10 PM PDT 24
Peak memory	277772 kb
Host	smart-e08285ce-dee2-43f4-ad19-cc60a0cb9252
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2667922293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2667922293
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.2634215303
Short name	T952
Test name
Test status
Simulation time	2389184100 ps
CPU time	180.64 seconds
Started	Aug 10 07:39:18 PM PDT 24
Finished	Aug 10 07:42:19 PM PDT 24
Peak memory	260672 kb
Host	smart-478870ca-da9f-4f29-b211-a81c096e6f79
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634215303 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.flash_ctrl_wo.2634215303
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.648265201
Short name	T489
Test name
Test status
Simulation time	81026100 ps
CPU time	13.39 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:39:52 PM PDT 24
Peak memory	265724 kb
Host	smart-a1ebcebd-548a-4fe4-bf5d-6e67e3927af6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648265201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.648265201
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.1535029831
Short name	T929
Test name
Test status
Simulation time	38185700 ps
CPU time	15.69 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:39:55 PM PDT 24
Peak memory	284908 kb
Host	smart-ef066850-533a-46c5-b20a-6dc5799ccd13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535029831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1535029831
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2848473061
Short name	T920
Test name
Test status
Simulation time	10019510800 ps
CPU time	80.42 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:40:59 PM PDT 24
Peak memory	291736 kb
Host	smart-c657b71d-015b-445f-a8f8-6cdc9dac8013
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848473061 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2848473061
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2008891143
Short name	T267
Test name
Test status
Simulation time	146936800 ps
CPU time	13.65 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:39:53 PM PDT 24
Peak memory	258956 kb
Host	smart-76777af5-687a-4e96-8b26-069ac94c3f5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008891143 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2008891143
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.1693918493
Short name	T1085
Test name
Test status
Simulation time	140173604300 ps
CPU time	860.17 seconds
Started	Aug 10 07:39:34 PM PDT 24
Finished	Aug 10 07:53:55 PM PDT 24
Peak memory	261428 kb
Host	smart-c2ae9776-d73a-4a13-bd0e-cad2efaf62d7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693918493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.1693918493
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2974895374
Short name	T400
Test name
Test status
Simulation time	11560873600 ps
CPU time	114.07 seconds
Started	Aug 10 07:39:34 PM PDT 24
Finished	Aug 10 07:41:28 PM PDT 24
Peak memory	263300 kb
Host	smart-f92f173d-11f4-47cb-9f7b-09b0af6b5544
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974895374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.2974895374
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.4283264692
Short name	T698
Test name
Test status
Simulation time	1439391000 ps
CPU time	146.43 seconds
Started	Aug 10 07:39:34 PM PDT 24
Finished	Aug 10 07:42:01 PM PDT 24
Peak memory	294972 kb
Host	smart-3f39ffc4-0e49-4c8c-b713-dca107946842
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283264692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.4283264692
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1269844940
Short name	T404
Test name
Test status
Simulation time	7056582900 ps
CPU time	129.92 seconds
Started	Aug 10 07:39:37 PM PDT 24
Finished	Aug 10 07:41:47 PM PDT 24
Peak memory	293524 kb
Host	smart-2d9df336-27a2-4ac2-a344-d268c9a2b105
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269844940 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1269844940
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.2467649572
Short name	T1051
Test name
Test status
Simulation time	4193771300 ps
CPU time	68.72 seconds
Started	Aug 10 07:39:37 PM PDT 24
Finished	Aug 10 07:40:46 PM PDT 24
Peak memory	261348 kb
Host	smart-66088567-c4ec-4186-a87e-318e4760a4a8
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467649572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2 467649572
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1866893524
Short name	T945
Test name
Test status
Simulation time	33187400 ps
CPU time	13.44 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:39:52 PM PDT 24
Peak memory	260808 kb
Host	smart-59907b0a-5782-40a7-bb22-5d19305614b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866893524 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1866893524
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.1373122432
Short name	T87
Test name
Test status
Simulation time	12781112900 ps
CPU time	405.76 seconds
Started	Aug 10 07:39:33 PM PDT 24
Finished	Aug 10 07:46:19 PM PDT 24
Peak memory	275140 kb
Host	smart-c0bfe2dd-9d04-4039-9d2c-0a6cc4a932cd
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373122432 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1373122432
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.1687786674
Short name	T1082
Test name
Test status
Simulation time	623288000 ps
CPU time	133.56 seconds
Started	Aug 10 07:39:33 PM PDT 24
Finished	Aug 10 07:41:47 PM PDT 24
Peak memory	260644 kb
Host	smart-a3277bc6-1b71-43a3-97eb-7227a4ed7d9e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687786674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o tp_reset.1687786674
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.1331912509
Short name	T974
Test name
Test status
Simulation time	65069200 ps
CPU time	112.08 seconds
Started	Aug 10 07:39:28 PM PDT 24
Finished	Aug 10 07:41:21 PM PDT 24
Peak memory	263700 kb
Host	smart-04b151de-bb39-420a-8fe0-b1b3f435964c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1331912509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1331912509
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.3888692487
Short name	T453
Test name
Test status
Simulation time	2563101600 ps
CPU time	207.66 seconds
Started	Aug 10 07:39:34 PM PDT 24
Finished	Aug 10 07:43:02 PM PDT 24
Peak memory	265744 kb
Host	smart-fa44afdb-ae00-4f8a-b40e-84ff023963f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888692487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.flash_ctrl_prog_reset.3888692487
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.1785803737
Short name	T658
Test name
Test status
Simulation time	1732689000 ps
CPU time	920.12 seconds
Started	Aug 10 07:39:29 PM PDT 24
Finished	Aug 10 07:54:50 PM PDT 24
Peak memory	287604 kb
Host	smart-1a44e94e-2563-4fe6-b723-598566a834fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785803737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1785803737
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.795805496
Short name	T1079
Test name
Test status
Simulation time	1419990200 ps
CPU time	125.6 seconds
Started	Aug 10 07:39:34 PM PDT 24
Finished	Aug 10 07:41:40 PM PDT 24
Peak memory	290708 kb
Host	smart-bc36b34d-492b-4125-badf-b4226b1ee9ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795805496 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.flash_ctrl_ro.795805496
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.593086005
Short name	T685
Test name
Test status
Simulation time	13266316500 ps
CPU time	552.83 seconds
Started	Aug 10 07:39:35 PM PDT 24
Finished	Aug 10 07:48:48 PM PDT 24
Peak memory	315364 kb
Host	smart-713ce277-eac3-4ff2-9bf1-dcd84b918fb7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593086005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.593086005
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.1427931444
Short name	T324
Test name
Test status
Simulation time	74599400 ps
CPU time	31.91 seconds
Started	Aug 10 07:39:33 PM PDT 24
Finished	Aug 10 07:40:05 PM PDT 24
Peak memory	274260 kb
Host	smart-4e685d7f-0da6-4a91-9b3f-efb0b6b2a435
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427931444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_rw_evict.1427931444
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3702102529
Short name	T841
Test name
Test status
Simulation time	35133300 ps
CPU time	31.23 seconds
Started	Aug 10 07:39:40 PM PDT 24
Finished	Aug 10 07:40:11 PM PDT 24
Peak memory	275608 kb
Host	smart-76dfdc74-a392-4dd8-a4a9-ce86f3c2824f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702102529 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3702102529
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.1452282706
Short name	T616
Test name
Test status
Simulation time	8257889500 ps
CPU time	72.38 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:40:52 PM PDT 24
Peak memory	264448 kb
Host	smart-85857e3d-c621-4746-8c8d-5a363c695335
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452282706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1452282706
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.1702704228
Short name	T887
Test name
Test status
Simulation time	185799800 ps
CPU time	125.39 seconds
Started	Aug 10 07:39:28 PM PDT 24
Finished	Aug 10 07:41:34 PM PDT 24
Peak memory	277008 kb
Host	smart-38059018-f9f9-4fb8-a36f-2a9983f36aee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702704228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1702704228
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.3701893432
Short name	T471
Test name
Test status
Simulation time	4161288400 ps
CPU time	211.92 seconds
Started	Aug 10 07:39:38 PM PDT 24
Finished	Aug 10 07:43:10 PM PDT 24
Peak memory	260056 kb
Host	smart-3f996873-75e4-4f97-8ee2-00305e2b370e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701893432 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.3701893432
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.2734190997
Short name	T22
Test name
Test status
Simulation time	107461400 ps
CPU time	13.75 seconds
Started	Aug 10 07:34:21 PM PDT 24
Finished	Aug 10 07:34:34 PM PDT 24
Peak memory	266168 kb
Host	smart-75ffa752-6348-428d-a804-83922287fc4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734190997 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2734190997
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.3080732740
Short name	T675
Test name
Test status
Simulation time	292327800 ps
CPU time	13.73 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 07:34:40 PM PDT 24
Peak memory	265732 kb
Host	smart-e3969ec1-8eab-49c0-ba17-437d4963fd0d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080732740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3 080732740
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.4074699460
Short name	T973
Test name
Test status
Simulation time	71602100 ps
CPU time	13.74 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:33 PM PDT 24
Peak memory	265312 kb
Host	smart-33f009ae-25e0-44a2-a1c0-bc319ad618ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074699460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.4074699460
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.4119292136
Short name	T680
Test name
Test status
Simulation time	58408500 ps
CPU time	15.86 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:35 PM PDT 24
Peak memory	285004 kb
Host	smart-643aab3d-ba05-475d-ab65-4060910bfc78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119292136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.4119292136
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.409942821
Short name	T730
Test name
Test status
Simulation time	10935300 ps
CPU time	21.9 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:41 PM PDT 24
Peak memory	274304 kb
Host	smart-d71777a2-7d8f-4096-a492-3d53e37ab3f2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409942821 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.409942821
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.2600894455
Short name	T58
Test name
Test status
Simulation time	93105000 ps
CPU time	235.82 seconds
Started	Aug 10 07:34:14 PM PDT 24
Finished	Aug 10 07:38:10 PM PDT 24
Peak memory	263916 kb
Host	smart-3fab493b-8e61-417b-9b3a-6c4c38ed6afe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2600894455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2600894455
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.3069474244
Short name	T146
Test name
Test status
Simulation time	17453424800 ps
CPU time	2273.85 seconds
Started	Aug 10 07:34:17 PM PDT 24
Finished	Aug 10 08:12:12 PM PDT 24
Peak memory	263400 kb
Host	smart-6850d72c-19de-43b7-8059-ba1f1b1826dd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3069474244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.3069474244
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.1126161163
Short name	T539
Test name
Test status
Simulation time	411656500 ps
CPU time	1970.24 seconds
Started	Aug 10 07:34:15 PM PDT 24
Finished	Aug 10 08:07:05 PM PDT 24
Peak memory	265012 kb
Host	smart-649dcd49-f264-44fb-b09c-636e17592451
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126161163 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1126161163
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.2141711912
Short name	T615
Test name
Test status
Simulation time	1393176400 ps
CPU time	929.22 seconds
Started	Aug 10 07:34:13 PM PDT 24
Finished	Aug 10 07:49:43 PM PDT 24
Peak memory	273268 kb
Host	smart-c6dd9fa3-8eb3-4272-a01a-f62842a24202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2141711912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2141711912
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.3143153977
Short name	T49
Test name
Test status
Simulation time	117912500 ps
CPU time	23.13 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:42 PM PDT 24
Peak memory	264128 kb
Host	smart-d5ee7dae-2fd1-4dbb-9d63-5914d769e99d
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143153977 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3143153977
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.3891664320
Short name	T105
Test name
Test status
Simulation time	691869800 ps
CPU time	39.11 seconds
Started	Aug 10 07:34:20 PM PDT 24
Finished	Aug 10 07:34:59 PM PDT 24
Peak memory	263624 kb
Host	smart-d0485b22-84cd-418a-acab-e152c3fd85c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891664320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.flash_ctrl_fs_sup.3891664320
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.634239221
Short name	T985
Test name
Test status
Simulation time	318011902100 ps
CPU time	2695.82 seconds
Started	Aug 10 07:34:15 PM PDT 24
Finished	Aug 10 08:19:11 PM PDT 24
Peak memory	265740 kb
Host	smart-ac67c2cf-47f2-4596-861b-35a857338734
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634239221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_full_mem_access.634239221
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.2264553615
Short name	T870
Test name
Test status
Simulation time	127841200 ps
CPU time	27.79 seconds
Started	Aug 10 07:34:20 PM PDT 24
Finished	Aug 10 07:34:48 PM PDT 24
Peak memory	267956 kb
Host	smart-69eeb46d-12f6-421f-aee0-b824ad780326
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264553615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_host_addr_infection.2264553615
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.3600268691
Short name	T258
Test name
Test status
Simulation time	194095100 ps
CPU time	125.51 seconds
Started	Aug 10 07:34:15 PM PDT 24
Finished	Aug 10 07:36:21 PM PDT 24
Peak memory	263332 kb
Host	smart-1b1ba3d7-aa04-4f0a-8cba-c255fb3bc333
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3600268691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3600268691
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3160814548
Short name	T195
Test name
Test status
Simulation time	10036491100 ps
CPU time	67.01 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:35:26 PM PDT 24
Peak memory	293840 kb
Host	smart-13744de8-8c19-4c53-a069-c08a72bbd5fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160814548 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3160814548
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3975449506
Short name	T313
Test name
Test status
Simulation time	206996800 ps
CPU time	13.56 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 07:34:32 PM PDT 24
Peak memory	260684 kb
Host	smart-867935fd-dad3-4924-b3bf-36d877d6b6fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975449506 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3975449506
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.3220734688
Short name	T100
Test name
Test status
Simulation time	85451921300 ps
CPU time	1867.24 seconds
Started	Aug 10 07:34:14 PM PDT 24
Finished	Aug 10 08:05:22 PM PDT 24
Peak memory	261180 kb
Host	smart-d5f10e21-dfb9-4beb-a6cc-ac2665b19c33
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220734688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_hw_rma.3220734688
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.113583943
Short name	T192
Test name
Test status
Simulation time	80141712400 ps
CPU time	870.06 seconds
Started	Aug 10 07:34:15 PM PDT 24
Finished	Aug 10 07:48:45 PM PDT 24
Peak memory	265020 kb
Host	smart-7609318b-e9fa-43ef-b970-59b46e1874b5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113583943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_hw_rma_reset.113583943
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1418457721
Short name	T589
Test name
Test status
Simulation time	3112788900 ps
CPU time	90.02 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:35:42 PM PDT 24
Peak memory	260616 kb
Host	smart-258a83f1-cec8-421e-b460-94699a82fae9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418457721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.1418457721
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.2179836103
Short name	T225
Test name
Test status
Simulation time	16076934300 ps
CPU time	633.54 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:44:52 PM PDT 24
Peak memory	337380 kb
Host	smart-aeada986-b226-47ba-9022-c41afa02bc95
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179836103 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.2179836103
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.2269004924
Short name	T38
Test name
Test status
Simulation time	651524000 ps
CPU time	128.06 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 07:36:35 PM PDT 24
Peak memory	286360 kb
Host	smart-37fda19b-7ae5-4a2e-97a4-40a96f4fb9ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269004924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_intr_rd.2269004924
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3887327681
Short name	T432
Test name
Test status
Simulation time	11906777900 ps
CPU time	117.76 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 07:36:23 PM PDT 24
Peak memory	293816 kb
Host	smart-40d6f73f-232e-429f-b6e9-1bed87decb80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887327681 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3887327681
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.528464970
Short name	T31
Test name
Test status
Simulation time	9291107100 ps
CPU time	65.32 seconds
Started	Aug 10 07:34:21 PM PDT 24
Finished	Aug 10 07:35:27 PM PDT 24
Peak memory	261192 kb
Host	smart-14991aa6-618c-441a-9629-2e1bb9de0993
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528464970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_intr_wr.528464970
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3426726827
Short name	T582
Test name
Test status
Simulation time	75337007300 ps
CPU time	237.16 seconds
Started	Aug 10 07:34:20 PM PDT 24
Finished	Aug 10 07:38:17 PM PDT 24
Peak memory	260864 kb
Host	smart-05480f29-566c-4d8e-92c4-edb69a71948c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342 6726827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3426726827
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.3607377281
Short name	T391
Test name
Test status
Simulation time	4378696400 ps
CPU time	80.77 seconds
Started	Aug 10 07:34:13 PM PDT 24
Finished	Aug 10 07:35:34 PM PDT 24
Peak memory	263956 kb
Host	smart-fc4ad94c-d150-4637-8287-0fa06730ae2a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607377281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3607377281
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3784129410
Short name	T955
Test name
Test status
Simulation time	31117900 ps
CPU time	13.42 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 07:34:39 PM PDT 24
Peak memory	265408 kb
Host	smart-f1db4b5b-41a7-411a-97fc-2f580e20c752
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784129410 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3784129410
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.3254450538
Short name	T88
Test name
Test status
Simulation time	930621300 ps
CPU time	71.96 seconds
Started	Aug 10 07:34:16 PM PDT 24
Finished	Aug 10 07:35:28 PM PDT 24
Peak memory	261344 kb
Host	smart-74d33840-404d-4bf1-8a4a-97fd095f7eea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254450538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3254450538
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.2986093156
Short name	T218
Test name
Test status
Simulation time	1583681700 ps
CPU time	144.51 seconds
Started	Aug 10 07:34:17 PM PDT 24
Finished	Aug 10 07:36:41 PM PDT 24
Peak memory	265776 kb
Host	smart-70a5afbb-e20f-4b32-8eca-47936d6f2dca
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986093156 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2986093156
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.155186403
Short name	T82
Test name
Test status
Simulation time	72779700 ps
CPU time	130.9 seconds
Started	Aug 10 07:34:14 PM PDT 24
Finished	Aug 10 07:36:25 PM PDT 24
Peak memory	264768 kb
Host	smart-cac75985-b6ad-47be-ae36-43dd9852487f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155186403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp _reset.155186403
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.2576857836
Short name	T1039
Test name
Test status
Simulation time	4709466500 ps
CPU time	164.94 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 07:37:03 PM PDT 24
Peak memory	282520 kb
Host	smart-0ed92a6f-4a56-4985-be85-e428226b849c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576857836 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2576857836
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.193945455
Short name	T61
Test name
Test status
Simulation time	25372800 ps
CPU time	14.04 seconds
Started	Aug 10 07:34:21 PM PDT 24
Finished	Aug 10 07:34:35 PM PDT 24
Peak memory	277764 kb
Host	smart-60f616f2-f4ef-4e6c-a541-dbb6dc976f15
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=193945455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.193945455
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.3719621274
Short name	T410
Test name
Test status
Simulation time	74593600 ps
CPU time	153.65 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 07:36:52 PM PDT 24
Peak memory	263300 kb
Host	smart-c8357dda-96c8-4662-8148-35f913bb12a4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3719621274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3719621274
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.4045731099
Short name	T201
Test name
Test status
Simulation time	15954000 ps
CPU time	14.29 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:33 PM PDT 24
Peak memory	263512 kb
Host	smart-8af59954-251f-45e8-b1f9-7dfbdcf96b99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045731099 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.4045731099
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.396264842
Short name	T508
Test name
Test status
Simulation time	5215618900 ps
CPU time	224.04 seconds
Started	Aug 10 07:34:20 PM PDT 24
Finished	Aug 10 07:38:05 PM PDT 24
Peak memory	265780 kb
Host	smart-61e3d2e6-dd63-403d-8f90-fec3d6f939b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396264842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_prog_reset.396264842
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.2508353460
Short name	T735
Test name
Test status
Simulation time	1258094200 ps
CPU time	918.92 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:49:38 PM PDT 24
Peak memory	284040 kb
Host	smart-edea047d-f35a-4324-b520-a897a66b8638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508353460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2508353460
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2058281289
Short name	T682
Test name
Test status
Simulation time	5634509000 ps
CPU time	204.43 seconds
Started	Aug 10 07:34:16 PM PDT 24
Finished	Aug 10 07:37:40 PM PDT 24
Peak memory	263468 kb
Host	smart-0c38fce6-63d1-4ac9-9f44-8abc79ca0119
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2058281289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2058281289
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.1766523236
Short name	T151
Test name
Test status
Simulation time	140655500 ps
CPU time	33.24 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:53 PM PDT 24
Peak memory	274364 kb
Host	smart-8805fa99-40fe-41c0-a57c-65683e0ef8c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766523236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_re_evict.1766523236
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.4002694397
Short name	T434
Test name
Test status
Simulation time	19146300 ps
CPU time	21.14 seconds
Started	Aug 10 07:34:17 PM PDT 24
Finished	Aug 10 07:34:38 PM PDT 24
Peak memory	265632 kb
Host	smart-7472122e-913c-44be-9a4a-c22ecaffbdf4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002694397 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.4002694397
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.1992925423
Short name	T634
Test name
Test status
Simulation time	119604400 ps
CPU time	22.83 seconds
Started	Aug 10 07:34:16 PM PDT 24
Finished	Aug 10 07:34:39 PM PDT 24
Peak memory	266012 kb
Host	smart-eb20de6b-48eb-460d-8ce4-a63ab9f87acd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992925423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.1992925423
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.2787445669
Short name	T175
Test name
Test status
Simulation time	787453170500 ps
CPU time	1270.8 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:55:30 PM PDT 24
Peak memory	262088 kb
Host	smart-11189202-f24b-4337-bbad-14d83940c4ea
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787445669 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2787445669
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.18960107
Short name	T207
Test name
Test status
Simulation time	549409700 ps
CPU time	138.66 seconds
Started	Aug 10 07:34:12 PM PDT 24
Finished	Aug 10 07:36:31 PM PDT 24
Peak memory	282572 kb
Host	smart-2d66c835-1130-4ab8-8de4-46b5b69a4069
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960107 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.flash_ctrl_ro.18960107
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.1581361266
Short name	T534
Test name
Test status
Simulation time	2454977300 ps
CPU time	136.58 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:36:36 PM PDT 24
Peak memory	282652 kb
Host	smart-ec517971-5d11-408c-8502-d06b7ccad97d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1581361266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1581361266
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.2246859909
Short name	T441
Test name
Test status
Simulation time	3090864900 ps
CPU time	175.64 seconds
Started	Aug 10 07:34:17 PM PDT 24
Finished	Aug 10 07:37:13 PM PDT 24
Peak memory	290708 kb
Host	smart-4aeb1bf8-28b6-41b7-a354-13a1a417fabb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246859909 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2246859909
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.2127818000
Short name	T1000
Test name
Test status
Simulation time	7066237700 ps
CPU time	521.95 seconds
Started	Aug 10 07:34:18 PM PDT 24
Finished	Aug 10 07:43:00 PM PDT 24
Peak memory	310164 kb
Host	smart-1819c13e-3a69-4968-8367-599e1b570adc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127818000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.flash_ctrl_rw.2127818000
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.3985149859
Short name	T423
Test name
Test status
Simulation time	100066600 ps
CPU time	32.27 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:34:52 PM PDT 24
Peak memory	276384 kb
Host	smart-0f8993d9-a066-481a-a314-d2a9118d3cf7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985149859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_rw_evict.3985149859
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.1976863072
Short name	T1050
Test name
Test status
Simulation time	66017800 ps
CPU time	28.24 seconds
Started	Aug 10 07:34:21 PM PDT 24
Finished	Aug 10 07:34:49 PM PDT 24
Peak memory	274340 kb
Host	smart-12d6c768-9aef-4410-b230-a18772582df3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976863072 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.1976863072
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.2231185166
Short name	T132
Test name
Test status
Simulation time	1527761600 ps
CPU time	4838.34 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 08:54:58 PM PDT 24
Peak memory	289876 kb
Host	smart-54453133-1ed7-4473-90d5-eb7e7ca8e5ea
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231185166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2231185166
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.2228830603
Short name	T135
Test name
Test status
Simulation time	3658307200 ps
CPU time	86.06 seconds
Started	Aug 10 07:34:20 PM PDT 24
Finished	Aug 10 07:35:46 PM PDT 24
Peak memory	274292 kb
Host	smart-aef1e8b5-51ba-49b8-b2e8-f3667143045e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228830603 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_address.2228830603
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.2833747054
Short name	T39
Test name
Test status
Simulation time	1768385200 ps
CPU time	60.01 seconds
Started	Aug 10 07:34:17 PM PDT 24
Finished	Aug 10 07:35:17 PM PDT 24
Peak memory	274516 kb
Host	smart-05ac5b10-aafa-4671-95aa-fd270b3206e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833747054 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_serr_counter.2833747054
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.1063994407
Short name	T603
Test name
Test status
Simulation time	23768600 ps
CPU time	52.74 seconds
Started	Aug 10 07:34:13 PM PDT 24
Finished	Aug 10 07:35:05 PM PDT 24
Peak memory	271896 kb
Host	smart-8c911403-db48-4d51-a1ed-b5955b0a4b8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063994407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.1063994407
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.4158783313
Short name	T1062
Test name
Test status
Simulation time	15129900 ps
CPU time	23.51 seconds
Started	Aug 10 07:34:14 PM PDT 24
Finished	Aug 10 07:34:37 PM PDT 24
Peak memory	260356 kb
Host	smart-8c542882-7a6b-4225-90df-5f4254ba7596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158783313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.4158783313
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.3692263012
Short name	T68
Test name
Test status
Simulation time	306810300 ps
CPU time	1359.99 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:56:59 PM PDT 24
Peak memory	290392 kb
Host	smart-0de87c87-f6b6-42ab-8899-73a25b69f4fd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692263012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.3692263012
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.2619085917
Short name	T879
Test name
Test status
Simulation time	85681900 ps
CPU time	26.71 seconds
Started	Aug 10 07:34:15 PM PDT 24
Finished	Aug 10 07:34:41 PM PDT 24
Peak memory	260340 kb
Host	smart-c209a493-21b6-4f8c-83dc-0a61a53b06bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619085917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.2619085917
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.497993403
Short name	T526
Test name
Test status
Simulation time	17068730600 ps
CPU time	204.95 seconds
Started	Aug 10 07:34:16 PM PDT 24
Finished	Aug 10 07:37:41 PM PDT 24
Peak memory	260600 kb
Host	smart-29742f02-a697-44f8-bcfc-ef1075d69336
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497993403 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.flash_ctrl_wo.497993403
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.722001445
Short name	T1058
Test name
Test status
Simulation time	107208800 ps
CPU time	13.67 seconds
Started	Aug 10 07:39:46 PM PDT 24
Finished	Aug 10 07:40:00 PM PDT 24
Peak memory	265656 kb
Host	smart-f436d186-4f96-4fd4-a4ec-79145eda9952
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722001445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.722001445
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.2588337601
Short name	T959
Test name
Test status
Simulation time	23254200 ps
CPU time	15.68 seconds
Started	Aug 10 07:39:47 PM PDT 24
Finished	Aug 10 07:40:02 PM PDT 24
Peak memory	283588 kb
Host	smart-6484dbb3-b46f-46d0-8d83-3fbc597e48ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588337601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2588337601
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.2330507389
Short name	T356
Test name
Test status
Simulation time	11372000 ps
CPU time	22.43 seconds
Started	Aug 10 07:39:47 PM PDT 24
Finished	Aug 10 07:40:09 PM PDT 24
Peak memory	274240 kb
Host	smart-d67c3727-eba3-43f9-a7be-9d1c6337d0d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330507389 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.2330507389
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.1833560006
Short name	T295
Test name
Test status
Simulation time	15491850200 ps
CPU time	146.18 seconds
Started	Aug 10 07:39:39 PM PDT 24
Finished	Aug 10 07:42:05 PM PDT 24
Peak memory	261196 kb
Host	smart-40def9ca-f2d9-4d52-8e75-e21dcc8537de
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833560006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.1833560006
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.3944250306
Short name	T35
Test name
Test status
Simulation time	3182580600 ps
CPU time	134.07 seconds
Started	Aug 10 07:39:45 PM PDT 24
Finished	Aug 10 07:41:59 PM PDT 24
Peak memory	293992 kb
Host	smart-6111cd29-3232-422b-aa7a-68153189ae25
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944250306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.3944250306
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4045529853
Short name	T810
Test name
Test status
Simulation time	111964194100 ps
CPU time	427.07 seconds
Started	Aug 10 07:39:44 PM PDT 24
Finished	Aug 10 07:46:52 PM PDT 24
Peak memory	285764 kb
Host	smart-f02a9ca1-e544-4ca6-98a5-c47157b63ed2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045529853 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.4045529853
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.4046623748
Short name	T586
Test name
Test status
Simulation time	153912200 ps
CPU time	132.97 seconds
Started	Aug 10 07:39:40 PM PDT 24
Finished	Aug 10 07:41:53 PM PDT 24
Peak memory	261516 kb
Host	smart-119f70c9-3107-4cde-ba3c-3962a7079c6b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046623748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o tp_reset.4046623748
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.3906393755
Short name	T715
Test name
Test status
Simulation time	23337153200 ps
CPU time	139.24 seconds
Started	Aug 10 07:39:44 PM PDT 24
Finished	Aug 10 07:42:04 PM PDT 24
Peak memory	261132 kb
Host	smart-2ad3d388-89bd-47e5-8b10-ba4c098bc4f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906393755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.flash_ctrl_prog_reset.3906393755
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.3219928017
Short name	T712
Test name
Test status
Simulation time	54423900 ps
CPU time	31.01 seconds
Started	Aug 10 07:39:46 PM PDT 24
Finished	Aug 10 07:40:18 PM PDT 24
Peak memory	274340 kb
Host	smart-f1067055-244b-4e30-8162-8ed22b1bd4cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219928017 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3219928017
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.940213371
Short name	T384
Test name
Test status
Simulation time	2221099800 ps
CPU time	66.43 seconds
Started	Aug 10 07:39:45 PM PDT 24
Finished	Aug 10 07:40:51 PM PDT 24
Peak memory	264452 kb
Host	smart-56be08cb-7f62-4e0c-8bdd-756d0aebcc1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940213371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.940213371
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.2936029979
Short name	T593
Test name
Test status
Simulation time	48086500 ps
CPU time	77.68 seconds
Started	Aug 10 07:39:40 PM PDT 24
Finished	Aug 10 07:40:57 PM PDT 24
Peak memory	276228 kb
Host	smart-5cc19c0d-6812-494f-aaa0-3a4beb81b30c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936029979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2936029979
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.2626747510
Short name	T1019
Test name
Test status
Simulation time	150109300 ps
CPU time	14.09 seconds
Started	Aug 10 07:39:52 PM PDT 24
Finished	Aug 10 07:40:06 PM PDT 24
Peak memory	265684 kb
Host	smart-a08a146d-a9cb-4720-bfad-3cd753ad0b30
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626747510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 2626747510
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.1592345794
Short name	T474
Test name
Test status
Simulation time	100159200 ps
CPU time	15.86 seconds
Started	Aug 10 07:39:50 PM PDT 24
Finished	Aug 10 07:40:06 PM PDT 24
Peak memory	283504 kb
Host	smart-5094e798-17f6-4344-94c6-7b4c3b2e96d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592345794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1592345794
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.3277559530
Short name	T619
Test name
Test status
Simulation time	28573300 ps
CPU time	21.86 seconds
Started	Aug 10 07:39:50 PM PDT 24
Finished	Aug 10 07:40:12 PM PDT 24
Peak memory	274092 kb
Host	smart-d47650d9-b342-46c5-98d8-7513cf9a798d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277559530 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.3277559530
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2327509847
Short name	T395
Test name
Test status
Simulation time	3011206500 ps
CPU time	111.45 seconds
Started	Aug 10 07:39:45 PM PDT 24
Finished	Aug 10 07:41:37 PM PDT 24
Peak memory	261164 kb
Host	smart-79eb8702-54a7-4bb3-ac37-df9ae2b54856
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327509847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.2327509847
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.4182254514
Short name	T553
Test name
Test status
Simulation time	12868859300 ps
CPU time	295.34 seconds
Started	Aug 10 07:39:53 PM PDT 24
Finished	Aug 10 07:44:49 PM PDT 24
Peak memory	285836 kb
Host	smart-a2c5db2d-41d5-4bbb-a152-7ca119403e7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182254514 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.4182254514
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.2550211779
Short name	T893
Test name
Test status
Simulation time	83984900 ps
CPU time	131.07 seconds
Started	Aug 10 07:39:50 PM PDT 24
Finished	Aug 10 07:42:01 PM PDT 24
Peak memory	260564 kb
Host	smart-5f7a5cd8-36b9-4844-87d4-f3cfb924d54e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550211779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o tp_reset.2550211779
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.2017335184
Short name	T837
Test name
Test status
Simulation time	20533800 ps
CPU time	13.42 seconds
Started	Aug 10 07:39:52 PM PDT 24
Finished	Aug 10 07:40:05 PM PDT 24
Peak memory	259500 kb
Host	smart-e98e6374-55f3-44af-98d5-380b383df386
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017335184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.2017335184
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.39606267
Short name	T1061
Test name
Test status
Simulation time	40101300 ps
CPU time	31.12 seconds
Started	Aug 10 07:39:51 PM PDT 24
Finished	Aug 10 07:40:22 PM PDT 24
Peak memory	276368 kb
Host	smart-59302228-b0d4-495f-8123-c685886faa73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39606267 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.39606267
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.459187040
Short name	T653
Test name
Test status
Simulation time	3718210400 ps
CPU time	67.32 seconds
Started	Aug 10 07:39:51 PM PDT 24
Finished	Aug 10 07:40:59 PM PDT 24
Peak memory	263848 kb
Host	smart-51f51379-3db0-40f4-b9bb-d10df2d2f4d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459187040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.459187040
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.2004426719
Short name	T1057
Test name
Test status
Simulation time	134130400 ps
CPU time	147.92 seconds
Started	Aug 10 07:39:46 PM PDT 24
Finished	Aug 10 07:42:14 PM PDT 24
Peak memory	277588 kb
Host	smart-5ccaaaec-95b2-48e2-bd3b-ad211b1a86c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2004426719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2004426719
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.7311550
Short name	T503
Test name
Test status
Simulation time	139261700 ps
CPU time	13.53 seconds
Started	Aug 10 07:40:02 PM PDT 24
Finished	Aug 10 07:40:16 PM PDT 24
Peak memory	258716 kb
Host	smart-5716b9dd-3339-4933-b81e-de66320a2b3e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7311550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.7311550
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.2806727182
Short name	T719
Test name
Test status
Simulation time	45711100 ps
CPU time	16.11 seconds
Started	Aug 10 07:40:02 PM PDT 24
Finished	Aug 10 07:40:18 PM PDT 24
Peak memory	283572 kb
Host	smart-3acbb852-89f2-4dc1-8914-64665bf2b2cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806727182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2806727182
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.243317962
Short name	T709
Test name
Test status
Simulation time	16340700 ps
CPU time	22.39 seconds
Started	Aug 10 07:40:01 PM PDT 24
Finished	Aug 10 07:40:24 PM PDT 24
Peak memory	274252 kb
Host	smart-7b20795c-869f-4f66-83f5-d985dd761a2b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243317962 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.243317962
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2596441883
Short name	T815
Test name
Test status
Simulation time	3519695300 ps
CPU time	153.94 seconds
Started	Aug 10 07:39:58 PM PDT 24
Finished	Aug 10 07:42:32 PM PDT 24
Peak memory	263808 kb
Host	smart-048dae1d-6f5f-4fc6-bc92-49a936a14d58
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596441883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.2596441883
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.3618880007
Short name	T670
Test name
Test status
Simulation time	791356200 ps
CPU time	134.93 seconds
Started	Aug 10 07:39:57 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	294924 kb
Host	smart-db27ce74-52b6-427d-8963-07c1a7bb2346
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618880007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_intr_rd.3618880007
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1556328767
Short name	T476
Test name
Test status
Simulation time	29279062000 ps
CPU time	274.23 seconds
Started	Aug 10 07:39:57 PM PDT 24
Finished	Aug 10 07:44:31 PM PDT 24
Peak memory	285788 kb
Host	smart-a66820d0-3c95-4346-81d7-e7b32e50c093
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556328767 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1556328767
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.752626982
Short name	T176
Test name
Test status
Simulation time	476618000 ps
CPU time	133.06 seconds
Started	Aug 10 07:39:58 PM PDT 24
Finished	Aug 10 07:42:11 PM PDT 24
Peak memory	261620 kb
Host	smart-a30fb1e4-7d3e-426d-a788-7de67a392aa3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752626982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot p_reset.752626982
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.2411598121
Short name	T1084
Test name
Test status
Simulation time	20822100 ps
CPU time	13.45 seconds
Started	Aug 10 07:40:01 PM PDT 24
Finished	Aug 10 07:40:15 PM PDT 24
Peak memory	259580 kb
Host	smart-2619dd43-890c-4b69-896d-65f8f9254e72
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411598121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.2411598121
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.1288647629
Short name	T710
Test name
Test status
Simulation time	41289400 ps
CPU time	28.4 seconds
Started	Aug 10 07:40:02 PM PDT 24
Finished	Aug 10 07:40:31 PM PDT 24
Peak memory	274272 kb
Host	smart-1feb2d09-2d74-4f7b-88bd-585ac856838b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288647629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl ash_ctrl_rw_evict.1288647629
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.3389127714
Short name	T34
Test name
Test status
Simulation time	3362142100 ps
CPU time	75.58 seconds
Started	Aug 10 07:40:00 PM PDT 24
Finished	Aug 10 07:41:16 PM PDT 24
Peak memory	265400 kb
Host	smart-521d26c4-6c5c-4e70-a0be-d66d1ce1b803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389127714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3389127714
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.2148090014
Short name	T1086
Test name
Test status
Simulation time	122662900 ps
CPU time	148.03 seconds
Started	Aug 10 07:39:57 PM PDT 24
Finished	Aug 10 07:42:25 PM PDT 24
Peak memory	279808 kb
Host	smart-a38253b1-9aad-47c8-a58a-4dac1f399d9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148090014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2148090014
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.802208268
Short name	T731
Test name
Test status
Simulation time	79050800 ps
CPU time	13.76 seconds
Started	Aug 10 07:40:07 PM PDT 24
Finished	Aug 10 07:40:20 PM PDT 24
Peak memory	265716 kb
Host	smart-815b3c25-4fcb-4070-ab26-8edb872ca3d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802208268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.802208268
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.1323662516
Short name	T989
Test name
Test status
Simulation time	27742700 ps
CPU time	16.31 seconds
Started	Aug 10 07:40:08 PM PDT 24
Finished	Aug 10 07:40:24 PM PDT 24
Peak memory	283564 kb
Host	smart-f8218d20-7f42-4c7f-a63a-db5c0bf3963a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323662516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1323662516
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.1764319474
Short name	T821
Test name
Test status
Simulation time	29155400 ps
CPU time	22.39 seconds
Started	Aug 10 07:40:08 PM PDT 24
Finished	Aug 10 07:40:30 PM PDT 24
Peak memory	274280 kb
Host	smart-62219618-ebdc-4cd8-b5e7-39be02dd39c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764319474 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.1764319474
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1389650654
Short name	T947
Test name
Test status
Simulation time	2056588200 ps
CPU time	68.21 seconds
Started	Aug 10 07:40:05 PM PDT 24
Finished	Aug 10 07:41:13 PM PDT 24
Peak memory	263524 kb
Host	smart-7de691db-52e5-4731-b955-3ab77947bcb5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389650654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ hw_sec_otp.1389650654
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.750701437
Short name	T839
Test name
Test status
Simulation time	87562253900 ps
CPU time	167.08 seconds
Started	Aug 10 07:40:10 PM PDT 24
Finished	Aug 10 07:42:57 PM PDT 24
Peak memory	293588 kb
Host	smart-32224169-8deb-461f-ae17-58239db5ad39
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750701437 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.750701437
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.1889053339
Short name	T181
Test name
Test status
Simulation time	51106200 ps
CPU time	130.82 seconds
Started	Aug 10 07:40:01 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	260532 kb
Host	smart-89faeb69-1341-4a45-9d7d-e0dab8c862bc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889053339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o tp_reset.1889053339
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.596324820
Short name	T966
Test name
Test status
Simulation time	81327200 ps
CPU time	14.04 seconds
Started	Aug 10 07:40:07 PM PDT 24
Finished	Aug 10 07:40:22 PM PDT 24
Peak memory	265784 kb
Host	smart-045d4de3-5abe-4cad-a95c-c2a68cb78a59
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596324820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.flash_ctrl_prog_reset.596324820
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.2538456050
Short name	T317
Test name
Test status
Simulation time	179123700 ps
CPU time	31.62 seconds
Started	Aug 10 07:40:05 PM PDT 24
Finished	Aug 10 07:40:37 PM PDT 24
Peak memory	274316 kb
Host	smart-3af6682d-2c6b-48e3-9f92-5303e5e89dda
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538456050 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.2538456050
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.2565982863
Short name	T683
Test name
Test status
Simulation time	5725610200 ps
CPU time	79.11 seconds
Started	Aug 10 07:40:07 PM PDT 24
Finished	Aug 10 07:41:26 PM PDT 24
Peak memory	265476 kb
Host	smart-dad21461-70c1-4074-a28b-05f78fdbe5ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565982863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2565982863
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.3564483408
Short name	T365
Test name
Test status
Simulation time	87632900 ps
CPU time	123.21 seconds
Started	Aug 10 07:40:01 PM PDT 24
Finished	Aug 10 07:42:04 PM PDT 24
Peak memory	276524 kb
Host	smart-27799347-a5f7-458c-a650-f955b9c01a09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564483408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3564483408
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.836555113
Short name	T862
Test name
Test status
Simulation time	226217000 ps
CPU time	14.12 seconds
Started	Aug 10 07:40:20 PM PDT 24
Finished	Aug 10 07:40:34 PM PDT 24
Peak memory	265716 kb
Host	smart-40cf4798-2094-47c7-86fa-492accc90e17
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836555113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.836555113
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.2891760156
Short name	T560
Test name
Test status
Simulation time	63937100 ps
CPU time	16.1 seconds
Started	Aug 10 07:40:20 PM PDT 24
Finished	Aug 10 07:40:36 PM PDT 24
Peak memory	284972 kb
Host	smart-80a5b5bd-ad7c-4d0b-a7f0-9afebba0f311
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891760156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2891760156
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.2960335997
Short name	T99
Test name
Test status
Simulation time	10347800 ps
CPU time	22.32 seconds
Started	Aug 10 07:40:12 PM PDT 24
Finished	Aug 10 07:40:35 PM PDT 24
Peak memory	274220 kb
Host	smart-c0578dce-57e8-4e2d-b33d-b18397771130
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960335997 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.2960335997
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1138388289
Short name	T984
Test name
Test status
Simulation time	6644370200 ps
CPU time	142.09 seconds
Started	Aug 10 07:40:14 PM PDT 24
Finished	Aug 10 07:42:36 PM PDT 24
Peak memory	261412 kb
Host	smart-e1a1dd70-f46d-46a7-a39d-a87c95cc2973
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138388289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ hw_sec_otp.1138388289
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2356235959
Short name	T828
Test name
Test status
Simulation time	12032990000 ps
CPU time	132.06 seconds
Started	Aug 10 07:40:13 PM PDT 24
Finished	Aug 10 07:42:25 PM PDT 24
Peak memory	293624 kb
Host	smart-1114503e-2366-49ed-8410-af9698d77bd8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356235959 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.2356235959
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.2826803056
Short name	T506
Test name
Test status
Simulation time	146018100 ps
CPU time	132.61 seconds
Started	Aug 10 07:40:17 PM PDT 24
Finished	Aug 10 07:42:30 PM PDT 24
Peak memory	260820 kb
Host	smart-37cac662-048e-4e8c-be7e-07d778cc4384
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826803056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.2826803056
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.2601549080
Short name	T678
Test name
Test status
Simulation time	63716000 ps
CPU time	13.46 seconds
Started	Aug 10 07:40:13 PM PDT 24
Finished	Aug 10 07:40:27 PM PDT 24
Peak memory	259484 kb
Host	smart-efd6ea02-e110-49bd-baac-fa50ddea0bb1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601549080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.2601549080
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.3368129206
Short name	T1004
Test name
Test status
Simulation time	46087200 ps
CPU time	30.28 seconds
Started	Aug 10 07:40:13 PM PDT 24
Finished	Aug 10 07:40:44 PM PDT 24
Peak memory	276396 kb
Host	smart-7a7aa057-3147-4d83-9030-1fff1396431f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368129206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl ash_ctrl_rw_evict.3368129206
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.4088923935
Short name	T329
Test name
Test status
Simulation time	72379200 ps
CPU time	28.44 seconds
Started	Aug 10 07:40:13 PM PDT 24
Finished	Aug 10 07:40:42 PM PDT 24
Peak memory	274240 kb
Host	smart-223cc444-38c2-4450-bfd5-3276298a66c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088923935 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.4088923935
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.4119094125
Short name	T1031
Test name
Test status
Simulation time	7338288900 ps
CPU time	74.4 seconds
Started	Aug 10 07:40:17 PM PDT 24
Finished	Aug 10 07:41:32 PM PDT 24
Peak memory	265340 kb
Host	smart-28b042ee-9b2f-44b2-9997-3ddb2ec7e773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119094125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.4119094125
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.1810462765
Short name	T924
Test name
Test status
Simulation time	23750700 ps
CPU time	74.56 seconds
Started	Aug 10 07:40:13 PM PDT 24
Finished	Aug 10 07:41:28 PM PDT 24
Peak memory	276168 kb
Host	smart-7f3b675e-eac3-4fd4-86c5-fb037e042d2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1810462765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1810462765
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.2335578775
Short name	T435
Test name
Test status
Simulation time	17248500 ps
CPU time	13.46 seconds
Started	Aug 10 07:40:25 PM PDT 24
Finished	Aug 10 07:40:38 PM PDT 24
Peak memory	265708 kb
Host	smart-37faede5-ea8f-434d-89a5-dfc1b8d9c111
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335578775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 2335578775
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.1788632620
Short name	T120
Test name
Test status
Simulation time	21697200 ps
CPU time	16.05 seconds
Started	Aug 10 07:40:19 PM PDT 24
Finished	Aug 10 07:40:35 PM PDT 24
Peak memory	283628 kb
Host	smart-36348b76-43f8-4525-9ed7-ad3299e41c6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788632620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1788632620
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.655790870
Short name	T358
Test name
Test status
Simulation time	87044600 ps
CPU time	22.28 seconds
Started	Aug 10 07:40:18 PM PDT 24
Finished	Aug 10 07:40:40 PM PDT 24
Peak memory	274240 kb
Host	smart-7a3a708e-d3c9-4efa-974d-13edbb89d1a0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655790870 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.655790870
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2496036196
Short name	T1006
Test name
Test status
Simulation time	4797098500 ps
CPU time	107.8 seconds
Started	Aug 10 07:40:23 PM PDT 24
Finished	Aug 10 07:42:11 PM PDT 24
Peak memory	263388 kb
Host	smart-ab998ece-9be8-4437-a3af-7bc8923010bd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496036196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.2496036196
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.2264069264
Short name	T306
Test name
Test status
Simulation time	5692839000 ps
CPU time	211.22 seconds
Started	Aug 10 07:40:19 PM PDT 24
Finished	Aug 10 07:43:50 PM PDT 24
Peak memory	285868 kb
Host	smart-b2273a02-2026-447e-9239-b2a090b8613b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264069264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_intr_rd.2264069264
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2181306111
Short name	T76
Test name
Test status
Simulation time	23577654100 ps
CPU time	174.9 seconds
Started	Aug 10 07:40:19 PM PDT 24
Finished	Aug 10 07:43:14 PM PDT 24
Peak memory	286200 kb
Host	smart-0e50d3ef-5f00-4b29-8c42-88a9227925f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181306111 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2181306111
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.2264303372
Short name	T1102
Test name
Test status
Simulation time	42858400 ps
CPU time	132.58 seconds
Started	Aug 10 07:40:19 PM PDT 24
Finished	Aug 10 07:42:32 PM PDT 24
Peak memory	260616 kb
Host	smart-79216425-1b1b-4b27-a26a-d40a4fae12d4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264303372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o tp_reset.2264303372
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.568288783
Short name	T669
Test name
Test status
Simulation time	22175800 ps
CPU time	13.77 seconds
Started	Aug 10 07:40:19 PM PDT 24
Finished	Aug 10 07:40:33 PM PDT 24
Peak memory	259560 kb
Host	smart-c203d43b-71bb-4eea-a6d0-b6fb8d0a0df5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568288783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.flash_ctrl_prog_reset.568288783
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.1112151801
Short name	T202
Test name
Test status
Simulation time	63917500 ps
CPU time	31.08 seconds
Started	Aug 10 07:40:24 PM PDT 24
Finished	Aug 10 07:40:55 PM PDT 24
Peak memory	274312 kb
Host	smart-ed59c0ba-b5c2-4280-a9f2-9d9e6b6b041c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112151801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl ash_ctrl_rw_evict.1112151801
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2127468648
Short name	T335
Test name
Test status
Simulation time	124400100 ps
CPU time	29.08 seconds
Started	Aug 10 07:40:23 PM PDT 24
Finished	Aug 10 07:40:53 PM PDT 24
Peak memory	274328 kb
Host	smart-0890e3c3-3471-4739-aa6b-6ae87eb92729
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127468648 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2127468648
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.3873878995
Short name	T168
Test name
Test status
Simulation time	471173900 ps
CPU time	64.39 seconds
Started	Aug 10 07:40:22 PM PDT 24
Finished	Aug 10 07:41:27 PM PDT 24
Peak memory	265388 kb
Host	smart-039e944c-c344-41dd-b709-c995d464222e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873878995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3873878995
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.2648475249
Short name	T622
Test name
Test status
Simulation time	235990800 ps
CPU time	125.31 seconds
Started	Aug 10 07:40:20 PM PDT 24
Finished	Aug 10 07:42:25 PM PDT 24
Peak memory	278140 kb
Host	smart-29bf4705-e3f4-4212-9f0a-a6e8a796b366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2648475249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2648475249
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.100722336
Short name	T1017
Test name
Test status
Simulation time	33314400 ps
CPU time	13.49 seconds
Started	Aug 10 07:40:30 PM PDT 24
Finished	Aug 10 07:40:43 PM PDT 24
Peak memory	265744 kb
Host	smart-01de5468-9ef6-4e58-89dd-17375461f7e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100722336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.100722336
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.3795449621
Short name	T659
Test name
Test status
Simulation time	41723000 ps
CPU time	13.46 seconds
Started	Aug 10 07:40:30 PM PDT 24
Finished	Aug 10 07:40:44 PM PDT 24
Peak memory	284968 kb
Host	smart-9064f1d7-dc9e-4c31-8f38-c005ee177ff6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795449621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3795449621
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.1777555181
Short name	T521
Test name
Test status
Simulation time	11246200 ps
CPU time	22.14 seconds
Started	Aug 10 07:40:31 PM PDT 24
Finished	Aug 10 07:40:53 PM PDT 24
Peak memory	274356 kb
Host	smart-4e41d757-a927-4d29-bffd-b9d8f44fb711
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777555181 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.1777555181
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2907090003
Short name	T487
Test name
Test status
Simulation time	4057867300 ps
CPU time	142.53 seconds
Started	Aug 10 07:40:25 PM PDT 24
Finished	Aug 10 07:42:47 PM PDT 24
Peak memory	261636 kb
Host	smart-5fa1479b-2f50-4754-af4d-5288c84b10d1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907090003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.2907090003
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.2056433744
Short name	T311
Test name
Test status
Simulation time	7873392000 ps
CPU time	203.56 seconds
Started	Aug 10 07:40:25 PM PDT 24
Finished	Aug 10 07:43:48 PM PDT 24
Peak memory	291584 kb
Host	smart-b7733dae-eaff-4eef-bf9a-2b38ae9d2c8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056433744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.2056433744
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1580223774
Short name	T880
Test name
Test status
Simulation time	23784195900 ps
CPU time	293.39 seconds
Started	Aug 10 07:40:24 PM PDT 24
Finished	Aug 10 07:45:18 PM PDT 24
Peak memory	295032 kb
Host	smart-c8faeb1d-c149-4cfb-a9ee-216857b60ee3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580223774 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1580223774
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.1238654372
Short name	T654
Test name
Test status
Simulation time	103019700 ps
CPU time	132.26 seconds
Started	Aug 10 07:40:25 PM PDT 24
Finished	Aug 10 07:42:38 PM PDT 24
Peak memory	260720 kb
Host	smart-5e3ecad1-23c5-4956-994a-c48ae7e000b9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238654372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.1238654372
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.4211129519
Short name	T1024
Test name
Test status
Simulation time	68514200 ps
CPU time	13.45 seconds
Started	Aug 10 07:40:25 PM PDT 24
Finished	Aug 10 07:40:38 PM PDT 24
Peak memory	259528 kb
Host	smart-7bfb6910-0bc2-4e64-96a5-40fa2473d115
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211129519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.4211129519
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.3889309398
Short name	T315
Test name
Test status
Simulation time	73160600 ps
CPU time	31.97 seconds
Started	Aug 10 07:40:24 PM PDT 24
Finished	Aug 10 07:40:56 PM PDT 24
Peak memory	276336 kb
Host	smart-3833f8c2-c732-45f7-b3d5-93595200b559
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889309398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl ash_ctrl_rw_evict.3889309398
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.2851463242
Short name	T1049
Test name
Test status
Simulation time	111316400 ps
CPU time	31.43 seconds
Started	Aug 10 07:40:32 PM PDT 24
Finished	Aug 10 07:41:03 PM PDT 24
Peak memory	275588 kb
Host	smart-533df0f4-4e99-4968-98f9-001c56ecb797
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851463242 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.2851463242
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.2211037476
Short name	T918
Test name
Test status
Simulation time	37330900 ps
CPU time	152.54 seconds
Started	Aug 10 07:40:25 PM PDT 24
Finished	Aug 10 07:42:57 PM PDT 24
Peak memory	277460 kb
Host	smart-b4bd4a8b-31cb-4766-96e5-2d6b23597fd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211037476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2211037476
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.651320684
Short name	T948
Test name
Test status
Simulation time	48026600 ps
CPU time	14.38 seconds
Started	Aug 10 07:40:36 PM PDT 24
Finished	Aug 10 07:40:51 PM PDT 24
Peak memory	258868 kb
Host	smart-f511bf54-4b82-4069-a1c3-03a6c96a1e87
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651320684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.651320684
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.4106045202
Short name	T362
Test name
Test status
Simulation time	40088900 ps
CPU time	16.3 seconds
Started	Aug 10 07:40:36 PM PDT 24
Finished	Aug 10 07:40:53 PM PDT 24
Peak memory	283628 kb
Host	smart-239a680e-c95b-4969-8332-09216c65e107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106045202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.4106045202
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.3572655245
Short name	T44
Test name
Test status
Simulation time	28621700 ps
CPU time	21.59 seconds
Started	Aug 10 07:40:36 PM PDT 24
Finished	Aug 10 07:40:57 PM PDT 24
Peak memory	274324 kb
Host	smart-e75cb90b-9728-4b72-af51-bcad25d4b2f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572655245 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.3572655245
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3730042540
Short name	T580
Test name
Test status
Simulation time	643294200 ps
CPU time	60.52 seconds
Started	Aug 10 07:40:35 PM PDT 24
Finished	Aug 10 07:41:35 PM PDT 24
Peak memory	263492 kb
Host	smart-a2f59608-33c9-4c75-803c-35978ee3863b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730042540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ hw_sec_otp.3730042540
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.3568971008
Short name	T338
Test name
Test status
Simulation time	1237608200 ps
CPU time	135.1 seconds
Started	Aug 10 07:40:32 PM PDT 24
Finished	Aug 10 07:42:47 PM PDT 24
Peak memory	286340 kb
Host	smart-64abf585-cffd-4509-a807-3137fca821fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568971008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.3568971008
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.812796373
Short name	T530
Test name
Test status
Simulation time	80720012600 ps
CPU time	300.34 seconds
Started	Aug 10 07:40:32 PM PDT 24
Finished	Aug 10 07:45:32 PM PDT 24
Peak memory	285676 kb
Host	smart-c4c5cbe7-480c-4503-b49a-2f45126877f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812796373 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.812796373
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.1147961516
Short name	T663
Test name
Test status
Simulation time	52029500 ps
CPU time	133 seconds
Started	Aug 10 07:40:36 PM PDT 24
Finished	Aug 10 07:42:49 PM PDT 24
Peak memory	261712 kb
Host	smart-1be89911-e966-4158-aa78-16f73bbc6edd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147961516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o tp_reset.1147961516
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.3179442542
Short name	T512
Test name
Test status
Simulation time	29182600 ps
CPU time	28.85 seconds
Started	Aug 10 07:40:36 PM PDT 24
Finished	Aug 10 07:41:05 PM PDT 24
Peak memory	274320 kb
Host	smart-7b1bc6fb-e902-4ffa-ac0a-e725bde87312
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179442542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl ash_ctrl_rw_evict.3179442542
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.4279819296
Short name	T749
Test name
Test status
Simulation time	1589316800 ps
CPU time	62.14 seconds
Started	Aug 10 07:40:37 PM PDT 24
Finished	Aug 10 07:41:39 PM PDT 24
Peak memory	264328 kb
Host	smart-a43713e4-5788-410d-a6ac-15fa7c687824
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279819296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.4279819296
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.1178194863
Short name	T213
Test name
Test status
Simulation time	277319700 ps
CPU time	176.11 seconds
Started	Aug 10 07:40:29 PM PDT 24
Finished	Aug 10 07:43:26 PM PDT 24
Peak memory	278048 kb
Host	smart-980cd93e-5604-4fae-b8ac-abf24233a540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178194863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1178194863
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.3628599944
Short name	T448
Test name
Test status
Simulation time	106605700 ps
CPU time	14.08 seconds
Started	Aug 10 07:40:41 PM PDT 24
Finished	Aug 10 07:40:55 PM PDT 24
Peak memory	258788 kb
Host	smart-4889d979-0c64-4302-9feb-dd87a7f01208
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628599944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test. 3628599944
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.1811082486
Short name	T741
Test name
Test status
Simulation time	14082300 ps
CPU time	13.23 seconds
Started	Aug 10 07:40:41 PM PDT 24
Finished	Aug 10 07:40:55 PM PDT 24
Peak memory	275412 kb
Host	smart-b4d80e4c-36b2-404f-ad57-16c3d1bbd9ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1811082486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1811082486
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.3576624712
Short name	T967
Test name
Test status
Simulation time	11915000 ps
CPU time	22.07 seconds
Started	Aug 10 07:40:43 PM PDT 24
Finished	Aug 10 07:41:05 PM PDT 24
Peak memory	274320 kb
Host	smart-2f1d6a36-4866-4d99-a911-91a167a296d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576624712 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.3576624712
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1832174858
Short name	T927
Test name
Test status
Simulation time	5247977300 ps
CPU time	150.89 seconds
Started	Aug 10 07:40:37 PM PDT 24
Finished	Aug 10 07:43:08 PM PDT 24
Peak memory	261316 kb
Host	smart-ef5de559-efa9-45ce-859e-719262a8834e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832174858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.1832174858
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.857321027
Short name	T647
Test name
Test status
Simulation time	8235657000 ps
CPU time	224.57 seconds
Started	Aug 10 07:40:42 PM PDT 24
Finished	Aug 10 07:44:26 PM PDT 24
Peak memory	285716 kb
Host	smart-a24c559c-2309-488b-87c1-bfa8a768e176
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857321027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas h_ctrl_intr_rd.857321027
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1815022592
Short name	T309
Test name
Test status
Simulation time	6017049100 ps
CPU time	137.66 seconds
Started	Aug 10 07:40:41 PM PDT 24
Finished	Aug 10 07:42:59 PM PDT 24
Peak memory	290552 kb
Host	smart-2f43bcd7-78a2-42e1-86f8-59707db2260b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815022592 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1815022592
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.1154104771
Short name	T369
Test name
Test status
Simulation time	99781000 ps
CPU time	132.32 seconds
Started	Aug 10 07:40:42 PM PDT 24
Finished	Aug 10 07:42:54 PM PDT 24
Peak memory	261676 kb
Host	smart-7adf3d34-0421-4982-8fe0-61d7b110ca97
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154104771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o tp_reset.1154104771
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.253471563
Short name	T577
Test name
Test status
Simulation time	38027900 ps
CPU time	13.53 seconds
Started	Aug 10 07:40:42 PM PDT 24
Finished	Aug 10 07:40:55 PM PDT 24
Peak memory	260044 kb
Host	smart-b707b863-bc72-407a-ba61-23d73e513622
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253471563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.flash_ctrl_prog_reset.253471563
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.798890243
Short name	T1038
Test name
Test status
Simulation time	50188700 ps
CPU time	32 seconds
Started	Aug 10 07:40:41 PM PDT 24
Finished	Aug 10 07:41:13 PM PDT 24
Peak memory	276396 kb
Host	smart-6aa5cc0a-8bc5-4cf6-8b04-3d15c3f95ac7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798890243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_rw_evict.798890243
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.2210953017
Short name	T336
Test name
Test status
Simulation time	35344700 ps
CPU time	31.64 seconds
Started	Aug 10 07:40:42 PM PDT 24
Finished	Aug 10 07:41:14 PM PDT 24
Peak memory	274268 kb
Host	smart-156f0456-5894-4538-a7ce-a95f05385cbe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210953017 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.2210953017
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.1788393165
Short name	T380
Test name
Test status
Simulation time	2429651900 ps
CPU time	56.21 seconds
Started	Aug 10 07:40:41 PM PDT 24
Finished	Aug 10 07:41:38 PM PDT 24
Peak memory	265792 kb
Host	smart-a5418cbb-c1fa-4a86-b2ab-a336cb4ef008
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788393165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1788393165
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.1265116053
Short name	T762
Test name
Test status
Simulation time	32827800 ps
CPU time	52.84 seconds
Started	Aug 10 07:40:38 PM PDT 24
Finished	Aug 10 07:41:31 PM PDT 24
Peak memory	271900 kb
Host	smart-dc353527-7d23-47ac-bfc3-d2959106cdfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265116053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.1265116053
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.1930676337
Short name	T854
Test name
Test status
Simulation time	29671400 ps
CPU time	13.52 seconds
Started	Aug 10 07:40:53 PM PDT 24
Finished	Aug 10 07:41:07 PM PDT 24
Peak memory	258788 kb
Host	smart-8fd2e4be-c141-4b22-af3c-e07cb426559c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930676337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 1930676337
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.4163846631
Short name	T131
Test name
Test status
Simulation time	27568700 ps
CPU time	16.01 seconds
Started	Aug 10 07:40:53 PM PDT 24
Finished	Aug 10 07:41:09 PM PDT 24
Peak memory	275508 kb
Host	smart-da29ba5b-420d-4594-b180-a49c90d83f22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163846631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.4163846631
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.2437070087
Short name	T912
Test name
Test status
Simulation time	17197900 ps
CPU time	22.2 seconds
Started	Aug 10 07:40:54 PM PDT 24
Finished	Aug 10 07:41:16 PM PDT 24
Peak memory	274292 kb
Host	smart-2ef8fcdd-395c-4506-9527-a60bf2ac877d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437070087 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.2437070087
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2676012996
Short name	T844
Test name
Test status
Simulation time	3189202100 ps
CPU time	96.71 seconds
Started	Aug 10 07:40:48 PM PDT 24
Finished	Aug 10 07:42:25 PM PDT 24
Peak memory	263880 kb
Host	smart-9971e3ec-419a-45c8-8a6b-689468246295
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676012996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ hw_sec_otp.2676012996
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.2995002297
Short name	T933
Test name
Test status
Simulation time	624015000 ps
CPU time	125.75 seconds
Started	Aug 10 07:40:48 PM PDT 24
Finished	Aug 10 07:42:54 PM PDT 24
Peak memory	294784 kb
Host	smart-91aad802-cb58-4dae-ab7e-4a9c144eab30
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995002297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.2995002297
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.623331826
Short name	T925
Test name
Test status
Simulation time	53182455400 ps
CPU time	269.16 seconds
Started	Aug 10 07:40:49 PM PDT 24
Finished	Aug 10 07:45:18 PM PDT 24
Peak memory	285876 kb
Host	smart-3aa0491c-532d-4a18-8ab7-0e041f12d7ea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623331826 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.623331826
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.4201845719
Short name	T882
Test name
Test status
Simulation time	39383900 ps
CPU time	132.6 seconds
Started	Aug 10 07:40:51 PM PDT 24
Finished	Aug 10 07:43:03 PM PDT 24
Peak memory	264628 kb
Host	smart-60eb8d93-0b4b-492c-b764-753c3bbc64d3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201845719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o tp_reset.4201845719
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.2723007138
Short name	T711
Test name
Test status
Simulation time	20652800 ps
CPU time	14.2 seconds
Started	Aug 10 07:40:51 PM PDT 24
Finished	Aug 10 07:41:06 PM PDT 24
Peak memory	259396 kb
Host	smart-a0ef7196-017c-4c3a-a7ed-5ebb405b2ec8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723007138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.flash_ctrl_prog_reset.2723007138
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.1651133019
Short name	T316
Test name
Test status
Simulation time	81229900 ps
CPU time	31.66 seconds
Started	Aug 10 07:40:51 PM PDT 24
Finished	Aug 10 07:41:23 PM PDT 24
Peak memory	276308 kb
Host	smart-e81e29a2-2406-4c7b-b57d-e11c6cc4adf5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651133019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl ash_ctrl_rw_evict.1651133019
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.925739959
Short name	T417
Test name
Test status
Simulation time	104406600 ps
CPU time	174.54 seconds
Started	Aug 10 07:40:48 PM PDT 24
Finished	Aug 10 07:43:43 PM PDT 24
Peak memory	277864 kb
Host	smart-f0824ac4-b0fa-4a78-9b3e-c72e6e8ffeae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=925739959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.925739959
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.3855243503
Short name	T113
Test name
Test status
Simulation time	41225900 ps
CPU time	14.05 seconds
Started	Aug 10 07:34:54 PM PDT 24
Finished	Aug 10 07:35:08 PM PDT 24
Peak memory	258760 kb
Host	smart-cf7145e0-9966-4b54-9625-a14059f89bea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855243503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3 855243503
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.867382977
Short name	T241
Test name
Test status
Simulation time	73035500 ps
CPU time	14.52 seconds
Started	Aug 10 07:34:54 PM PDT 24
Finished	Aug 10 07:35:09 PM PDT 24
Peak memory	265712 kb
Host	smart-39c739ef-4c6c-4074-86ce-695bd3f4e16b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867382977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. flash_ctrl_config_regwen.867382977
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.3093695525
Short name	T775
Test name
Test status
Simulation time	15564200 ps
CPU time	16.03 seconds
Started	Aug 10 07:34:49 PM PDT 24
Finished	Aug 10 07:35:05 PM PDT 24
Peak memory	283544 kb
Host	smart-18e4341e-401d-48c4-b5cf-f0310d8bd0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093695525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3093695525
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_derr_detect.1188178352
Short name	T717
Test name
Test status
Simulation time	879370300 ps
CPU time	220.35 seconds
Started	Aug 10 07:34:42 PM PDT 24
Finished	Aug 10 07:38:23 PM PDT 24
Peak memory	282272 kb
Host	smart-3051ed5e-ef56-4d12-9034-a0d2b2047ca6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188178352 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.1188178352
Directory	/workspace/3.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.4043085624
Short name	T98
Test name
Test status
Simulation time	15045400 ps
CPU time	21.91 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 07:35:09 PM PDT 24
Peak memory	274320 kb
Host	smart-531e9433-4308-488a-9d8b-e914a7c4ff49
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043085624 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.4043085624
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.4206328777
Short name	T60
Test name
Test status
Simulation time	22086435400 ps
CPU time	719.82 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:46:25 PM PDT 24
Peak memory	264068 kb
Host	smart-20bf17ad-f6e9-4b6e-b37f-f9045c71fe9b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4206328777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.4206328777
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.1940406004
Short name	T1055
Test name
Test status
Simulation time	23268280100 ps
CPU time	2327.39 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 08:13:13 PM PDT 24
Peak memory	265792 kb
Host	smart-681c37a3-9f06-4908-b9e3-b4e10853cb83
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1940406004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1940406004
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.2659095050
Short name	T106
Test name
Test status
Simulation time	2281732100 ps
CPU time	2631.25 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 08:18:17 PM PDT 24
Peak memory	265800 kb
Host	smart-35a9d0ba-f7ff-4057-b85b-14fa909bc1cc
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659095050 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2659095050
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.3287916449
Short name	T817
Test name
Test status
Simulation time	281774600 ps
CPU time	750.09 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:46:55 PM PDT 24
Peak memory	274012 kb
Host	smart-d941da42-6a45-4405-a596-496a69a7ffa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287916449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3287916449
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.1345923248
Short name	T54
Test name
Test status
Simulation time	1754494200 ps
CPU time	27.43 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:34:52 PM PDT 24
Peak memory	263160 kb
Host	smart-543f1dd0-a60f-4e05-bd07-bf5d3f980122
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345923248 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1345923248
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.2676965592
Short name	T142
Test name
Test status
Simulation time	112711501200 ps
CPU time	2708.03 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 08:19:34 PM PDT 24
Peak memory	277704 kb
Host	smart-f38ef3ce-7286-4ac5-902c-780684a93363
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676965592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.2676965592
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.2037059939
Short name	T462
Test name
Test status
Simulation time	203191400 ps
CPU time	91.12 seconds
Started	Aug 10 07:34:27 PM PDT 24
Finished	Aug 10 07:35:58 PM PDT 24
Peak memory	265872 kb
Host	smart-31d8f5e7-5253-4358-9e27-ad91d6f45eca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2037059939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2037059939
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.203448360
Short name	T773
Test name
Test status
Simulation time	10033788700 ps
CPU time	54.26 seconds
Started	Aug 10 07:34:57 PM PDT 24
Finished	Aug 10 07:35:52 PM PDT 24
Peak memory	288276 kb
Host	smart-d7741c05-39bd-49a6-b65e-d274126084db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203448360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.203448360
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2199923990
Short name	T266
Test name
Test status
Simulation time	26221600 ps
CPU time	13.47 seconds
Started	Aug 10 07:34:57 PM PDT 24
Finished	Aug 10 07:35:11 PM PDT 24
Peak memory	258888 kb
Host	smart-a36431a0-662d-437f-aa2d-f916c0021eb4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199923990 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2199923990
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.233981269
Short name	T771
Test name
Test status
Simulation time	4586390700 ps
CPU time	133.8 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 07:36:40 PM PDT 24
Peak memory	263912 kb
Host	smart-c46a7e89-f073-40b5-aab4-0c0154256f22
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233981269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw _sec_otp.233981269
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_integrity.2821497246
Short name	T572
Test name
Test status
Simulation time	3422273200 ps
CPU time	657.84 seconds
Started	Aug 10 07:34:42 PM PDT 24
Finished	Aug 10 07:45:40 PM PDT 24
Peak memory	332488 kb
Host	smart-580af02a-dad0-4cd9-9a36-8818963ef893
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821497246 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_integrity.2821497246
Directory	/workspace/3.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.2516588489
Short name	T1040
Test name
Test status
Simulation time	583406600 ps
CPU time	155.55 seconds
Started	Aug 10 07:34:42 PM PDT 24
Finished	Aug 10 07:37:18 PM PDT 24
Peak memory	291732 kb
Host	smart-516f8543-dc50-4462-817e-082d1214183d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516588489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.2516588489
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.835175418
Short name	T857
Test name
Test status
Simulation time	11172535600 ps
CPU time	120.34 seconds
Started	Aug 10 07:34:42 PM PDT 24
Finished	Aug 10 07:36:42 PM PDT 24
Peak memory	293548 kb
Host	smart-741a83d6-583f-4335-ba76-ebbf62696472
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835175418 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.835175418
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.3209770202
Short name	T778
Test name
Test status
Simulation time	2627072300 ps
CPU time	66.51 seconds
Started	Aug 10 07:34:42 PM PDT 24
Finished	Aug 10 07:35:49 PM PDT 24
Peak memory	260632 kb
Host	smart-46625519-91a7-479a-93e4-cffe42971044
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209770202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_intr_wr.3209770202
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3874126635
Short name	T706
Test name
Test status
Simulation time	106841302000 ps
CPU time	213.48 seconds
Started	Aug 10 07:34:49 PM PDT 24
Finished	Aug 10 07:38:22 PM PDT 24
Peak memory	261192 kb
Host	smart-94d147de-9e3d-4f12-a84c-717367befc4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387 4126635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3874126635
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.3186423121
Short name	T205
Test name
Test status
Simulation time	6501925000 ps
CPU time	67.37 seconds
Started	Aug 10 07:34:27 PM PDT 24
Finished	Aug 10 07:35:34 PM PDT 24
Peak memory	261204 kb
Host	smart-78876c2c-383a-449d-9f20-0c8cb92c113b
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186423121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3186423121
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.4292320079
Short name	T806
Test name
Test status
Simulation time	15498900 ps
CPU time	13.6 seconds
Started	Aug 10 07:34:59 PM PDT 24
Finished	Aug 10 07:35:13 PM PDT 24
Peak memory	265408 kb
Host	smart-bdf3d281-203d-4180-aace-a7fd44971dbb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292320079 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.4292320079
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.618305052
Short name	T81
Test name
Test status
Simulation time	675993000 ps
CPU time	74.88 seconds
Started	Aug 10 07:34:29 PM PDT 24
Finished	Aug 10 07:35:44 PM PDT 24
Peak memory	261272 kb
Host	smart-13ec13ed-61ec-4663-9a1f-e3e79c787d4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618305052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.618305052
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.2237523396
Short name	T160
Test name
Test status
Simulation time	16953344400 ps
CPU time	210.94 seconds
Started	Aug 10 07:34:27 PM PDT 24
Finished	Aug 10 07:37:58 PM PDT 24
Peak memory	273592 kb
Host	smart-13868547-37a8-4da2-a556-e0e5b7f895d0
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237523396 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2237523396
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.1818031679
Short name	T886
Test name
Test status
Simulation time	198967400 ps
CPU time	132.7 seconds
Started	Aug 10 07:34:24 PM PDT 24
Finished	Aug 10 07:36:37 PM PDT 24
Peak memory	265872 kb
Host	smart-04a9064e-d715-4d98-985a-b521a4065a31
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818031679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot p_reset.1818031679
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.2429586913
Short name	T1090
Test name
Test status
Simulation time	4124827400 ps
CPU time	170.99 seconds
Started	Aug 10 07:34:43 PM PDT 24
Finished	Aug 10 07:37:34 PM PDT 24
Peak memory	295972 kb
Host	smart-ed84d345-bd1d-4dea-be76-e1e7cd16ee7f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429586913 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2429586913
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.282793177
Short name	T216
Test name
Test status
Simulation time	18107600 ps
CPU time	14.08 seconds
Started	Aug 10 07:34:53 PM PDT 24
Finished	Aug 10 07:35:08 PM PDT 24
Peak memory	262336 kb
Host	smart-66272017-f6b9-4af5-a81c-ceba89155595
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=282793177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.282793177
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.297378988
Short name	T509
Test name
Test status
Simulation time	5376410000 ps
CPU time	321.18 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:39:47 PM PDT 24
Peak memory	263724 kb
Host	smart-3d015294-963f-4706-ab70-946ed3b00f9e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=297378988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.297378988
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.4116391526
Short name	T84
Test name
Test status
Simulation time	15055400 ps
CPU time	14.12 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 07:35:02 PM PDT 24
Peak memory	266264 kb
Host	smart-1f3f4e91-f35c-4e12-b763-862ccc6ecd31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116391526 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.4116391526
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.3461485748
Short name	T758
Test name
Test status
Simulation time	26142700 ps
CPU time	13.59 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 07:35:00 PM PDT 24
Peak memory	259392 kb
Host	smart-21b3f971-309c-4269-b022-a042f9d0c7e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461485748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.flash_ctrl_prog_reset.3461485748
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.1875724195
Short name	T872
Test name
Test status
Simulation time	68008000 ps
CPU time	256.72 seconds
Started	Aug 10 07:34:28 PM PDT 24
Finished	Aug 10 07:38:45 PM PDT 24
Peak memory	277628 kb
Host	smart-5c58205c-9e6c-4768-8f58-f9f8378ec543
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1875724195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1875724195
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.688219232
Short name	T1056
Test name
Test status
Simulation time	722083100 ps
CPU time	147.23 seconds
Started	Aug 10 07:34:29 PM PDT 24
Finished	Aug 10 07:36:56 PM PDT 24
Peak memory	263440 kb
Host	smart-a73ecbd3-745b-4540-9f56-428d8d03bdc3
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=688219232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.688219232
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.1883028523
Short name	T318
Test name
Test status
Simulation time	175638700 ps
CPU time	31.37 seconds
Started	Aug 10 07:34:48 PM PDT 24
Finished	Aug 10 07:35:19 PM PDT 24
Peak memory	274356 kb
Host	smart-8f745c4c-9640-4eeb-8509-2e3a031a5a02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883028523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_re_evict.1883028523
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.480122845
Short name	T418
Test name
Test status
Simulation time	57633800 ps
CPU time	21.18 seconds
Started	Aug 10 07:34:32 PM PDT 24
Finished	Aug 10 07:34:53 PM PDT 24
Peak memory	266092 kb
Host	smart-29b1b397-c131-436c-8bdd-451cd7ca4df4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480122845 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.480122845
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.612462933
Short name	T644
Test name
Test status
Simulation time	42802000 ps
CPU time	22.85 seconds
Started	Aug 10 07:34:24 PM PDT 24
Finished	Aug 10 07:34:47 PM PDT 24
Peak memory	266040 kb
Host	smart-62b6faa3-1646-48e8-8b10-9661409e99be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612462933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_read_word_sweep_serr.612462933
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.2824066515
Short name	T649
Test name
Test status
Simulation time	2021808800 ps
CPU time	114.97 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:36:20 PM PDT 24
Peak memory	282440 kb
Host	smart-b792868f-6946-4104-8046-6b4ab934abec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824066515 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_ro.2824066515
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.2206134627
Short name	T171
Test name
Test status
Simulation time	1486975400 ps
CPU time	148.61 seconds
Started	Aug 10 07:34:35 PM PDT 24
Finished	Aug 10 07:37:04 PM PDT 24
Peak memory	282632 kb
Host	smart-57b559c3-8dac-4834-a9d1-6aa577734cde
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2206134627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2206134627
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.3840326106
Short name	T928
Test name
Test status
Simulation time	1787191400 ps
CPU time	123.16 seconds
Started	Aug 10 07:34:32 PM PDT 24
Finished	Aug 10 07:36:35 PM PDT 24
Peak memory	282600 kb
Host	smart-c166d757-32af-4f45-83e6-b9e6dd939f22
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840326106 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3840326106
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.255045661
Short name	T540
Test name
Test status
Simulation time	3286136600 ps
CPU time	491.91 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:42:38 PM PDT 24
Peak memory	315308 kb
Host	smart-e34cbf04-1313-4516-8d6f-7d369249db53
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255045661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.255045661
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_derr.2699519813
Short name	T971
Test name
Test status
Simulation time	24803353000 ps
CPU time	238.99 seconds
Started	Aug 10 07:34:37 PM PDT 24
Finished	Aug 10 07:38:36 PM PDT 24
Peak memory	289128 kb
Host	smart-7313505f-6f30-4e91-9cd0-be8201f3aaad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699519813 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_derr.2699519813
Directory	/workspace/3.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict.3392212453
Short name	T564
Test name
Test status
Simulation time	45689800 ps
CPU time	31.2 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 07:35:19 PM PDT 24
Peak memory	274288 kb
Host	smart-a860c1c1-61ed-4f2a-930d-7432edd3f874
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392212453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_rw_evict.3392212453
Directory	/workspace/3.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.2650450734
Short name	T264
Test name
Test status
Simulation time	1502299600 ps
CPU time	199.17 seconds
Started	Aug 10 07:34:30 PM PDT 24
Finished	Aug 10 07:37:49 PM PDT 24
Peak memory	296060 kb
Host	smart-9227f743-acd9-40ef-b2ba-b9f3cdda0df6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650450734 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.flash_ctrl_rw_serr.2650450734
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.3476229047
Short name	T133
Test name
Test status
Simulation time	3221699200 ps
CPU time	4888.24 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 08:56:16 PM PDT 24
Peak memory	295664 kb
Host	smart-97833022-0a90-4ec1-bf8b-f42ea3333246
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476229047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.3476229047
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.3411268100
Short name	T1041
Test name
Test status
Simulation time	2795968500 ps
CPU time	62.92 seconds
Started	Aug 10 07:34:46 PM PDT 24
Finished	Aug 10 07:35:49 PM PDT 24
Peak memory	264868 kb
Host	smart-b3de1ebb-2174-4c92-8590-b7635dfde8e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411268100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.3411268100
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.2670237927
Short name	T421
Test name
Test status
Simulation time	1418029300 ps
CPU time	132.26 seconds
Started	Aug 10 07:34:32 PM PDT 24
Finished	Aug 10 07:36:44 PM PDT 24
Peak memory	266052 kb
Host	smart-50b424aa-9f93-444d-a364-8a673b4d65c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670237927 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.2670237927
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.870542270
Short name	T454
Test name
Test status
Simulation time	887014700 ps
CPU time	58.53 seconds
Started	Aug 10 07:34:33 PM PDT 24
Finished	Aug 10 07:35:32 PM PDT 24
Peak memory	274396 kb
Host	smart-0c7366bc-0b14-486e-850b-e14e65f73ee1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870542270 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_counter.870542270
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.575387179
Short name	T638
Test name
Test status
Simulation time	59137000 ps
CPU time	144.94 seconds
Started	Aug 10 07:34:19 PM PDT 24
Finished	Aug 10 07:36:44 PM PDT 24
Peak memory	277416 kb
Host	smart-21fd2999-d4af-4762-a5c3-60d64678fee4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575387179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.575387179
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.1215954979
Short name	T504
Test name
Test status
Simulation time	86700700 ps
CPU time	26.22 seconds
Started	Aug 10 07:34:24 PM PDT 24
Finished	Aug 10 07:34:51 PM PDT 24
Peak memory	260416 kb
Host	smart-1a165754-77f8-424d-9f56-c4ba9e1eef9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215954979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1215954979
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.4020415001
Short name	T796
Test name
Test status
Simulation time	3801739600 ps
CPU time	1499.01 seconds
Started	Aug 10 07:34:47 PM PDT 24
Finished	Aug 10 07:59:47 PM PDT 24
Peak memory	288556 kb
Host	smart-4a5add85-1570-42af-bc82-6bd8f43fe294
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020415001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.4020415001
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.3881693863
Short name	T911
Test name
Test status
Simulation time	83937000 ps
CPU time	26.66 seconds
Started	Aug 10 07:34:26 PM PDT 24
Finished	Aug 10 07:34:53 PM PDT 24
Peak memory	260204 kb
Host	smart-7fa28120-95df-4b62-88ae-5afc16bffc6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881693863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3881693863
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.2958215735
Short name	T287
Test name
Test status
Simulation time	4574687700 ps
CPU time	192.99 seconds
Started	Aug 10 07:34:25 PM PDT 24
Finished	Aug 10 07:37:38 PM PDT 24
Peak memory	260652 kb
Host	smart-3c4e08f1-9d90-49cd-ab29-53c10367c47b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958215735 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.2958215735
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.702577191
Short name	T655
Test name
Test status
Simulation time	24452500 ps
CPU time	13.83 seconds
Started	Aug 10 07:40:58 PM PDT 24
Finished	Aug 10 07:41:12 PM PDT 24
Peak memory	265740 kb
Host	smart-3333ba1b-f631-45c7-b772-2d1c765d2b97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702577191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.702577191
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.1791801970
Short name	T1083
Test name
Test status
Simulation time	15460400 ps
CPU time	16.14 seconds
Started	Aug 10 07:41:00 PM PDT 24
Finished	Aug 10 07:41:16 PM PDT 24
Peak memory	275548 kb
Host	smart-e6e1cd71-a8c7-4141-a28a-d5432167ba9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791801970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1791801970
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.1162451167
Short name	T371
Test name
Test status
Simulation time	36263500 ps
CPU time	22.02 seconds
Started	Aug 10 07:40:58 PM PDT 24
Finished	Aug 10 07:41:20 PM PDT 24
Peak memory	266248 kb
Host	smart-d566e4dc-8cbf-4032-abc6-5b2998572419
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162451167 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.1162451167
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.582392618
Short name	T116
Test name
Test status
Simulation time	3122708000 ps
CPU time	208.46 seconds
Started	Aug 10 07:40:53 PM PDT 24
Finished	Aug 10 07:44:21 PM PDT 24
Peak memory	262624 kb
Host	smart-46ed2a98-39a9-4f6c-9679-a928121a2a12
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582392618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h w_sec_otp.582392618
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.348486346
Short name	T1001
Test name
Test status
Simulation time	2807530800 ps
CPU time	140.36 seconds
Started	Aug 10 07:40:54 PM PDT 24
Finished	Aug 10 07:43:14 PM PDT 24
Peak memory	295076 kb
Host	smart-df7eb4a3-1288-4cf1-b7fe-b85207afa18a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348486346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas h_ctrl_intr_rd.348486346
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1369037623
Short name	T981
Test name
Test status
Simulation time	12517739900 ps
CPU time	147.13 seconds
Started	Aug 10 07:40:54 PM PDT 24
Finished	Aug 10 07:43:22 PM PDT 24
Peak memory	293592 kb
Host	smart-9027a922-4be3-453e-84a9-1c16313bedee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369037623 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.1369037623
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.3941442167
Short name	T897
Test name
Test status
Simulation time	51614900 ps
CPU time	132.59 seconds
Started	Aug 10 07:40:53 PM PDT 24
Finished	Aug 10 07:43:06 PM PDT 24
Peak memory	260860 kb
Host	smart-8004d438-a561-438a-8909-a7b72894cc87
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941442167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o tp_reset.3941442167
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1328597450
Short name	T1048
Test name
Test status
Simulation time	137348900 ps
CPU time	29.11 seconds
Started	Aug 10 07:40:54 PM PDT 24
Finished	Aug 10 07:41:23 PM PDT 24
Peak memory	274312 kb
Host	smart-e196067d-f3ac-40c0-8181-e2e0a2ab6b78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328597450 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1328597450
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.1886757942
Short name	T555
Test name
Test status
Simulation time	8355357000 ps
CPU time	77.33 seconds
Started	Aug 10 07:40:59 PM PDT 24
Finished	Aug 10 07:42:16 PM PDT 24
Peak memory	265164 kb
Host	smart-a81158e7-90fe-480a-85ff-b215a76d4850
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886757942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1886757942
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.1987682629
Short name	T930
Test name
Test status
Simulation time	103643200 ps
CPU time	148.68 seconds
Started	Aug 10 07:40:54 PM PDT 24
Finished	Aug 10 07:43:22 PM PDT 24
Peak memory	277320 kb
Host	smart-d92c1d09-7dd7-4ba9-8b99-8d79daafeb59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987682629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1987682629
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.833120097
Short name	T1014
Test name
Test status
Simulation time	340334800 ps
CPU time	14.13 seconds
Started	Aug 10 07:41:04 PM PDT 24
Finished	Aug 10 07:41:18 PM PDT 24
Peak memory	258820 kb
Host	smart-e83f19a4-1a41-491a-86df-f79dd2176884
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833120097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.833120097
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.220845814
Short name	T811
Test name
Test status
Simulation time	37504900 ps
CPU time	13.57 seconds
Started	Aug 10 07:41:05 PM PDT 24
Finished	Aug 10 07:41:18 PM PDT 24
Peak memory	284848 kb
Host	smart-a6043ab8-468d-4be5-a815-a9be507995a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220845814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.220845814
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.2915973037
Short name	T992
Test name
Test status
Simulation time	56134600 ps
CPU time	22.01 seconds
Started	Aug 10 07:40:59 PM PDT 24
Finished	Aug 10 07:41:21 PM PDT 24
Peak memory	274228 kb
Host	smart-381b092c-0e0d-48c0-9bb1-10c4ee1e6a71
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915973037 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.2915973037
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3626343733
Short name	T934
Test name
Test status
Simulation time	2257597300 ps
CPU time	185.42 seconds
Started	Aug 10 07:40:59 PM PDT 24
Finished	Aug 10 07:44:05 PM PDT 24
Peak memory	263788 kb
Host	smart-a2623db7-5856-4c82-9743-cf793d96c23d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626343733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ hw_sec_otp.3626343733
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.3169138586
Short name	T697
Test name
Test status
Simulation time	3801196500 ps
CPU time	219.89 seconds
Started	Aug 10 07:40:58 PM PDT 24
Finished	Aug 10 07:44:38 PM PDT 24
Peak memory	286084 kb
Host	smart-2f0a73b7-8139-49a0-b268-755296042e37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169138586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.3169138586
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1190601909
Short name	T75
Test name
Test status
Simulation time	25299782200 ps
CPU time	279.01 seconds
Started	Aug 10 07:40:58 PM PDT 24
Finished	Aug 10 07:45:38 PM PDT 24
Peak memory	290528 kb
Host	smart-7980dba0-2991-4b28-9138-99381cff7515
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190601909 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1190601909
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.3666183000
Short name	T573
Test name
Test status
Simulation time	37112000 ps
CPU time	131.2 seconds
Started	Aug 10 07:41:01 PM PDT 24
Finished	Aug 10 07:43:12 PM PDT 24
Peak memory	265192 kb
Host	smart-12cc690f-32ba-4893-bc26-74fcaaa0d9c5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666183000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.3666183000
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2134827371
Short name	T322
Test name
Test status
Simulation time	83466200 ps
CPU time	31.41 seconds
Started	Aug 10 07:40:59 PM PDT 24
Finished	Aug 10 07:41:31 PM PDT 24
Peak memory	276336 kb
Host	smart-abe46be7-0794-43ce-aa16-112d008f8d6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134827371 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2134827371
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.3730953574
Short name	T33
Test name
Test status
Simulation time	1783491700 ps
CPU time	66.91 seconds
Started	Aug 10 07:41:05 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	264352 kb
Host	smart-03eaa88e-ec82-4d4a-b300-ca90939e2e33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730953574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3730953574
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.612903400
Short name	T1115
Test name
Test status
Simulation time	43062400 ps
CPU time	123.79 seconds
Started	Aug 10 07:41:01 PM PDT 24
Finished	Aug 10 07:43:05 PM PDT 24
Peak memory	270308 kb
Host	smart-77198336-5e82-4a51-8727-95d5ee8b6be2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=612903400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.612903400
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.472897568
Short name	T714
Test name
Test status
Simulation time	75152800 ps
CPU time	14.56 seconds
Started	Aug 10 07:41:12 PM PDT 24
Finished	Aug 10 07:41:27 PM PDT 24
Peak memory	258704 kb
Host	smart-ef948f0e-fc24-487a-981d-7cb676e5fc8b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472897568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.472897568
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.2467769439
Short name	T707
Test name
Test status
Simulation time	21377500 ps
CPU time	13.53 seconds
Started	Aug 10 07:41:12 PM PDT 24
Finished	Aug 10 07:41:26 PM PDT 24
Peak memory	283492 kb
Host	smart-d1d3d689-8c2c-4ff4-a854-f57033202d10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467769439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2467769439
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.2148452297
Short name	T191
Test name
Test status
Simulation time	15149000 ps
CPU time	20.6 seconds
Started	Aug 10 07:41:14 PM PDT 24
Finished	Aug 10 07:41:34 PM PDT 24
Peak memory	274236 kb
Host	smart-a55d98fd-adbb-43f2-bc1b-7e019e2a3db3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148452297 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.2148452297
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.4105171796
Short name	T528
Test name
Test status
Simulation time	8958100400 ps
CPU time	96.93 seconds
Started	Aug 10 07:41:04 PM PDT 24
Finished	Aug 10 07:42:41 PM PDT 24
Peak memory	261180 kb
Host	smart-58c379d6-ffd8-48e5-8ba8-4e8d2f9e902c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105171796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ hw_sec_otp.4105171796
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.1608964637
Short name	T997
Test name
Test status
Simulation time	2777670200 ps
CPU time	156.37 seconds
Started	Aug 10 07:41:06 PM PDT 24
Finished	Aug 10 07:43:42 PM PDT 24
Peak memory	286456 kb
Host	smart-0207a56c-5bde-406c-a669-7763f01a5ae3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608964637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.1608964637
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2411593765
Short name	T592
Test name
Test status
Simulation time	37132660800 ps
CPU time	219.68 seconds
Started	Aug 10 07:41:13 PM PDT 24
Finished	Aug 10 07:44:53 PM PDT 24
Peak memory	290504 kb
Host	smart-5c4c2ae4-3e8b-4fd4-bca5-567e28e75b46
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411593765 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2411593765
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.1663175494
Short name	T26
Test name
Test status
Simulation time	27532200 ps
CPU time	30.83 seconds
Started	Aug 10 07:41:13 PM PDT 24
Finished	Aug 10 07:41:44 PM PDT 24
Peak memory	276392 kb
Host	smart-a81960df-19d9-489d-82d4-faf205ba1751
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663175494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.1663175494
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3621658758
Short name	T1071
Test name
Test status
Simulation time	112887200 ps
CPU time	31.65 seconds
Started	Aug 10 07:41:14 PM PDT 24
Finished	Aug 10 07:41:46 PM PDT 24
Peak memory	274308 kb
Host	smart-874d416e-f275-43e6-b229-f0e4595bbb4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621658758 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3621658758
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.1939606116
Short name	T363
Test name
Test status
Simulation time	61735100 ps
CPU time	76.88 seconds
Started	Aug 10 07:41:04 PM PDT 24
Finished	Aug 10 07:42:21 PM PDT 24
Peak memory	276224 kb
Host	smart-0f69bcdb-b818-40ed-a8a2-0bde05e70163
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939606116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1939606116
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.2351285766
Short name	T610
Test name
Test status
Simulation time	126573500 ps
CPU time	13.59 seconds
Started	Aug 10 07:41:18 PM PDT 24
Finished	Aug 10 07:41:32 PM PDT 24
Peak memory	258796 kb
Host	smart-90f084a3-fff7-4f12-8778-3dac4bfa8f4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351285766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 2351285766
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.3697388369
Short name	T740
Test name
Test status
Simulation time	13332600 ps
CPU time	15.6 seconds
Started	Aug 10 07:41:17 PM PDT 24
Finished	Aug 10 07:41:32 PM PDT 24
Peak memory	284840 kb
Host	smart-36e4f264-e831-4ccf-8a77-70c0cd87ae64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697388369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3697388369
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.86469209
Short name	T936
Test name
Test status
Simulation time	17950300 ps
CPU time	22.43 seconds
Started	Aug 10 07:41:16 PM PDT 24
Finished	Aug 10 07:41:39 PM PDT 24
Peak memory	266232 kb
Host	smart-6d6a7a32-f9fa-4d32-a38e-38b6f46031e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86469209 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 33.flash_ctrl_disable.86469209
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.782892187
Short name	T289
Test name
Test status
Simulation time	3608991800 ps
CPU time	125.13 seconds
Started	Aug 10 07:41:13 PM PDT 24
Finished	Aug 10 07:43:18 PM PDT 24
Peak memory	264032 kb
Host	smart-43d36e04-ee3c-4935-adaa-227962079a1e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782892187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_h w_sec_otp.782892187
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.404201854
Short name	T829
Test name
Test status
Simulation time	4726180300 ps
CPU time	244.88 seconds
Started	Aug 10 07:41:13 PM PDT 24
Finished	Aug 10 07:45:18 PM PDT 24
Peak memory	285796 kb
Host	smart-15a6a837-6bb4-4bac-b226-7f162130267a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404201854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flas h_ctrl_intr_rd.404201854
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.386882862
Short name	T699
Test name
Test status
Simulation time	240112189500 ps
CPU time	489.64 seconds
Started	Aug 10 07:41:12 PM PDT 24
Finished	Aug 10 07:49:22 PM PDT 24
Peak memory	292760 kb
Host	smart-331998fd-bbe2-4b42-8dcc-72e0a4f6ca84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386882862 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.386882862
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.1851073528
Short name	T94
Test name
Test status
Simulation time	94865400 ps
CPU time	132.22 seconds
Started	Aug 10 07:41:14 PM PDT 24
Finished	Aug 10 07:43:26 PM PDT 24
Peak memory	260752 kb
Host	smart-e79c0cf0-4162-440d-bf55-3f75f7db51f1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851073528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.1851073528
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.4082746516
Short name	T1033
Test name
Test status
Simulation time	29959200 ps
CPU time	31.85 seconds
Started	Aug 10 07:41:12 PM PDT 24
Finished	Aug 10 07:41:44 PM PDT 24
Peak memory	276280 kb
Host	smart-7659fa40-c633-4382-817d-79b46e524aa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082746516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.4082746516
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2977263450
Short name	T805
Test name
Test status
Simulation time	29257600 ps
CPU time	31.43 seconds
Started	Aug 10 07:41:19 PM PDT 24
Finished	Aug 10 07:41:50 PM PDT 24
Peak memory	276344 kb
Host	smart-1b123169-ee33-4103-947c-b982880214ed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977263450 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2977263450
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.192418764
Short name	T381
Test name
Test status
Simulation time	1784352400 ps
CPU time	70.86 seconds
Started	Aug 10 07:41:15 PM PDT 24
Finished	Aug 10 07:42:26 PM PDT 24
Peak memory	264528 kb
Host	smart-1d01bce6-d59c-49e7-9b6a-c07142a927fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192418764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.192418764
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.2646488374
Short name	T46
Test name
Test status
Simulation time	114433100 ps
CPU time	73.9 seconds
Started	Aug 10 07:41:13 PM PDT 24
Finished	Aug 10 07:42:27 PM PDT 24
Peak memory	276388 kb
Host	smart-5911061b-878d-4798-a004-886c7fd187e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2646488374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.2646488374
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.4230098936
Short name	T16
Test name
Test status
Simulation time	33801400 ps
CPU time	13.69 seconds
Started	Aug 10 07:41:24 PM PDT 24
Finished	Aug 10 07:41:38 PM PDT 24
Peak memory	258716 kb
Host	smart-fdc230dc-7896-44ca-8059-0875dc9524d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230098936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test. 4230098936
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.2832528692
Short name	T468
Test name
Test status
Simulation time	13755300 ps
CPU time	16.44 seconds
Started	Aug 10 07:41:24 PM PDT 24
Finished	Aug 10 07:41:41 PM PDT 24
Peak memory	283616 kb
Host	smart-edd8b208-ec8b-4013-abc2-801e019b8d8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832528692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2832528692
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.263554053
Short name	T189
Test name
Test status
Simulation time	16504400 ps
CPU time	22.08 seconds
Started	Aug 10 07:41:19 PM PDT 24
Finished	Aug 10 07:41:41 PM PDT 24
Peak memory	274216 kb
Host	smart-5318ff8b-3507-418e-a65f-12620973eda8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263554053 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.263554053
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1250787574
Short name	T994
Test name
Test status
Simulation time	1502520400 ps
CPU time	65.41 seconds
Started	Aug 10 07:41:17 PM PDT 24
Finished	Aug 10 07:42:23 PM PDT 24
Peak memory	263356 kb
Host	smart-c594ec72-5ffc-46ed-9975-d083ac5a253d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250787574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ hw_sec_otp.1250787574
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.2403883037
Short name	T1013
Test name
Test status
Simulation time	7258803200 ps
CPU time	212.59 seconds
Started	Aug 10 07:41:17 PM PDT 24
Finished	Aug 10 07:44:49 PM PDT 24
Peak memory	285552 kb
Host	smart-47e8b5b8-b470-4a07-bdd9-64d9d3f5cf34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403883037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla sh_ctrl_intr_rd.2403883037
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1278255711
Short name	T900
Test name
Test status
Simulation time	91209846600 ps
CPU time	333.37 seconds
Started	Aug 10 07:41:16 PM PDT 24
Finished	Aug 10 07:46:49 PM PDT 24
Peak memory	285980 kb
Host	smart-0d05b3d3-2c12-4a24-8d94-2c6473bd2df5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278255711 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1278255711
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.3828199868
Short name	T552
Test name
Test status
Simulation time	40878200 ps
CPU time	133.12 seconds
Started	Aug 10 07:41:18 PM PDT 24
Finished	Aug 10 07:43:32 PM PDT 24
Peak memory	261488 kb
Host	smart-e8a751fc-c9d5-4180-aa6b-83b971806d42
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828199868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o tp_reset.3828199868
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict.2942696821
Short name	T1101
Test name
Test status
Simulation time	31852700 ps
CPU time	31.52 seconds
Started	Aug 10 07:41:16 PM PDT 24
Finished	Aug 10 07:41:48 PM PDT 24
Peak memory	276268 kb
Host	smart-e0e76976-49fe-4e23-beac-68e933c5b748
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942696821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl ash_ctrl_rw_evict.2942696821
Directory	/workspace/34.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.906577873
Short name	T599
Test name
Test status
Simulation time	8980050700 ps
CPU time	84.53 seconds
Started	Aug 10 07:41:24 PM PDT 24
Finished	Aug 10 07:42:49 PM PDT 24
Peak memory	263804 kb
Host	smart-5ce3d899-5472-4b02-a17b-12cbb1a16681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=906577873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.906577873
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.2896103502
Short name	T728
Test name
Test status
Simulation time	26351200 ps
CPU time	49.67 seconds
Started	Aug 10 07:41:17 PM PDT 24
Finished	Aug 10 07:42:07 PM PDT 24
Peak memory	271796 kb
Host	smart-50f2f640-845f-412d-a471-1e637df490c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896103502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2896103502
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.3392631117
Short name	T1002
Test name
Test status
Simulation time	18575100 ps
CPU time	13.25 seconds
Started	Aug 10 07:41:29 PM PDT 24
Finished	Aug 10 07:41:42 PM PDT 24
Peak memory	258884 kb
Host	smart-5ff4ee0f-f205-486f-89c7-d9527ab96af6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392631117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 3392631117
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.3023365068
Short name	T657
Test name
Test status
Simulation time	90353800 ps
CPU time	16.41 seconds
Started	Aug 10 07:41:28 PM PDT 24
Finished	Aug 10 07:41:44 PM PDT 24
Peak memory	284932 kb
Host	smart-b3a4f549-9716-4d01-976f-a2e3067e9ee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023365068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3023365068
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.2646960216
Short name	T360
Test name
Test status
Simulation time	15040100 ps
CPU time	22.23 seconds
Started	Aug 10 07:41:27 PM PDT 24
Finished	Aug 10 07:41:49 PM PDT 24
Peak memory	266900 kb
Host	smart-e7fb476d-1edd-40c1-a1be-72e4869ca663
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646960216 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.2646960216
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3992117528
Short name	T463
Test name
Test status
Simulation time	11911770900 ps
CPU time	100.67 seconds
Started	Aug 10 07:41:23 PM PDT 24
Finished	Aug 10 07:43:03 PM PDT 24
Peak memory	261124 kb
Host	smart-a1ff39ef-fc38-4852-a821-7ad752846615
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992117528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.3992117528
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.2151395820
Short name	T812
Test name
Test status
Simulation time	8004429400 ps
CPU time	204.7 seconds
Started	Aug 10 07:41:24 PM PDT 24
Finished	Aug 10 07:44:48 PM PDT 24
Peak memory	291628 kb
Host	smart-e64ef415-0ed8-48b7-a33f-d58a26f83ba7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151395820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.2151395820
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.20121525
Short name	T566
Test name
Test status
Simulation time	5933099100 ps
CPU time	169.42 seconds
Started	Aug 10 07:41:24 PM PDT 24
Finished	Aug 10 07:44:14 PM PDT 24
Peak memory	290588 kb
Host	smart-d9e39486-7a23-4729-898a-12365be72caf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.20121525
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.3897600449
Short name	T965
Test name
Test status
Simulation time	85245400 ps
CPU time	132.18 seconds
Started	Aug 10 07:41:23 PM PDT 24
Finished	Aug 10 07:43:36 PM PDT 24
Peak memory	261464 kb
Host	smart-0959e8fc-a203-48eb-bb7a-5082f183a105
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897600449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o tp_reset.3897600449
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.1432540591
Short name	T754
Test name
Test status
Simulation time	27841900 ps
CPU time	31.25 seconds
Started	Aug 10 07:41:24 PM PDT 24
Finished	Aug 10 07:41:55 PM PDT 24
Peak memory	275564 kb
Host	smart-335998eb-64f5-4361-ab6c-185dcacdf384
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432540591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.1432540591
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1968792750
Short name	T840
Test name
Test status
Simulation time	44423500 ps
CPU time	28.08 seconds
Started	Aug 10 07:41:27 PM PDT 24
Finished	Aug 10 07:41:55 PM PDT 24
Peak memory	274364 kb
Host	smart-967fa0d2-042a-412d-af9e-d8bcb0b4df5b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968792750 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1968792750
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.104450973
Short name	T963
Test name
Test status
Simulation time	1218510300 ps
CPU time	61.98 seconds
Started	Aug 10 07:41:29 PM PDT 24
Finished	Aug 10 07:42:31 PM PDT 24
Peak memory	263916 kb
Host	smart-38d98d42-34c6-4bd4-931e-52943ccc1e4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104450973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.104450973
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.1204849832
Short name	T782
Test name
Test status
Simulation time	47218200 ps
CPU time	76.56 seconds
Started	Aug 10 07:41:26 PM PDT 24
Finished	Aug 10 07:42:43 PM PDT 24
Peak memory	276240 kb
Host	smart-223c1dfb-6445-4079-b15f-2071fe7ee2b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204849832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1204849832
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.874096509
Short name	T743
Test name
Test status
Simulation time	54812500 ps
CPU time	13.94 seconds
Started	Aug 10 07:41:37 PM PDT 24
Finished	Aug 10 07:41:51 PM PDT 24
Peak memory	258660 kb
Host	smart-5850dece-a33c-4a0e-87f0-b4ce4d957080
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874096509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.874096509
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.3780934291
Short name	T845
Test name
Test status
Simulation time	18524500 ps
CPU time	15.71 seconds
Started	Aug 10 07:41:37 PM PDT 24
Finished	Aug 10 07:41:52 PM PDT 24
Peak memory	284880 kb
Host	smart-fb92f511-69c6-4493-952b-f4b822b00c69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780934291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3780934291
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.2698101476
Short name	T892
Test name
Test status
Simulation time	20907300 ps
CPU time	22.17 seconds
Started	Aug 10 07:41:31 PM PDT 24
Finished	Aug 10 07:41:53 PM PDT 24
Peak memory	274084 kb
Host	smart-08fd147e-b47f-4e17-966e-9f61b07c08a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698101476 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.2698101476
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.2803532872
Short name	T834
Test name
Test status
Simulation time	765976400 ps
CPU time	154.81 seconds
Started	Aug 10 07:41:30 PM PDT 24
Finished	Aug 10 07:44:04 PM PDT 24
Peak memory	292444 kb
Host	smart-4da05b15-b03c-41e3-b4ca-6901cd97bd93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803532872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.2803532872
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3230100415
Short name	T1078
Test name
Test status
Simulation time	23748503400 ps
CPU time	298.66 seconds
Started	Aug 10 07:41:27 PM PDT 24
Finished	Aug 10 07:46:26 PM PDT 24
Peak memory	292764 kb
Host	smart-7df74e1f-8afa-4b5b-9902-b9e750e8b6f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230100415 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3230100415
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.362804173
Short name	T859
Test name
Test status
Simulation time	308277700 ps
CPU time	31.23 seconds
Started	Aug 10 07:41:28 PM PDT 24
Finished	Aug 10 07:42:00 PM PDT 24
Peak memory	276356 kb
Host	smart-9af40fad-be43-47b1-8b71-0ecf1091f891
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362804173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_rw_evict.362804173
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.59874808
Short name	T161
Test name
Test status
Simulation time	28856900 ps
CPU time	31.5 seconds
Started	Aug 10 07:41:29 PM PDT 24
Finished	Aug 10 07:42:00 PM PDT 24
Peak memory	276332 kb
Host	smart-67c93ed2-ea96-4616-9c44-03e221e3d0f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59874808 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.59874808
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.1373065784
Short name	T1030
Test name
Test status
Simulation time	7795562900 ps
CPU time	72.84 seconds
Started	Aug 10 07:41:31 PM PDT 24
Finished	Aug 10 07:42:44 PM PDT 24
Peak memory	264512 kb
Host	smart-1f31d104-ee61-4f78-befb-b25ddeebb6de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373065784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1373065784
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.3921606672
Short name	T976
Test name
Test status
Simulation time	127804800 ps
CPU time	171.91 seconds
Started	Aug 10 07:41:31 PM PDT 24
Finished	Aug 10 07:44:23 PM PDT 24
Peak memory	277696 kb
Host	smart-b2883876-7aec-4187-979e-687a61af0b03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921606672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3921606672
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.172396152
Short name	T535
Test name
Test status
Simulation time	318913500 ps
CPU time	14.2 seconds
Started	Aug 10 07:41:39 PM PDT 24
Finished	Aug 10 07:41:54 PM PDT 24
Peak memory	265748 kb
Host	smart-c28e6023-317b-4ad4-9e7c-b9719639e83e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172396152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.172396152
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.3292131083
Short name	T687
Test name
Test status
Simulation time	40389500 ps
CPU time	13.41 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:41:48 PM PDT 24
Peak memory	284828 kb
Host	smart-c3fd1874-09fa-4748-8371-216a600b4a40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292131083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3292131083
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.2517732023
Short name	T958
Test name
Test status
Simulation time	17750800 ps
CPU time	22.38 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:41:57 PM PDT 24
Peak memory	274260 kb
Host	smart-18dfd9b6-ff08-4cd7-be1a-3fb2832e92e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517732023 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.2517732023
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1569412217
Short name	T470
Test name
Test status
Simulation time	3010676000 ps
CPU time	68.99 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:42:43 PM PDT 24
Peak memory	261296 kb
Host	smart-642b1521-3a67-47c9-9f1e-e93c42475752
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569412217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ hw_sec_otp.1569412217
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.343480957
Short name	T639
Test name
Test status
Simulation time	5549285000 ps
CPU time	219.25 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:45:13 PM PDT 24
Peak memory	285636 kb
Host	smart-16d02554-bd94-4358-acbc-de88efd21fac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343480957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas h_ctrl_intr_rd.343480957
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.4103765870
Short name	T977
Test name
Test status
Simulation time	23715976800 ps
CPU time	251.04 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:45:45 PM PDT 24
Peak memory	285992 kb
Host	smart-c8c9fc2f-0865-4716-8570-b01e2287a25b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103765870 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.4103765870
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.2052529671
Short name	T368
Test name
Test status
Simulation time	39520100 ps
CPU time	112.41 seconds
Started	Aug 10 07:41:35 PM PDT 24
Finished	Aug 10 07:43:28 PM PDT 24
Peak memory	260584 kb
Host	smart-b234425a-bf91-4c2f-82f6-f7489a34679e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052529671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o tp_reset.2052529671
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.2936415534
Short name	T830
Test name
Test status
Simulation time	66911600 ps
CPU time	32.14 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:42:06 PM PDT 24
Peak memory	274312 kb
Host	smart-a0c4d857-8002-4d88-83ad-b2966706f6ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936415534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.2936415534
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3456631175
Short name	T774
Test name
Test status
Simulation time	51295800 ps
CPU time	31.5 seconds
Started	Aug 10 07:41:36 PM PDT 24
Finished	Aug 10 07:42:07 PM PDT 24
Peak memory	274300 kb
Host	smart-29f3a074-7d1f-4b5e-81a2-e342f04ad5b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456631175 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3456631175
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.2699389557
Short name	T766
Test name
Test status
Simulation time	665957000 ps
CPU time	59.97 seconds
Started	Aug 10 07:41:34 PM PDT 24
Finished	Aug 10 07:42:34 PM PDT 24
Peak memory	264412 kb
Host	smart-3b80ad3e-1653-48d8-9c62-a1fbf4d9b833
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699389557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2699389557
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.712917336
Short name	T412
Test name
Test status
Simulation time	105805600 ps
CPU time	49.77 seconds
Started	Aug 10 07:41:35 PM PDT 24
Finished	Aug 10 07:42:25 PM PDT 24
Peak memory	271800 kb
Host	smart-a8d3d03f-52a9-4a74-9bed-ddd588135f1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712917336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.712917336
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.1760962302
Short name	T583
Test name
Test status
Simulation time	51236900 ps
CPU time	13.61 seconds
Started	Aug 10 07:41:41 PM PDT 24
Finished	Aug 10 07:41:55 PM PDT 24
Peak memory	265752 kb
Host	smart-ba057ff0-1970-4869-b050-8cae52b0752b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760962302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 1760962302
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.3437003765
Short name	T613
Test name
Test status
Simulation time	20590900 ps
CPU time	13.82 seconds
Started	Aug 10 07:41:42 PM PDT 24
Finished	Aug 10 07:41:56 PM PDT 24
Peak memory	283620 kb
Host	smart-0826a25a-2624-4668-b363-49974ea25a1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437003765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3437003765
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.1404190266
Short name	T118
Test name
Test status
Simulation time	21165900 ps
CPU time	20.68 seconds
Started	Aug 10 07:41:41 PM PDT 24
Finished	Aug 10 07:42:02 PM PDT 24
Peak memory	274288 kb
Host	smart-a2a69d85-b205-4f40-b8f8-6d1418a8e1f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404190266 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.1404190266
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2582074028
Short name	T294
Test name
Test status
Simulation time	7333619000 ps
CPU time	157.23 seconds
Started	Aug 10 07:41:40 PM PDT 24
Finished	Aug 10 07:44:17 PM PDT 24
Peak memory	261528 kb
Host	smart-f50e10ba-fb42-483e-8409-28a61682dc4d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582074028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.2582074028
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.1876441815
Short name	T665
Test name
Test status
Simulation time	6438656900 ps
CPU time	196.47 seconds
Started	Aug 10 07:41:41 PM PDT 24
Finished	Aug 10 07:44:58 PM PDT 24
Peak memory	291668 kb
Host	smart-c67ce4db-93af-4486-8c7a-d76ccae73fdb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876441815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.1876441815
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.886067167
Short name	T917
Test name
Test status
Simulation time	50134040400 ps
CPU time	153.61 seconds
Started	Aug 10 07:41:40 PM PDT 24
Finished	Aug 10 07:44:14 PM PDT 24
Peak memory	293592 kb
Host	smart-a7d40503-6149-48a3-94c6-095cded66abc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886067167 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.886067167
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.901673948
Short name	T126
Test name
Test status
Simulation time	94992400 ps
CPU time	131.81 seconds
Started	Aug 10 07:41:41 PM PDT 24
Finished	Aug 10 07:43:53 PM PDT 24
Peak memory	261512 kb
Host	smart-fc05f64f-bc59-4beb-9c5c-375b04ee749d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901673948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot p_reset.901673948
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.1629968930
Short name	T779
Test name
Test status
Simulation time	29200200 ps
CPU time	30.91 seconds
Started	Aug 10 07:41:39 PM PDT 24
Finished	Aug 10 07:42:10 PM PDT 24
Peak memory	276308 kb
Host	smart-4ad0d8eb-238f-47e0-b120-6cebbb672030
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629968930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl ash_ctrl_rw_evict.1629968930
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1662855947
Short name	T337
Test name
Test status
Simulation time	43209400 ps
CPU time	31.3 seconds
Started	Aug 10 07:41:41 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	274292 kb
Host	smart-8d197f1a-2cb1-4fb9-ba71-9d0f80f966b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662855947 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1662855947
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.1686259361
Short name	T727
Test name
Test status
Simulation time	2597546200 ps
CPU time	71.98 seconds
Started	Aug 10 07:41:39 PM PDT 24
Finished	Aug 10 07:42:52 PM PDT 24
Peak memory	264332 kb
Host	smart-90eb54dc-8ec7-48ca-a71c-36ff7ad7fd43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686259361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1686259361
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.3570433143
Short name	T501
Test name
Test status
Simulation time	27742100 ps
CPU time	172.48 seconds
Started	Aug 10 07:41:40 PM PDT 24
Finished	Aug 10 07:44:33 PM PDT 24
Peak memory	279524 kb
Host	smart-86263ac9-2ad8-4353-be90-587bc26b15f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570433143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3570433143
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.2721719922
Short name	T868
Test name
Test status
Simulation time	37275300 ps
CPU time	13.86 seconds
Started	Aug 10 07:41:52 PM PDT 24
Finished	Aug 10 07:42:06 PM PDT 24
Peak memory	265728 kb
Host	smart-1deb9240-bbc8-4646-b87e-4942c2542336
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721719922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 2721719922
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.3344653354
Short name	T399
Test name
Test status
Simulation time	46445100 ps
CPU time	13.56 seconds
Started	Aug 10 07:41:51 PM PDT 24
Finished	Aug 10 07:42:04 PM PDT 24
Peak memory	283552 kb
Host	smart-87544047-1f31-44b3-8118-9650e595b887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3344653354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3344653354
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.158846114
Short name	T1027
Test name
Test status
Simulation time	25185300 ps
CPU time	22.31 seconds
Started	Aug 10 07:41:52 PM PDT 24
Finished	Aug 10 07:42:15 PM PDT 24
Peak memory	274248 kb
Host	smart-efce6ee9-bc06-4e88-bea9-939d07ac107c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158846114 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.158846114
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.1783447502
Short name	T637
Test name
Test status
Simulation time	8487391700 ps
CPU time	124.26 seconds
Started	Aug 10 07:41:47 PM PDT 24
Finished	Aug 10 07:43:51 PM PDT 24
Peak memory	261148 kb
Host	smart-6b204de0-2e24-4cb8-8be0-e190f4d5e3d5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783447502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ hw_sec_otp.1783447502
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.2182544158
Short name	T486
Test name
Test status
Simulation time	8255498100 ps
CPU time	252.44 seconds
Started	Aug 10 07:41:46 PM PDT 24
Finished	Aug 10 07:45:58 PM PDT 24
Peak memory	285760 kb
Host	smart-db05004f-01ef-4440-aa2b-fa66e079b4e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182544158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.2182544158
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1399456362
Short name	T867
Test name
Test status
Simulation time	11694150400 ps
CPU time	131.73 seconds
Started	Aug 10 07:41:46 PM PDT 24
Finished	Aug 10 07:43:58 PM PDT 24
Peak memory	293476 kb
Host	smart-49d6682d-348a-4877-9c55-6b4208845c44
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399456362 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1399456362
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.1160581511
Short name	T651
Test name
Test status
Simulation time	37448800 ps
CPU time	111.65 seconds
Started	Aug 10 07:41:45 PM PDT 24
Finished	Aug 10 07:43:37 PM PDT 24
Peak memory	260528 kb
Host	smart-afc50183-cf13-4777-86df-bd7ed4258809
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160581511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o tp_reset.1160581511
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.3190058527
Short name	T664
Test name
Test status
Simulation time	80451300 ps
CPU time	31.73 seconds
Started	Aug 10 07:41:47 PM PDT 24
Finished	Aug 10 07:42:18 PM PDT 24
Peak memory	274264 kb
Host	smart-5b07b3d7-05f6-46b8-9e9f-01d960519137
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190058527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl ash_ctrl_rw_evict.3190058527
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.4130382232
Short name	T416
Test name
Test status
Simulation time	45693500 ps
CPU time	31.14 seconds
Started	Aug 10 07:41:45 PM PDT 24
Finished	Aug 10 07:42:17 PM PDT 24
Peak memory	274368 kb
Host	smart-285a0470-3f3f-4bc6-b214-7bea348bb073
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130382232 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.4130382232
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.446466757
Short name	T469
Test name
Test status
Simulation time	15490043600 ps
CPU time	82.65 seconds
Started	Aug 10 07:41:52 PM PDT 24
Finished	Aug 10 07:43:15 PM PDT 24
Peak memory	264176 kb
Host	smart-a37be884-5a29-4d90-a682-579866cb3b70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446466757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.446466757
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.476682665
Short name	T532
Test name
Test status
Simulation time	33123100 ps
CPU time	75.93 seconds
Started	Aug 10 07:41:45 PM PDT 24
Finished	Aug 10 07:43:01 PM PDT 24
Peak memory	277192 kb
Host	smart-12d2c8ba-c18b-4685-9353-74c195127502
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476682665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.476682665
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.404802577
Short name	T548
Test name
Test status
Simulation time	92350200 ps
CPU time	13.9 seconds
Started	Aug 10 07:35:23 PM PDT 24
Finished	Aug 10 07:35:37 PM PDT 24
Peak memory	258788 kb
Host	smart-7378dc0e-8f32-4fc2-8ec7-6cbfc812e4e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404802577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.404802577
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.667431458
Short name	T350
Test name
Test status
Simulation time	60779300 ps
CPU time	14 seconds
Started	Aug 10 07:35:18 PM PDT 24
Finished	Aug 10 07:35:32 PM PDT 24
Peak memory	262204 kb
Host	smart-1b4be6c9-b688-40a4-8f0d-ffcee8e47d38
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667431458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. flash_ctrl_config_regwen.667431458
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.822790484
Short name	T906
Test name
Test status
Simulation time	40474600 ps
CPU time	15.95 seconds
Started	Aug 10 07:35:21 PM PDT 24
Finished	Aug 10 07:35:37 PM PDT 24
Peak memory	275492 kb
Host	smart-69e5563b-60a2-48f4-90c3-3ce62d8488bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822790484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.822790484
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_derr_detect.1181747915
Short name	T240
Test name
Test status
Simulation time	1351581900 ps
CPU time	200.26 seconds
Started	Aug 10 07:35:18 PM PDT 24
Finished	Aug 10 07:38:38 PM PDT 24
Peak memory	281892 kb
Host	smart-44711d1c-6040-4327-b4dc-471bfa38c095
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181747915 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.1181747915
Directory	/workspace/4.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.570157047
Short name	T12
Test name
Test status
Simulation time	20377100 ps
CPU time	20.95 seconds
Started	Aug 10 07:35:22 PM PDT 24
Finished	Aug 10 07:35:43 PM PDT 24
Peak memory	274316 kb
Host	smart-89356b77-1fce-403d-adb0-2b5eda6147ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570157047 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.570157047
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.1145897988
Short name	T861
Test name
Test status
Simulation time	9963900200 ps
CPU time	2485.69 seconds
Started	Aug 10 07:35:05 PM PDT 24
Finished	Aug 10 08:16:31 PM PDT 24
Peak memory	263412 kb
Host	smart-afb2cc80-5eec-48b4-b94b-1e656bbb39da
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1145897988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.1145897988
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.1066518446
Short name	T109
Test name
Test status
Simulation time	3013461500 ps
CPU time	2864.68 seconds
Started	Aug 10 07:35:05 PM PDT 24
Finished	Aug 10 08:22:50 PM PDT 24
Peak memory	262736 kb
Host	smart-c248d5e1-bdf6-4589-8e84-363c421e4cbb
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066518446 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1066518446
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.3875514205
Short name	T849
Test name
Test status
Simulation time	600921500 ps
CPU time	742.54 seconds
Started	Aug 10 07:35:05 PM PDT 24
Finished	Aug 10 07:47:27 PM PDT 24
Peak memory	271164 kb
Host	smart-100e80ca-7302-4863-99b9-31de11a35ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875514205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3875514205
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.3378997739
Short name	T397
Test name
Test status
Simulation time	709026500 ps
CPU time	27.61 seconds
Started	Aug 10 07:35:00 PM PDT 24
Finished	Aug 10 07:35:28 PM PDT 24
Peak memory	264244 kb
Host	smart-8d54755a-8520-462f-ac0a-152aa332c772
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378997739 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.3378997739
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.2046932995
Short name	T333
Test name
Test status
Simulation time	340057900 ps
CPU time	40.47 seconds
Started	Aug 10 07:35:17 PM PDT 24
Finished	Aug 10 07:35:57 PM PDT 24
Peak memory	265528 kb
Host	smart-4ac4a4fa-f651-4f9e-b047-1c466f801102
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046932995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.2046932995
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.3550222325
Short name	T80
Test name
Test status
Simulation time	203478800000 ps
CPU time	4447.74 seconds
Started	Aug 10 07:35:00 PM PDT 24
Finished	Aug 10 08:49:09 PM PDT 24
Peak memory	265692 kb
Host	smart-f2ba9651-2870-488b-b49c-86a92439fb1a
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550222325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.3550222325
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.3423622186
Short name	T804
Test name
Test status
Simulation time	37205800 ps
CPU time	38.26 seconds
Started	Aug 10 07:34:58 PM PDT 24
Finished	Aug 10 07:35:37 PM PDT 24
Peak memory	263288 kb
Host	smart-455d9089-d158-4d41-ad2a-9c18a035c982
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3423622186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3423622186
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.649737541
Short name	T269
Test name
Test status
Simulation time	10032086900 ps
CPU time	59.81 seconds
Started	Aug 10 07:35:24 PM PDT 24
Finished	Aug 10 07:36:24 PM PDT 24
Peak memory	272484 kb
Host	smart-321c9ecc-00e6-4b3e-9d83-97085ad391f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649737541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.649737541
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1500535840
Short name	T314
Test name
Test status
Simulation time	45619000 ps
CPU time	13.64 seconds
Started	Aug 10 07:35:23 PM PDT 24
Finished	Aug 10 07:35:36 PM PDT 24
Peak memory	265272 kb
Host	smart-8bbff8fb-5055-4efe-b4fb-bebc080b05d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500535840 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1500535840
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1003463802
Short name	T296
Test name
Test status
Simulation time	40124188100 ps
CPU time	838.86 seconds
Started	Aug 10 07:35:01 PM PDT 24
Finished	Aug 10 07:49:00 PM PDT 24
Peak memory	261396 kb
Host	smart-7c898058-c21f-4148-a4d1-d1c48c3816b1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003463802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.1003463802
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3548732092
Short name	T661
Test name
Test status
Simulation time	589410400 ps
CPU time	31.07 seconds
Started	Aug 10 07:35:00 PM PDT 24
Finished	Aug 10 07:35:31 PM PDT 24
Peak memory	261316 kb
Host	smart-72171b81-53d0-427a-b59c-20744f14ce4c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548732092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.3548732092
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.3532341319
Short name	T388
Test name
Test status
Simulation time	14535738000 ps
CPU time	542.58 seconds
Started	Aug 10 07:35:10 PM PDT 24
Finished	Aug 10 07:44:13 PM PDT 24
Peak memory	334676 kb
Host	smart-748ac5d0-1580-4b3c-9bd3-43da804b7166
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532341319 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.3532341319
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.4227537934
Short name	T923
Test name
Test status
Simulation time	673410300 ps
CPU time	130.68 seconds
Started	Aug 10 07:35:11 PM PDT 24
Finished	Aug 10 07:37:22 PM PDT 24
Peak memory	294968 kb
Host	smart-571d3592-874b-465d-8ca0-03c87f7174a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227537934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_intr_rd.4227537934
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1658466983
Short name	T308
Test name
Test status
Simulation time	17012954300 ps
CPU time	264.23 seconds
Started	Aug 10 07:35:21 PM PDT 24
Finished	Aug 10 07:39:45 PM PDT 24
Peak memory	294896 kb
Host	smart-547a5b68-10a3-4f43-a127-b4ef0ccab2bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658466983 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.1658466983
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.4219673566
Short name	T856
Test name
Test status
Simulation time	4339524800 ps
CPU time	72.06 seconds
Started	Aug 10 07:35:11 PM PDT 24
Finished	Aug 10 07:36:23 PM PDT 24
Peak memory	261272 kb
Host	smart-76782bb7-a78b-4e81-b828-0910d4911878
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219673566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_wr.4219673566
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.664576202
Short name	T667
Test name
Test status
Simulation time	79596719400 ps
CPU time	174.6 seconds
Started	Aug 10 07:35:12 PM PDT 24
Finished	Aug 10 07:38:07 PM PDT 24
Peak memory	260908 kb
Host	smart-02950a6b-4d61-45ee-886d-b121a7d90b5d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664 576202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.664576202
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.4270765944
Short name	T1044
Test name
Test status
Simulation time	974496200 ps
CPU time	76.75 seconds
Started	Aug 10 07:35:05 PM PDT 24
Finished	Aug 10 07:36:22 PM PDT 24
Peak memory	261280 kb
Host	smart-60f9d43e-7db0-4c09-a602-456f211e4c63
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270765944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.4270765944
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3782674000
Short name	T477
Test name
Test status
Simulation time	48910200 ps
CPU time	13.49 seconds
Started	Aug 10 07:35:25 PM PDT 24
Finished	Aug 10 07:35:39 PM PDT 24
Peak memory	260836 kb
Host	smart-f5dedaf6-0385-4163-bc28-6e7272224c7e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782674000 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3782674000
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.749006973
Short name	T73
Test name
Test status
Simulation time	3818964300 ps
CPU time	73.24 seconds
Started	Aug 10 07:35:15 PM PDT 24
Finished	Aug 10 07:36:28 PM PDT 24
Peak memory	261076 kb
Host	smart-1e471fa8-861a-49e2-8c72-59d7f5193d62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749006973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.749006973
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.1354466894
Short name	T905
Test name
Test status
Simulation time	53170800 ps
CPU time	109.64 seconds
Started	Aug 10 07:35:03 PM PDT 24
Finished	Aug 10 07:36:52 PM PDT 24
Peak memory	260928 kb
Host	smart-9e94dfa6-0780-4988-81e5-50c3588db79b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354466894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot p_reset.1354466894
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3168712834
Short name	T62
Test name
Test status
Simulation time	15944400 ps
CPU time	14.09 seconds
Started	Aug 10 07:35:20 PM PDT 24
Finished	Aug 10 07:35:35 PM PDT 24
Peak memory	277620 kb
Host	smart-b3b9e70b-4ff5-4f83-bf6b-ce027c98f31e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3168712834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3168712834
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.1737339089
Short name	T460
Test name
Test status
Simulation time	87991100 ps
CPU time	154.74 seconds
Started	Aug 10 07:35:01 PM PDT 24
Finished	Aug 10 07:37:36 PM PDT 24
Peak memory	263704 kb
Host	smart-0766dfdb-6f27-4363-a4b1-82a586b84c68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1737339089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1737339089
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1630235056
Short name	T162
Test name
Test status
Simulation time	865695400 ps
CPU time	17.93 seconds
Started	Aug 10 07:35:18 PM PDT 24
Finished	Aug 10 07:35:36 PM PDT 24
Peak memory	263732 kb
Host	smart-dead634d-8ba5-448d-8bc2-004ba9e24289
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630235056 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1630235056
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.457357579
Short name	T215
Test name
Test status
Simulation time	121147600 ps
CPU time	14.39 seconds
Started	Aug 10 07:35:22 PM PDT 24
Finished	Aug 10 07:35:36 PM PDT 24
Peak memory	263536 kb
Host	smart-91345468-d13b-479c-af03-b4c7233106ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457357579 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.457357579
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.45819722
Short name	T776
Test name
Test status
Simulation time	21857900 ps
CPU time	13.71 seconds
Started	Aug 10 07:35:19 PM PDT 24
Finished	Aug 10 07:35:33 PM PDT 24
Peak memory	265736 kb
Host	smart-9a64b675-9cee-4acd-adc3-9fcf5e5dd3c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45819722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_prog_reset.45819722
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.483373343
Short name	T1008
Test name
Test status
Simulation time	82145300 ps
CPU time	597.8 seconds
Started	Aug 10 07:35:02 PM PDT 24
Finished	Aug 10 07:45:00 PM PDT 24
Peak memory	283364 kb
Host	smart-1bb0a798-7a98-487d-8575-8b0e98970f16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=483373343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.483373343
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1265757302
Short name	T915
Test name
Test status
Simulation time	1407640600 ps
CPU time	132.09 seconds
Started	Aug 10 07:35:02 PM PDT 24
Finished	Aug 10 07:37:14 PM PDT 24
Peak memory	263332 kb
Host	smart-e7bf9bb9-6722-4507-9163-7aea454a7718
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1265757302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1265757302
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.351174074
Short name	T903
Test name
Test status
Simulation time	507472200 ps
CPU time	35.52 seconds
Started	Aug 10 07:35:20 PM PDT 24
Finished	Aug 10 07:35:56 PM PDT 24
Peak memory	274256 kb
Host	smart-281272fd-ebbe-429e-a781-7bc73ff2a45d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351174074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_re_evict.351174074
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3115388906
Short name	T767
Test name
Test status
Simulation time	58725900 ps
CPU time	22.69 seconds
Started	Aug 10 07:35:12 PM PDT 24
Finished	Aug 10 07:35:35 PM PDT 24
Peak memory	266088 kb
Host	smart-11c3c16f-d315-4995-90a0-ab438ad40636
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115388906 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3115388906
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.160731925
Short name	T499
Test name
Test status
Simulation time	44543100 ps
CPU time	22.75 seconds
Started	Aug 10 07:35:05 PM PDT 24
Finished	Aug 10 07:35:28 PM PDT 24
Peak memory	266020 kb
Host	smart-b3fbf974-6cc8-4ff3-abce-7a01cdf9f494
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160731925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_read_word_sweep_serr.160731925
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.1450130424
Short name	T111
Test name
Test status
Simulation time	2374458600 ps
CPU time	127.79 seconds
Started	Aug 10 07:35:07 PM PDT 24
Finished	Aug 10 07:37:15 PM PDT 24
Peak memory	291980 kb
Host	smart-59a1cd53-1af2-45b3-8d00-555f14f87590
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450130424 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_ro.1450130424
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.2838660993
Short name	T167
Test name
Test status
Simulation time	7735007700 ps
CPU time	137.97 seconds
Started	Aug 10 07:35:12 PM PDT 24
Finished	Aug 10 07:37:30 PM PDT 24
Peak memory	282568 kb
Host	smart-e708dfcb-2091-4b6b-9aa8-3ccea3bc2104
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2838660993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2838660993
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.1953154402
Short name	T824
Test name
Test status
Simulation time	1789924700 ps
CPU time	124.17 seconds
Started	Aug 10 07:35:06 PM PDT 24
Finished	Aug 10 07:37:11 PM PDT 24
Peak memory	295864 kb
Host	smart-d108b0d9-1f42-49d2-90f3-78c739d2c50d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953154402 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1953154402
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.958665307
Short name	T640
Test name
Test status
Simulation time	4837476400 ps
CPU time	531.31 seconds
Started	Aug 10 07:35:06 PM PDT 24
Finished	Aug 10 07:43:57 PM PDT 24
Peak memory	310440 kb
Host	smart-e808f45d-a455-428d-b1ab-d8ab52194cee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958665307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.958665307
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_derr.654458641
Short name	T703
Test name
Test status
Simulation time	6551451900 ps
CPU time	265.96 seconds
Started	Aug 10 07:35:17 PM PDT 24
Finished	Aug 10 07:39:44 PM PDT 24
Peak memory	292368 kb
Host	smart-30092089-889f-4456-9b6a-dc74a88b2c77
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654458641 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_derr.654458641
Directory	/workspace/4.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3389590638
Short name	T464
Test name
Test status
Simulation time	39647800 ps
CPU time	29.11 seconds
Started	Aug 10 07:35:18 PM PDT 24
Finished	Aug 10 07:35:48 PM PDT 24
Peak memory	276288 kb
Host	smart-f093fafe-fcc8-4101-95ad-deb7c2125e07
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389590638 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3389590638
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_serr.684160153
Short name	T946
Test name
Test status
Simulation time	2513149800 ps
CPU time	197.89 seconds
Started	Aug 10 07:35:07 PM PDT 24
Finished	Aug 10 07:38:25 PM PDT 24
Peak memory	282544 kb
Host	smart-149217ef-bb38-4e1b-9956-8a93d10a00af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684160153 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_rw_serr.684160153
Directory	/workspace/4.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.4115232647
Short name	T14
Test name
Test status
Simulation time	1011867700 ps
CPU time	4994.18 seconds
Started	Aug 10 07:35:22 PM PDT 24
Finished	Aug 10 08:58:37 PM PDT 24
Peak memory	287608 kb
Host	smart-441439fa-ae5d-46aa-a644-09fbe0f4bc44
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115232647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.4115232647
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.350403670
Short name	T513
Test name
Test status
Simulation time	5454219000 ps
CPU time	68.94 seconds
Started	Aug 10 07:35:20 PM PDT 24
Finished	Aug 10 07:36:29 PM PDT 24
Peak memory	264492 kb
Host	smart-0cfe170b-59cd-445b-919f-86b41ac064e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350403670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.350403670
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.1339803279
Short name	T673
Test name
Test status
Simulation time	4200812700 ps
CPU time	79.54 seconds
Started	Aug 10 07:35:04 PM PDT 24
Finished	Aug 10 07:36:24 PM PDT 24
Peak memory	274276 kb
Host	smart-fd0e002d-ea7a-4fbd-b28c-2ad267a484e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339803279 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_address.1339803279
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.3306224278
Short name	T962
Test name
Test status
Simulation time	1069963600 ps
CPU time	83.45 seconds
Started	Aug 10 07:35:16 PM PDT 24
Finished	Aug 10 07:36:40 PM PDT 24
Peak memory	274412 kb
Host	smart-ce46dd31-f8ec-4940-98f7-e14aec966b08
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306224278 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.3306224278
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.852849541
Short name	T428
Test name
Test status
Simulation time	307726500 ps
CPU time	105.79 seconds
Started	Aug 10 07:34:54 PM PDT 24
Finished	Aug 10 07:36:40 PM PDT 24
Peak memory	276580 kb
Host	smart-11edcd02-7ef8-4a4d-897c-a0aa410e1da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852849541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.852849541
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.1436695196
Short name	T825
Test name
Test status
Simulation time	51227900 ps
CPU time	26.25 seconds
Started	Aug 10 07:35:01 PM PDT 24
Finished	Aug 10 07:35:28 PM PDT 24
Peak memory	260328 kb
Host	smart-b4537801-0474-46fb-88d2-d58c97b8c2c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436695196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1436695196
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.1604322776
Short name	T502
Test name
Test status
Simulation time	924629100 ps
CPU time	1205.87 seconds
Started	Aug 10 07:35:19 PM PDT 24
Finished	Aug 10 07:55:25 PM PDT 24
Peak memory	290408 kb
Host	smart-49241ba6-b4cb-4a43-852b-88944235f0be
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604322776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.1604322776
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.2210466331
Short name	T770
Test name
Test status
Simulation time	89024300 ps
CPU time	26.45 seconds
Started	Aug 10 07:34:59 PM PDT 24
Finished	Aug 10 07:35:26 PM PDT 24
Peak memory	260328 kb
Host	smart-8971e6c2-b077-45cc-9aea-fc231a42e9cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2210466331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2210466331
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.2259275740
Short name	T263
Test name
Test status
Simulation time	12871003500 ps
CPU time	179.42 seconds
Started	Aug 10 07:35:05 PM PDT 24
Finished	Aug 10 07:38:04 PM PDT 24
Peak memory	260628 kb
Host	smart-31575067-f888-4c3c-ab90-93d6e0ae19b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259275740 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.2259275740
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.2118498807
Short name	T576
Test name
Test status
Simulation time	51050200 ps
CPU time	14.2 seconds
Started	Aug 10 07:41:53 PM PDT 24
Finished	Aug 10 07:42:07 PM PDT 24
Peak memory	258704 kb
Host	smart-0a0aa187-4e18-4411-8755-b4262c361f5a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118498807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 2118498807
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.345734163
Short name	T361
Test name
Test status
Simulation time	40999400 ps
CPU time	16.08 seconds
Started	Aug 10 07:41:55 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	284916 kb
Host	smart-57b58d33-79f9-4289-81a0-e2bc365651cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345734163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.345734163
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.4292295118
Short name	T374
Test name
Test status
Simulation time	11301600 ps
CPU time	21.89 seconds
Started	Aug 10 07:41:52 PM PDT 24
Finished	Aug 10 07:42:14 PM PDT 24
Peak memory	274260 kb
Host	smart-0cc19df9-f48f-4938-90a8-8ac995c990d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292295118 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.4292295118
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1173503392
Short name	T272
Test name
Test status
Simulation time	1693566000 ps
CPU time	61.45 seconds
Started	Aug 10 07:41:52 PM PDT 24
Finished	Aug 10 07:42:54 PM PDT 24
Peak memory	263928 kb
Host	smart-96e43be1-5b67-4485-9d6c-c7a1282ea18e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173503392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ hw_sec_otp.1173503392
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.2780106367
Short name	T769
Test name
Test status
Simulation time	146453900 ps
CPU time	131.09 seconds
Started	Aug 10 07:41:53 PM PDT 24
Finished	Aug 10 07:44:04 PM PDT 24
Peak memory	260720 kb
Host	smart-91f57706-863f-49db-b6cb-7e1a7f580a3f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780106367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o tp_reset.2780106367
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.290561747
Short name	T488
Test name
Test status
Simulation time	2022502200 ps
CPU time	62.04 seconds
Started	Aug 10 07:41:55 PM PDT 24
Finished	Aug 10 07:42:57 PM PDT 24
Peak memory	263924 kb
Host	smart-bb16bf39-8d27-4001-9084-57dafaec8651
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290561747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.290561747
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.4203043021
Short name	T960
Test name
Test status
Simulation time	30200800 ps
CPU time	172.65 seconds
Started	Aug 10 07:41:54 PM PDT 24
Finished	Aug 10 07:44:47 PM PDT 24
Peak memory	280224 kb
Host	smart-2afa0d74-753a-403f-9686-2baf044a75bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4203043021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.4203043021
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.1376551243
Short name	T409
Test name
Test status
Simulation time	65910400 ps
CPU time	14.05 seconds
Started	Aug 10 07:41:58 PM PDT 24
Finished	Aug 10 07:42:13 PM PDT 24
Peak memory	258796 kb
Host	smart-b89b2685-393f-484f-9e55-1e9d3c451e0e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376551243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 1376551243
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.879251648
Short name	T523
Test name
Test status
Simulation time	15040300 ps
CPU time	15.76 seconds
Started	Aug 10 07:41:57 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	284948 kb
Host	smart-0e2fbd8a-c154-4f78-8494-b79675ed678c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879251648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.879251648
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.2408568478
Short name	T190
Test name
Test status
Simulation time	17586200 ps
CPU time	22.49 seconds
Started	Aug 10 07:41:58 PM PDT 24
Finished	Aug 10 07:42:21 PM PDT 24
Peak memory	274124 kb
Host	smart-cb9e6b56-3c97-4f69-9bd9-c12f190f56ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408568478 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.2408568478
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3235176590
Short name	T285
Test name
Test status
Simulation time	11879452500 ps
CPU time	200.55 seconds
Started	Aug 10 07:41:51 PM PDT 24
Finished	Aug 10 07:45:12 PM PDT 24
Peak memory	261504 kb
Host	smart-7734171b-8659-4665-8c3f-f63983ca9cf5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235176590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.3235176590
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.4202662123
Short name	T1020
Test name
Test status
Simulation time	75300700 ps
CPU time	111.27 seconds
Started	Aug 10 07:42:01 PM PDT 24
Finished	Aug 10 07:43:52 PM PDT 24
Peak memory	260732 kb
Host	smart-3a5d3aaa-574f-4446-9a75-be49555e4617
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202662123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o tp_reset.4202662123
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.800035264
Short name	T1010
Test name
Test status
Simulation time	1404403200 ps
CPU time	65.86 seconds
Started	Aug 10 07:41:58 PM PDT 24
Finished	Aug 10 07:43:04 PM PDT 24
Peak memory	264812 kb
Host	smart-ee80a4de-fca9-4630-a143-4831c18d39b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800035264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.800035264
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.2487860716
Short name	T627
Test name
Test status
Simulation time	106704600 ps
CPU time	149.49 seconds
Started	Aug 10 07:41:54 PM PDT 24
Finished	Aug 10 07:44:24 PM PDT 24
Peak memory	270640 kb
Host	smart-a4756d57-d571-4432-889f-53a58cff4a8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487860716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2487860716
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.1203487322
Short name	T403
Test name
Test status
Simulation time	48097500 ps
CPU time	13.96 seconds
Started	Aug 10 07:41:58 PM PDT 24
Finished	Aug 10 07:42:12 PM PDT 24
Peak memory	258668 kb
Host	smart-8625f5f9-ecb9-48ad-8201-7f43e60f49a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203487322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 1203487322
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.3570424383
Short name	T570
Test name
Test status
Simulation time	63607200 ps
CPU time	15.77 seconds
Started	Aug 10 07:42:02 PM PDT 24
Finished	Aug 10 07:42:18 PM PDT 24
Peak memory	283660 kb
Host	smart-7fa61118-897f-4097-9fa0-73808ae707d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570424383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3570424383
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.1069250915
Short name	T1076
Test name
Test status
Simulation time	16635300 ps
CPU time	22.39 seconds
Started	Aug 10 07:41:57 PM PDT 24
Finished	Aug 10 07:42:19 PM PDT 24
Peak memory	275476 kb
Host	smart-56052c0a-a708-47d9-9aea-81b2b2013b09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069250915 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.1069250915
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2962476144
Short name	T292
Test name
Test status
Simulation time	11523867200 ps
CPU time	108.39 seconds
Started	Aug 10 07:41:58 PM PDT 24
Finished	Aug 10 07:43:46 PM PDT 24
Peak memory	263436 kb
Host	smart-3f6687d1-64ee-4b3c-9722-9bd9a6b160df
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962476144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_ hw_sec_otp.2962476144
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.3521030833
Short name	T908
Test name
Test status
Simulation time	132496200 ps
CPU time	131.39 seconds
Started	Aug 10 07:41:57 PM PDT 24
Finished	Aug 10 07:44:09 PM PDT 24
Peak memory	264284 kb
Host	smart-53c1b8d0-37de-436e-953a-93386f589233
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521030833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.3521030833
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.1187449323
Short name	T688
Test name
Test status
Simulation time	801575800 ps
CPU time	59.13 seconds
Started	Aug 10 07:41:58 PM PDT 24
Finished	Aug 10 07:42:57 PM PDT 24
Peak memory	264856 kb
Host	smart-853f099f-7d7e-4d14-a21c-2912789a7498
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187449323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1187449323
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.7701495
Short name	T1018
Test name
Test status
Simulation time	25723000 ps
CPU time	102.3 seconds
Started	Aug 10 07:41:59 PM PDT 24
Finished	Aug 10 07:43:41 PM PDT 24
Peak memory	276732 kb
Host	smart-f42778c9-f3c8-4410-ba24-cc619ef4ab41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=7701495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.7701495
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.3247883628
Short name	T866
Test name
Test status
Simulation time	87797400 ps
CPU time	13.86 seconds
Started	Aug 10 07:42:02 PM PDT 24
Finished	Aug 10 07:42:16 PM PDT 24
Peak memory	258808 kb
Host	smart-846b7412-0bef-4ce2-8fa0-15b29d3928f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247883628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 3247883628
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.416682558
Short name	T832
Test name
Test status
Simulation time	26054400 ps
CPU time	13.35 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:42:17 PM PDT 24
Peak memory	284780 kb
Host	smart-c0e7ddd6-50c0-4309-97ab-3ef988753b6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416682558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.416682558
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.3100930390
Short name	T1046
Test name
Test status
Simulation time	15890800 ps
CPU time	22.48 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:42:26 PM PDT 24
Peak memory	274312 kb
Host	smart-3786abdb-01d8-4bcb-a467-63e269577ce8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100930390 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.3100930390
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1665357242
Short name	T831
Test name
Test status
Simulation time	431313300 ps
CPU time	47.22 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:42:50 PM PDT 24
Peak memory	263876 kb
Host	smart-ffd6e0d7-cdaa-4390-becd-aba60c684b5c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665357242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.1665357242
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.2417740414
Short name	T686
Test name
Test status
Simulation time	452519600 ps
CPU time	132.84 seconds
Started	Aug 10 07:42:02 PM PDT 24
Finished	Aug 10 07:44:15 PM PDT 24
Peak memory	265332 kb
Host	smart-4a7846a9-95f8-4cae-b688-aea14f7330c2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417740414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.2417740414
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.1584534572
Short name	T1098
Test name
Test status
Simulation time	614695800 ps
CPU time	63.52 seconds
Started	Aug 10 07:42:04 PM PDT 24
Finished	Aug 10 07:43:07 PM PDT 24
Peak memory	264376 kb
Host	smart-86c0dcff-0157-4173-b345-6b3fbaca6151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584534572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1584534572
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.1990163283
Short name	T41
Test name
Test status
Simulation time	154597500 ps
CPU time	125.24 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:44:08 PM PDT 24
Peak memory	277168 kb
Host	smart-742e1a4c-c22f-4ff3-b2e5-f0f52695d016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990163283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1990163283
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.1153940442
Short name	T625
Test name
Test status
Simulation time	31503200 ps
CPU time	13.74 seconds
Started	Aug 10 07:42:01 PM PDT 24
Finished	Aug 10 07:42:15 PM PDT 24
Peak memory	258788 kb
Host	smart-7f54712a-7e4a-4093-ab43-9b6cfda49c0b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153940442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test. 1153940442
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.140914530
Short name	T662
Test name
Test status
Simulation time	17275800 ps
CPU time	16.14 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:42:19 PM PDT 24
Peak memory	284928 kb
Host	smart-8ff3d139-b534-4635-8013-40a59b0d674a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140914530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.140914530
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.2764529177
Short name	T3
Test name
Test status
Simulation time	12842800 ps
CPU time	22.32 seconds
Started	Aug 10 07:42:02 PM PDT 24
Finished	Aug 10 07:42:25 PM PDT 24
Peak memory	274092 kb
Host	smart-d5dbd9d7-515e-4325-ab98-440078e2534e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764529177 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.2764529177
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3371829343
Short name	T505
Test name
Test status
Simulation time	2084675700 ps
CPU time	52.67 seconds
Started	Aug 10 07:42:02 PM PDT 24
Finished	Aug 10 07:42:55 PM PDT 24
Peak memory	261296 kb
Host	smart-471cfbd4-9313-4125-90bc-913a7749f1ec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371829343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.3371829343
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.3592845479
Short name	T820
Test name
Test status
Simulation time	43794000 ps
CPU time	132.36 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:44:15 PM PDT 24
Peak memory	260924 kb
Host	smart-82a92558-662e-437b-ae8e-a5231bccf236
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592845479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o tp_reset.3592845479
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.440081924
Short name	T424
Test name
Test status
Simulation time	741205100 ps
CPU time	75 seconds
Started	Aug 10 07:42:03 PM PDT 24
Finished	Aug 10 07:43:18 PM PDT 24
Peak memory	265412 kb
Host	smart-9b906579-02b5-4bcc-8a09-51ff780cb516
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440081924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.440081924
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.2110781387
Short name	T745
Test name
Test status
Simulation time	38646500 ps
CPU time	176.96 seconds
Started	Aug 10 07:42:04 PM PDT 24
Finished	Aug 10 07:45:01 PM PDT 24
Peak memory	277596 kb
Host	smart-bc155e55-98e9-4116-9b6e-9725212d8428
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110781387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2110781387
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.3774293336
Short name	T631
Test name
Test status
Simulation time	73592800 ps
CPU time	13.94 seconds
Started	Aug 10 07:42:09 PM PDT 24
Finished	Aug 10 07:42:23 PM PDT 24
Peak memory	258804 kb
Host	smart-4f155824-15b9-4dfc-b12f-258c94f66919
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774293336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test. 3774293336
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.3607781711
Short name	T1067
Test name
Test status
Simulation time	13173300 ps
CPU time	13.48 seconds
Started	Aug 10 07:42:07 PM PDT 24
Finished	Aug 10 07:42:21 PM PDT 24
Peak memory	284952 kb
Host	smart-9be2d2ef-cc42-469d-b6c9-4b158cb50420
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607781711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3607781711
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.363645470
Short name	T354
Test name
Test status
Simulation time	19649000 ps
CPU time	21.89 seconds
Started	Aug 10 07:42:08 PM PDT 24
Finished	Aug 10 07:42:30 PM PDT 24
Peak memory	274232 kb
Host	smart-d36765ff-bc1c-4533-ae4b-0f350bc0a16d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363645470 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.363645470
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1067132006
Short name	T972
Test name
Test status
Simulation time	3716621600 ps
CPU time	67.88 seconds
Started	Aug 10 07:42:11 PM PDT 24
Finished	Aug 10 07:43:19 PM PDT 24
Peak memory	261292 kb
Host	smart-13607c3b-81fd-4b3b-a7dc-1eec420931e9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067132006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.1067132006
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.2581961659
Short name	T450
Test name
Test status
Simulation time	72516300 ps
CPU time	110.33 seconds
Started	Aug 10 07:42:08 PM PDT 24
Finished	Aug 10 07:43:59 PM PDT 24
Peak memory	260768 kb
Host	smart-f29516db-7af0-427d-bb78-bf97f7a37a52
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581961659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.2581961659
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.2081758224
Short name	T376
Test name
Test status
Simulation time	6364866500 ps
CPU time	77.35 seconds
Started	Aug 10 07:42:09 PM PDT 24
Finished	Aug 10 07:43:27 PM PDT 24
Peak memory	263456 kb
Host	smart-de1466b7-16bc-4189-998e-65d2bfc11700
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081758224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2081758224
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.1104225079
Short name	T751
Test name
Test status
Simulation time	677557500 ps
CPU time	105.73 seconds
Started	Aug 10 07:42:10 PM PDT 24
Finished	Aug 10 07:43:56 PM PDT 24
Peak memory	281884 kb
Host	smart-212a2fa5-0963-4346-8220-a171da6ef936
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104225079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1104225079
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.3489902279
Short name	T1091
Test name
Test status
Simulation time	34191400 ps
CPU time	13.55 seconds
Started	Aug 10 07:42:16 PM PDT 24
Finished	Aug 10 07:42:29 PM PDT 24
Peak memory	258704 kb
Host	smart-68b7ff4c-3430-44be-a2ac-fb50ade89ba9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489902279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test. 3489902279
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.2600513189
Short name	T500
Test name
Test status
Simulation time	15337600 ps
CPU time	13.76 seconds
Started	Aug 10 07:42:14 PM PDT 24
Finished	Aug 10 07:42:27 PM PDT 24
Peak memory	284888 kb
Host	smart-b325221f-6fe4-4873-a327-f9f0845c090f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600513189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2600513189
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.3880985560
Short name	T763
Test name
Test status
Simulation time	27090700 ps
CPU time	23 seconds
Started	Aug 10 07:42:08 PM PDT 24
Finished	Aug 10 07:42:31 PM PDT 24
Peak memory	274216 kb
Host	smart-06c81f48-0e59-4713-a24b-924f988688a0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880985560 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.3880985560
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.852147220
Short name	T455
Test name
Test status
Simulation time	21205953000 ps
CPU time	192.21 seconds
Started	Aug 10 07:42:07 PM PDT 24
Finished	Aug 10 07:45:19 PM PDT 24
Peak memory	263384 kb
Host	smart-bd33b397-bf55-405c-a2f7-30b28f8d0aa3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852147220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h w_sec_otp.852147220
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.399469814
Short name	T83
Test name
Test status
Simulation time	157468500 ps
CPU time	131.21 seconds
Started	Aug 10 07:42:09 PM PDT 24
Finished	Aug 10 07:44:20 PM PDT 24
Peak memory	261604 kb
Host	smart-991ecfcb-e5b4-468a-a389-5e0875e97e16
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399469814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot p_reset.399469814
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.2068025612
Short name	T138
Test name
Test status
Simulation time	466473500 ps
CPU time	61.3 seconds
Started	Aug 10 07:42:17 PM PDT 24
Finished	Aug 10 07:43:18 PM PDT 24
Peak memory	265452 kb
Host	smart-f9ee3347-dcc7-49f9-aaa2-a5e10f4524dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068025612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2068025612
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.1996719863
Short name	T457
Test name
Test status
Simulation time	36165700 ps
CPU time	76.97 seconds
Started	Aug 10 07:42:08 PM PDT 24
Finished	Aug 10 07:43:25 PM PDT 24
Peak memory	277324 kb
Host	smart-b0a49bac-dff4-42a4-bb5b-b6096b1dfb44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1996719863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1996719863
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.3070939300
Short name	T833
Test name
Test status
Simulation time	49525100 ps
CPU time	13.7 seconds
Started	Aug 10 07:42:14 PM PDT 24
Finished	Aug 10 07:42:28 PM PDT 24
Peak memory	258768 kb
Host	smart-85ff4586-1cf4-4947-a1a8-daee165835a1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070939300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 3070939300
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.1623973389
Short name	T736
Test name
Test status
Simulation time	15599900 ps
CPU time	15.81 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:42:36 PM PDT 24
Peak memory	283292 kb
Host	smart-ad52e7de-8d0a-4007-9385-0060fff77e73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623973389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.1623973389
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.3027935885
Short name	T1060
Test name
Test status
Simulation time	35383200 ps
CPU time	22.37 seconds
Started	Aug 10 07:42:17 PM PDT 24
Finished	Aug 10 07:42:39 PM PDT 24
Peak memory	274108 kb
Host	smart-75e67d53-0bbc-4fb3-be14-969bdf7e9387
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027935885 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.3027935885
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.841396444
Short name	T1114
Test name
Test status
Simulation time	22860329000 ps
CPU time	157.1 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:44:57 PM PDT 24
Peak memory	263980 kb
Host	smart-2eec4aa0-b075-42b0-ac1a-0a3015a14700
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841396444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_h w_sec_otp.841396444
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.3698141322
Short name	T183
Test name
Test status
Simulation time	71944200 ps
CPU time	132.22 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:44:33 PM PDT 24
Peak memory	260564 kb
Host	smart-f6919b3f-ea0a-4a1d-b61d-9fa3de23cc55
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698141322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o tp_reset.3698141322
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.3455692599
Short name	T433
Test name
Test status
Simulation time	66643700 ps
CPU time	194.41 seconds
Started	Aug 10 07:42:14 PM PDT 24
Finished	Aug 10 07:45:29 PM PDT 24
Peak memory	279584 kb
Host	smart-b6c64fc1-11df-47b7-9f99-83d79d337259
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455692599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3455692599
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.1973054186
Short name	T1012
Test name
Test status
Simulation time	33531600 ps
CPU time	13.72 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:42:34 PM PDT 24
Peak memory	258804 kb
Host	smart-deff8e72-8b3c-4e5c-bdee-218989703f48
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973054186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test. 1973054186
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.2302069932
Short name	T546
Test name
Test status
Simulation time	27216700 ps
CPU time	13.43 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:42:34 PM PDT 24
Peak memory	284900 kb
Host	smart-728a15d3-dedb-44dc-a548-0bf2a4537d4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2302069932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2302069932
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.1324627006
Short name	T748
Test name
Test status
Simulation time	35619100 ps
CPU time	20.61 seconds
Started	Aug 10 07:42:22 PM PDT 24
Finished	Aug 10 07:42:43 PM PDT 24
Peak memory	274092 kb
Host	smart-df0b71dd-2cb1-4a5a-9228-0b6e64243685
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324627006 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.1324627006
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.758702123
Short name	T848
Test name
Test status
Simulation time	4552893200 ps
CPU time	98.73 seconds
Started	Aug 10 07:42:14 PM PDT 24
Finished	Aug 10 07:43:53 PM PDT 24
Peak memory	261640 kb
Host	smart-a0724a9b-ed73-4602-b827-9e9702296dd7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758702123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h w_sec_otp.758702123
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.1478755575
Short name	T1100
Test name
Test status
Simulation time	227670500 ps
CPU time	129.97 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:44:30 PM PDT 24
Peak memory	263704 kb
Host	smart-5bd8df1a-6ffc-470f-b05c-a83de4a3b581
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478755575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o tp_reset.1478755575
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.1732469201
Short name	T385
Test name
Test status
Simulation time	2162599600 ps
CPU time	66.98 seconds
Started	Aug 10 07:42:21 PM PDT 24
Finished	Aug 10 07:43:28 PM PDT 24
Peak memory	264480 kb
Host	smart-1ff5e568-9dcd-4ba0-91a9-958ec9e19544
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732469201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1732469201
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.4222920420
Short name	T449
Test name
Test status
Simulation time	45952200 ps
CPU time	123.82 seconds
Started	Aug 10 07:42:16 PM PDT 24
Finished	Aug 10 07:44:20 PM PDT 24
Peak memory	276796 kb
Host	smart-a062637c-b696-45dc-8982-678e9b52a0d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222920420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.4222920420
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.2548477075
Short name	T809
Test name
Test status
Simulation time	21401000 ps
CPU time	13.56 seconds
Started	Aug 10 07:42:26 PM PDT 24
Finished	Aug 10 07:42:40 PM PDT 24
Peak memory	258984 kb
Host	smart-20337c09-ca45-4b98-8faa-94a96147007b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548477075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test. 2548477075
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.3413576339
Short name	T413
Test name
Test status
Simulation time	93666700 ps
CPU time	13.46 seconds
Started	Aug 10 07:42:27 PM PDT 24
Finished	Aug 10 07:42:41 PM PDT 24
Peak memory	284884 kb
Host	smart-192e2074-1b84-45eb-bfdb-c5effd279eda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413576339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3413576339
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.396186364
Short name	T1073
Test name
Test status
Simulation time	15391300 ps
CPU time	21.93 seconds
Started	Aug 10 07:42:20 PM PDT 24
Finished	Aug 10 07:42:42 PM PDT 24
Peak memory	274024 kb
Host	smart-ff4cd27d-be1a-42a9-8da2-649e97a4ceb3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396186364 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.396186364
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3427905514
Short name	T288
Test name
Test status
Simulation time	2906815300 ps
CPU time	233.71 seconds
Started	Aug 10 07:42:21 PM PDT 24
Finished	Aug 10 07:46:15 PM PDT 24
Peak memory	263496 kb
Host	smart-d3437d45-6dd2-4a4c-8fac-f61ddac13f29
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427905514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ hw_sec_otp.3427905514
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.3045056021
Short name	T541
Test name
Test status
Simulation time	40880300 ps
CPU time	130.36 seconds
Started	Aug 10 07:42:21 PM PDT 24
Finished	Aug 10 07:44:32 PM PDT 24
Peak memory	260520 kb
Host	smart-375b810d-bed2-4f6b-a534-86bfdd6adf02
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045056021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.3045056021
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.962686602
Short name	T141
Test name
Test status
Simulation time	5819377300 ps
CPU time	83.16 seconds
Started	Aug 10 07:42:26 PM PDT 24
Finished	Aug 10 07:43:49 PM PDT 24
Peak memory	264396 kb
Host	smart-48c1f725-14ab-45f4-8d1a-4cc2138fce37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962686602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.962686602
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.1497469239
Short name	T701
Test name
Test status
Simulation time	25709600 ps
CPU time	174.04 seconds
Started	Aug 10 07:42:21 PM PDT 24
Finished	Aug 10 07:45:15 PM PDT 24
Peak memory	278916 kb
Host	smart-9f85ac84-6c54-4ca8-ae07-6dab92045c47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1497469239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1497469239
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.290902355
Short name	T1042
Test name
Test status
Simulation time	355763500 ps
CPU time	13.88 seconds
Started	Aug 10 07:35:47 PM PDT 24
Finished	Aug 10 07:36:01 PM PDT 24
Peak memory	258708 kb
Host	smart-77020e56-208e-463e-864e-5097485d35be
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290902355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.290902355
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.4078586196
Short name	T579
Test name
Test status
Simulation time	23810000 ps
CPU time	13.65 seconds
Started	Aug 10 07:35:47 PM PDT 24
Finished	Aug 10 07:36:01 PM PDT 24
Peak memory	284868 kb
Host	smart-a22b8900-9684-4d06-bf0e-6ea3a1a0c7c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078586196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.4078586196
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.2521913600
Short name	T373
Test name
Test status
Simulation time	19113200 ps
CPU time	22.29 seconds
Started	Aug 10 07:35:48 PM PDT 24
Finished	Aug 10 07:36:11 PM PDT 24
Peak memory	267156 kb
Host	smart-e057f298-ac85-4e65-9630-17313106fab6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521913600 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.2521913600
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.2438345489
Short name	T220
Test name
Test status
Simulation time	20176020400 ps
CPU time	2266.59 seconds
Started	Aug 10 07:35:28 PM PDT 24
Finished	Aug 10 08:13:15 PM PDT 24
Peak memory	265788 kb
Host	smart-386c12f5-7d50-4d15-a543-fd5f8b0bd781
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2438345489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.2438345489
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.260161703
Short name	T274
Test name
Test status
Simulation time	310573400 ps
CPU time	761.55 seconds
Started	Aug 10 07:35:35 PM PDT 24
Finished	Aug 10 07:48:16 PM PDT 24
Peak memory	271096 kb
Host	smart-6a8c2912-3735-4207-a61f-efbcb9721f74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260161703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.260161703
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.263166249
Short name	T1054
Test name
Test status
Simulation time	491593800 ps
CPU time	25.39 seconds
Started	Aug 10 07:35:31 PM PDT 24
Finished	Aug 10 07:35:57 PM PDT 24
Peak memory	264404 kb
Host	smart-7aba9830-e18f-4aaf-bef9-7981c3946d3f
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263166249 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.263166249
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1654250818
Short name	T785
Test name
Test status
Simulation time	10033230200 ps
CPU time	55.06 seconds
Started	Aug 10 07:35:47 PM PDT 24
Finished	Aug 10 07:36:42 PM PDT 24
Peak memory	272436 kb
Host	smart-f410e538-ccb7-4862-8f05-a6d9dfafadb2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654250818 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1654250818
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.3881254374
Short name	T139
Test name
Test status
Simulation time	15227700 ps
CPU time	13.73 seconds
Started	Aug 10 07:35:48 PM PDT 24
Finished	Aug 10 07:36:02 PM PDT 24
Peak memory	265756 kb
Host	smart-82128f92-af39-4577-bf4f-63d64fa4f0fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881254374 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3881254374
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.951851346
Short name	T799
Test name
Test status
Simulation time	80141380700 ps
CPU time	869.95 seconds
Started	Aug 10 07:35:30 PM PDT 24
Finished	Aug 10 07:50:00 PM PDT 24
Peak memory	264884 kb
Host	smart-88aa22cb-9386-40be-8c4b-f2719f98765f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951851346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.flash_ctrl_hw_rma_reset.951851346
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2170306112
Short name	T136
Test name
Test status
Simulation time	21660460500 ps
CPU time	183.93 seconds
Started	Aug 10 07:35:23 PM PDT 24
Finished	Aug 10 07:38:27 PM PDT 24
Peak memory	263936 kb
Host	smart-711a40fb-0647-4f3e-8969-7fba2e28a715
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170306112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h w_sec_otp.2170306112
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.2054441128
Short name	T1080
Test name
Test status
Simulation time	13778582300 ps
CPU time	146.49 seconds
Started	Aug 10 07:35:35 PM PDT 24
Finished	Aug 10 07:38:02 PM PDT 24
Peak memory	294772 kb
Host	smart-b02af956-c383-4998-939b-bb698a662d19
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054441128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_intr_rd.2054441128
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3654515864
Short name	T446
Test name
Test status
Simulation time	12200673400 ps
CPU time	311.63 seconds
Started	Aug 10 07:35:35 PM PDT 24
Finished	Aug 10 07:40:47 PM PDT 24
Peak memory	292764 kb
Host	smart-2c7ccf0d-3d32-48ca-b9ba-5403329714cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654515864 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3654515864
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.2107161362
Short name	T590
Test name
Test status
Simulation time	2550151700 ps
CPU time	71.62 seconds
Started	Aug 10 07:35:34 PM PDT 24
Finished	Aug 10 07:36:46 PM PDT 24
Peak memory	265836 kb
Host	smart-e0a47a4c-a54b-4d68-a821-b3467dd30979
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107161362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_wr.2107161362
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.4188701857
Short name	T517
Test name
Test status
Simulation time	109870809300 ps
CPU time	222.46 seconds
Started	Aug 10 07:35:43 PM PDT 24
Finished	Aug 10 07:39:25 PM PDT 24
Peak memory	261144 kb
Host	smart-ddd67885-dbec-417e-bf5e-7284dc3e99ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418 8701857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.4188701857
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.2970735499
Short name	T1111
Test name
Test status
Simulation time	16176012600 ps
CPU time	82.21 seconds
Started	Aug 10 07:35:29 PM PDT 24
Finished	Aug 10 07:36:52 PM PDT 24
Peak memory	263740 kb
Host	smart-a5bd1504-daaf-4f05-9b32-36fab4a1df11
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970735499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2970735499
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1189566604
Short name	T614
Test name
Test status
Simulation time	47336500 ps
CPU time	13.7 seconds
Started	Aug 10 07:35:49 PM PDT 24
Finished	Aug 10 07:36:03 PM PDT 24
Peak memory	260708 kb
Host	smart-28af004b-5cc1-4567-86ab-af7b12ca778f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189566604 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1189566604
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.176949724
Short name	T641
Test name
Test status
Simulation time	4729925400 ps
CPU time	220.61 seconds
Started	Aug 10 07:35:29 PM PDT 24
Finished	Aug 10 07:39:10 PM PDT 24
Peak memory	265808 kb
Host	smart-55f2e635-8067-4f1b-b854-88624ff92d46
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176949724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.176949724
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.4244258730
Short name	T700
Test name
Test status
Simulation time	15440727200 ps
CPU time	540.18 seconds
Started	Aug 10 07:35:26 PM PDT 24
Finished	Aug 10 07:44:26 PM PDT 24
Peak memory	263684 kb
Host	smart-2a9dd8f9-f540-4abf-b86d-53ac1a213d1e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4244258730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.4244258730
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.3961690405
Short name	T467
Test name
Test status
Simulation time	72456700 ps
CPU time	13.76 seconds
Started	Aug 10 07:35:45 PM PDT 24
Finished	Aug 10 07:35:59 PM PDT 24
Peak memory	259932 kb
Host	smart-22e9a4f8-ccd0-4d70-96ee-b06cb7e79108
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961690405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_prog_reset.3961690405
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.3076843500
Short name	T1016
Test name
Test status
Simulation time	469929600 ps
CPU time	760.84 seconds
Started	Aug 10 07:35:24 PM PDT 24
Finished	Aug 10 07:48:06 PM PDT 24
Peak memory	284796 kb
Host	smart-be3316b9-7aab-49d4-a5e8-e422c524fa65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076843500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3076843500
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.1069618269
Short name	T1022
Test name
Test status
Simulation time	69288300 ps
CPU time	35.42 seconds
Started	Aug 10 07:35:44 PM PDT 24
Finished	Aug 10 07:36:19 PM PDT 24
Peak memory	276620 kb
Host	smart-a9e76006-8cb3-4579-9c55-ed7f13b569f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069618269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.1069618269
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.3563605562
Short name	T705
Test name
Test status
Simulation time	702947100 ps
CPU time	112.64 seconds
Started	Aug 10 07:35:30 PM PDT 24
Finished	Aug 10 07:37:23 PM PDT 24
Peak memory	282384 kb
Host	smart-c925f3b4-010a-47a1-aa26-e2f0e4692e34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563605562 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.3563605562
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.3944325835
Short name	T20
Test name
Test status
Simulation time	664546700 ps
CPU time	150.93 seconds
Started	Aug 10 07:35:41 PM PDT 24
Finished	Aug 10 07:38:12 PM PDT 24
Peak memory	296108 kb
Host	smart-918b27c5-35d9-4188-a72b-672d7028d874
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944325835 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3944325835
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.1819989301
Short name	T874
Test name
Test status
Simulation time	8261771800 ps
CPU time	515.87 seconds
Started	Aug 10 07:35:39 PM PDT 24
Finished	Aug 10 07:44:15 PM PDT 24
Peak memory	310664 kb
Host	smart-a29c4618-6822-4307-b455-97ae4d709a99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819989301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.flash_ctrl_rw.1819989301
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_derr.3330135451
Short name	T578
Test name
Test status
Simulation time	9775550400 ps
CPU time	241.23 seconds
Started	Aug 10 07:35:36 PM PDT 24
Finished	Aug 10 07:39:37 PM PDT 24
Peak memory	292360 kb
Host	smart-35ba33dc-1051-48f4-9a15-58e80626f818
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330135451 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_derr.3330135451
Directory	/workspace/5.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_serr.1274786934
Short name	T114
Test name
Test status
Simulation time	1574131300 ps
CPU time	219.74 seconds
Started	Aug 10 07:35:35 PM PDT 24
Finished	Aug 10 07:39:15 PM PDT 24
Peak memory	282576 kb
Host	smart-e7516702-bb0f-45a5-85e0-2c5e2a3348d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274786934 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.flash_ctrl_rw_serr.1274786934
Directory	/workspace/5.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.3085494403
Short name	T375
Test name
Test status
Simulation time	1932056500 ps
CPU time	68.7 seconds
Started	Aug 10 07:35:46 PM PDT 24
Finished	Aug 10 07:36:55 PM PDT 24
Peak memory	264380 kb
Host	smart-d16ce070-dfea-4f12-96d7-4fbaa46cb9d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085494403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3085494403
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.3452614635
Short name	T496
Test name
Test status
Simulation time	53806800 ps
CPU time	219.95 seconds
Started	Aug 10 07:35:23 PM PDT 24
Finished	Aug 10 07:39:03 PM PDT 24
Peak memory	279672 kb
Host	smart-7be012ee-0808-44f2-a93b-aaabed99ec79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452614635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.3452614635
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.4095014933
Short name	T881
Test name
Test status
Simulation time	2195483300 ps
CPU time	180.2 seconds
Started	Aug 10 07:35:30 PM PDT 24
Finished	Aug 10 07:38:30 PM PDT 24
Peak memory	259960 kb
Host	smart-c88ddaa6-3ff6-4a3f-a81c-0f3e59e731ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095014933 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.flash_ctrl_wo.4095014933
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.3535423618
Short name	T515
Test name
Test status
Simulation time	40304100 ps
CPU time	16.19 seconds
Started	Aug 10 07:42:28 PM PDT 24
Finished	Aug 10 07:42:44 PM PDT 24
Peak memory	283600 kb
Host	smart-b549b45e-d5e1-4f5b-8a62-91a7935baf0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535423618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3535423618
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.1797722830
Short name	T601
Test name
Test status
Simulation time	39989500 ps
CPU time	133.91 seconds
Started	Aug 10 07:42:25 PM PDT 24
Finished	Aug 10 07:44:39 PM PDT 24
Peak memory	261760 kb
Host	smart-083652bc-de3c-471f-a66d-9a9d65af0c8d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797722830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o tp_reset.1797722830
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.2491587558
Short name	T764
Test name
Test status
Simulation time	21393300 ps
CPU time	15.61 seconds
Started	Aug 10 07:42:27 PM PDT 24
Finished	Aug 10 07:42:43 PM PDT 24
Peak memory	283672 kb
Host	smart-fc1eb3c7-def1-4970-9ede-c678531915a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491587558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2491587558
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.567575367
Short name	T443
Test name
Test status
Simulation time	138598200 ps
CPU time	131.08 seconds
Started	Aug 10 07:42:26 PM PDT 24
Finished	Aug 10 07:44:37 PM PDT 24
Peak memory	260628 kb
Host	smart-b6f905d5-1281-49d5-80e9-e55a38294296
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567575367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_ot p_reset.567575367
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.3311818684
Short name	T904
Test name
Test status
Simulation time	16841900 ps
CPU time	16.01 seconds
Started	Aug 10 07:42:28 PM PDT 24
Finished	Aug 10 07:42:44 PM PDT 24
Peak memory	283560 kb
Host	smart-41e113a0-fac2-4bbc-88f2-b6e036da58ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3311818684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3311818684
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.2478007820
Short name	T173
Test name
Test status
Simulation time	289405900 ps
CPU time	132.22 seconds
Started	Aug 10 07:42:27 PM PDT 24
Finished	Aug 10 07:44:40 PM PDT 24
Peak memory	260512 kb
Host	smart-9224e649-115d-421b-abe5-6ae6c2807884
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478007820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o tp_reset.2478007820
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.2509763875
Short name	T746
Test name
Test status
Simulation time	51052300 ps
CPU time	16.18 seconds
Started	Aug 10 07:42:28 PM PDT 24
Finished	Aug 10 07:42:45 PM PDT 24
Peak memory	283612 kb
Host	smart-926fe2e3-ee03-4e7c-bdf3-a854725acde8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2509763875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2509763875
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.920507129
Short name	T180
Test name
Test status
Simulation time	101990200 ps
CPU time	132.1 seconds
Started	Aug 10 07:42:28 PM PDT 24
Finished	Aug 10 07:44:40 PM PDT 24
Peak memory	265336 kb
Host	smart-d75b7be9-99da-44d1-bcce-f7403362b8b9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920507129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot p_reset.920507129
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.3348504633
Short name	T1011
Test name
Test status
Simulation time	51869200 ps
CPU time	15.91 seconds
Started	Aug 10 07:42:26 PM PDT 24
Finished	Aug 10 07:42:43 PM PDT 24
Peak memory	284792 kb
Host	smart-6b0c15af-91e5-464b-a4aa-e59b6f5d2c28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348504633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3348504633
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.4037459713
Short name	T813
Test name
Test status
Simulation time	72915500 ps
CPU time	111.1 seconds
Started	Aug 10 07:42:26 PM PDT 24
Finished	Aug 10 07:44:17 PM PDT 24
Peak memory	264640 kb
Host	smart-af73d8b2-d944-4e47-a787-fa308c0b2d3f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037459713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.4037459713
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.634794008
Short name	T563
Test name
Test status
Simulation time	15148400 ps
CPU time	15.9 seconds
Started	Aug 10 07:42:32 PM PDT 24
Finished	Aug 10 07:42:48 PM PDT 24
Peak memory	283552 kb
Host	smart-fb7fcc3f-cdd4-4383-8973-6c6c7c33399c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634794008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.634794008
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.2213013594
Short name	T635
Test name
Test status
Simulation time	60632000 ps
CPU time	133.39 seconds
Started	Aug 10 07:42:34 PM PDT 24
Finished	Aug 10 07:44:47 PM PDT 24
Peak memory	261608 kb
Host	smart-17f19a86-4875-403e-9b78-5f8451967041
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213013594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.2213013594
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.4195979722
Short name	T425
Test name
Test status
Simulation time	22771300 ps
CPU time	15.8 seconds
Started	Aug 10 07:42:33 PM PDT 24
Finished	Aug 10 07:42:49 PM PDT 24
Peak memory	283636 kb
Host	smart-7ce44438-f807-487b-a42f-913785900daa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195979722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.4195979722
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.2300398303
Short name	T1028
Test name
Test status
Simulation time	78853900 ps
CPU time	130.21 seconds
Started	Aug 10 07:42:34 PM PDT 24
Finished	Aug 10 07:44:44 PM PDT 24
Peak memory	260724 kb
Host	smart-6d04f677-8427-4125-8af5-47338c76cde5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300398303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o tp_reset.2300398303
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.451344900
Short name	T507
Test name
Test status
Simulation time	13326100 ps
CPU time	15.94 seconds
Started	Aug 10 07:42:31 PM PDT 24
Finished	Aug 10 07:42:48 PM PDT 24
Peak memory	283600 kb
Host	smart-f764e54f-a399-4058-bc3e-ce700ea9d907
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451344900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.451344900
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.615491479
Short name	T370
Test name
Test status
Simulation time	669724500 ps
CPU time	109.85 seconds
Started	Aug 10 07:42:34 PM PDT 24
Finished	Aug 10 07:44:24 PM PDT 24
Peak memory	265696 kb
Host	smart-b80c9200-bfbe-4e6f-b2ab-b678171e1107
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615491479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot p_reset.615491479
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.2383173246
Short name	T851
Test name
Test status
Simulation time	26417700 ps
CPU time	15.98 seconds
Started	Aug 10 07:42:32 PM PDT 24
Finished	Aug 10 07:42:48 PM PDT 24
Peak memory	284748 kb
Host	smart-2f3ee468-a865-4bbe-b6c9-ad048271ee1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383173246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2383173246
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.1874603347
Short name	T753
Test name
Test status
Simulation time	39336300 ps
CPU time	112.59 seconds
Started	Aug 10 07:42:35 PM PDT 24
Finished	Aug 10 07:44:27 PM PDT 24
Peak memory	260564 kb
Host	smart-cbbd6708-4931-4668-a045-b3d61ed9b05a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874603347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.1874603347
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.361577478
Short name	T602
Test name
Test status
Simulation time	16015900 ps
CPU time	13.32 seconds
Started	Aug 10 07:42:32 PM PDT 24
Finished	Aug 10 07:42:46 PM PDT 24
Peak memory	283648 kb
Host	smart-c3c58b72-d05f-4c37-89af-76a0609d4994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361577478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.361577478
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.4183349198
Short name	T112
Test name
Test status
Simulation time	60794200 ps
CPU time	13.5 seconds
Started	Aug 10 07:36:06 PM PDT 24
Finished	Aug 10 07:36:19 PM PDT 24
Peak memory	265736 kb
Host	smart-4534bcbd-f921-4ef8-a312-f9fc689a42cb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183349198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.4 183349198
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.718904423
Short name	T835
Test name
Test status
Simulation time	25067700 ps
CPU time	15.99 seconds
Started	Aug 10 07:36:08 PM PDT 24
Finished	Aug 10 07:36:24 PM PDT 24
Peak memory	283540 kb
Host	smart-661cdee0-2661-4fe2-a371-a0daf63b04ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718904423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.718904423
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.1834950311
Short name	T684
Test name
Test status
Simulation time	10343700 ps
CPU time	22.12 seconds
Started	Aug 10 07:36:05 PM PDT 24
Finished	Aug 10 07:36:27 PM PDT 24
Peak memory	274236 kb
Host	smart-aadbfd50-0036-47d7-8073-af6e37b39130
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834950311 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.1834950311
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.2715553579
Short name	T219
Test name
Test status
Simulation time	2886095000 ps
CPU time	2218.92 seconds
Started	Aug 10 07:35:53 PM PDT 24
Finished	Aug 10 08:12:52 PM PDT 24
Peak memory	265780 kb
Host	smart-0fd6460b-b170-4017-aed3-55622779a87f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2715553579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.2715553579
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.3603696256
Short name	T275
Test name
Test status
Simulation time	1410506100 ps
CPU time	957.25 seconds
Started	Aug 10 07:35:52 PM PDT 24
Finished	Aug 10 07:51:50 PM PDT 24
Peak memory	273812 kb
Host	smart-0d1a0e3b-478d-4b83-a4bd-94fbab98aeda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3603696256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3603696256
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.4177599771
Short name	T48
Test name
Test status
Simulation time	683803100 ps
CPU time	24.89 seconds
Started	Aug 10 07:35:53 PM PDT 24
Finished	Aug 10 07:36:18 PM PDT 24
Peak memory	263164 kb
Host	smart-5850ec2f-9b9e-4c6f-9467-217b9dc931be
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177599771 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.4177599771
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1116907293
Short name	T92
Test name
Test status
Simulation time	10011957400 ps
CPU time	319.31 seconds
Started	Aug 10 07:36:04 PM PDT 24
Finished	Aug 10 07:41:24 PM PDT 24
Peak memory	325772 kb
Host	smart-5afb469f-4c0c-4c72-8b77-6d4ec6ca88db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116907293 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1116907293
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3440152746
Short name	T312
Test name
Test status
Simulation time	25338700 ps
CPU time	13.65 seconds
Started	Aug 10 07:36:05 PM PDT 24
Finished	Aug 10 07:36:18 PM PDT 24
Peak memory	265204 kb
Host	smart-6c385b1b-491f-4608-8daf-4b8a73911263
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440152746 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3440152746
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3154143573
Short name	T472
Test name
Test status
Simulation time	80146013200 ps
CPU time	858.9 seconds
Started	Aug 10 07:35:47 PM PDT 24
Finished	Aug 10 07:50:06 PM PDT 24
Peak memory	261500 kb
Host	smart-210e5bc9-27af-4830-aa4d-8d479ee053b5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154143573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_hw_rma_reset.3154143573
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.473880166
Short name	T491
Test name
Test status
Simulation time	2044124100 ps
CPU time	68.57 seconds
Started	Aug 10 07:35:49 PM PDT 24
Finished	Aug 10 07:36:57 PM PDT 24
Peak memory	261468 kb
Host	smart-705f1be6-e853-448f-b99b-13f157dad494
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473880166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw _sec_otp.473880166
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.3213046556
Short name	T305
Test name
Test status
Simulation time	1337391900 ps
CPU time	164.52 seconds
Started	Aug 10 07:35:58 PM PDT 24
Finished	Aug 10 07:38:43 PM PDT 24
Peak memory	292240 kb
Host	smart-fe98972b-c2a8-47e3-8a30-d3584eb5a614
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213046556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_intr_rd.3213046556
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.228423246
Short name	T307
Test name
Test status
Simulation time	13043857200 ps
CPU time	260.84 seconds
Started	Aug 10 07:35:58 PM PDT 24
Finished	Aug 10 07:40:19 PM PDT 24
Peak memory	290520 kb
Host	smart-f3c99142-ba7d-442b-8f0f-13254613c702
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228423246 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.228423246
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.858305657
Short name	T2
Test name
Test status
Simulation time	4549202900 ps
CPU time	65.38 seconds
Started	Aug 10 07:36:03 PM PDT 24
Finished	Aug 10 07:37:09 PM PDT 24
Peak memory	261212 kb
Host	smart-d7148041-d24f-441c-b547-9e358f9cf2c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858305657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.flash_ctrl_intr_wr.858305657
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2995556554
Short name	T772
Test name
Test status
Simulation time	46396376000 ps
CPU time	196.38 seconds
Started	Aug 10 07:35:59 PM PDT 24
Finished	Aug 10 07:39:16 PM PDT 24
Peak memory	260956 kb
Host	smart-288c369f-26a2-4c9d-92a1-5df55ba9014a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299 5556554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2995556554
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.2979949340
Short name	T1064
Test name
Test status
Simulation time	3892821700 ps
CPU time	88.71 seconds
Started	Aug 10 07:35:54 PM PDT 24
Finished	Aug 10 07:37:22 PM PDT 24
Peak memory	264004 kb
Host	smart-3578c63a-78ee-4356-8eb9-2dbbcb0f30f0
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979949340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2979949340
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3346811802
Short name	T797
Test name
Test status
Simulation time	20346900 ps
CPU time	13.37 seconds
Started	Aug 10 07:36:08 PM PDT 24
Finished	Aug 10 07:36:21 PM PDT 24
Peak memory	260752 kb
Host	smart-319fa0fa-798f-4607-a4dd-7f0ff368f01e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346811802 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3346811802
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.186277030
Short name	T1025
Test name
Test status
Simulation time	14972160600 ps
CPU time	147.67 seconds
Started	Aug 10 07:35:53 PM PDT 24
Finished	Aug 10 07:38:21 PM PDT 24
Peak memory	265804 kb
Host	smart-d085c3ac-fbe1-4dd2-9936-43195580de86
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186277030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.186277030
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.1986772584
Short name	T864
Test name
Test status
Simulation time	160879400 ps
CPU time	110 seconds
Started	Aug 10 07:35:54 PM PDT 24
Finished	Aug 10 07:37:44 PM PDT 24
Peak memory	261580 kb
Host	smart-02af39bc-e73f-4139-9805-1f738c14f781
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986772584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.1986772584
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.1821630234
Short name	T398
Test name
Test status
Simulation time	88229900 ps
CPU time	242.52 seconds
Started	Aug 10 07:35:48 PM PDT 24
Finished	Aug 10 07:39:50 PM PDT 24
Peak memory	263748 kb
Host	smart-a55b5d09-7a69-463b-bf97-5c0f6c507918
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1821630234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1821630234
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.4008795551
Short name	T66
Test name
Test status
Simulation time	145364500 ps
CPU time	13.6 seconds
Started	Aug 10 07:35:59 PM PDT 24
Finished	Aug 10 07:36:13 PM PDT 24
Peak memory	265604 kb
Host	smart-363b41d5-5138-4e39-b4c6-4a1eae28fd3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008795551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.4008795551
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.319340822
Short name	T803
Test name
Test status
Simulation time	716411000 ps
CPU time	742.72 seconds
Started	Aug 10 07:35:48 PM PDT 24
Finished	Aug 10 07:48:11 PM PDT 24
Peak memory	284180 kb
Host	smart-bd26b987-8cf1-40dc-8425-f1ae401c2c12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319340822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.319340822
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.1461036356
Short name	T325
Test name
Test status
Simulation time	87951300 ps
CPU time	31.37 seconds
Started	Aug 10 07:36:04 PM PDT 24
Finished	Aug 10 07:36:36 PM PDT 24
Peak memory	274272 kb
Host	smart-ad7fb00c-927a-47c9-8408-86103c9ca76b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461036356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_re_evict.1461036356
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.4238040485
Short name	T597
Test name
Test status
Simulation time	537907700 ps
CPU time	135.59 seconds
Started	Aug 10 07:35:55 PM PDT 24
Finished	Aug 10 07:38:11 PM PDT 24
Peak memory	290656 kb
Host	smart-27febdba-e9ef-4cfc-b4a6-fb03d6d205bd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238040485 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_ro.4238040485
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.759402327
Short name	T1072
Test name
Test status
Simulation time	1437221000 ps
CPU time	178.07 seconds
Started	Aug 10 07:35:58 PM PDT 24
Finished	Aug 10 07:38:56 PM PDT 24
Peak memory	282652 kb
Host	smart-088f09cc-c7de-451e-8100-1e36035f428e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 759402327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.759402327
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.1040684068
Short name	T420
Test name
Test status
Simulation time	1148778600 ps
CPU time	145 seconds
Started	Aug 10 07:35:57 PM PDT 24
Finished	Aug 10 07:38:22 PM PDT 24
Peak memory	296168 kb
Host	smart-2fb319e2-e88c-4dbb-8946-e87171a9fbb0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040684068 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1040684068
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.3142848540
Short name	T672
Test name
Test status
Simulation time	47762871300 ps
CPU time	560.45 seconds
Started	Aug 10 07:35:53 PM PDT 24
Finished	Aug 10 07:45:13 PM PDT 24
Peak memory	315120 kb
Host	smart-23d442a2-580a-4c35-9658-9791925ec916
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142848540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.flash_ctrl_rw.3142848540
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_derr.238727860
Short name	T458
Test name
Test status
Simulation time	9228430200 ps
CPU time	227.42 seconds
Started	Aug 10 07:35:58 PM PDT 24
Finished	Aug 10 07:39:45 PM PDT 24
Peak memory	292568 kb
Host	smart-bbe84715-785e-4696-8f8b-573fd62a1112
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238727860 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_derr.238727860
Directory	/workspace/6.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.3146393114
Short name	T334
Test name
Test status
Simulation time	28348000 ps
CPU time	31.7 seconds
Started	Aug 10 07:35:59 PM PDT 24
Finished	Aug 10 07:36:30 PM PDT 24
Peak memory	274320 kb
Host	smart-0b80361a-5900-494c-bd51-f81f267facce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146393114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.3146393114
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.394455555
Short name	T877
Test name
Test status
Simulation time	76817400 ps
CPU time	29.09 seconds
Started	Aug 10 07:36:05 PM PDT 24
Finished	Aug 10 07:36:34 PM PDT 24
Peak memory	276352 kb
Host	smart-9f0207c7-2c70-482b-9897-6e74dcc46f3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394455555 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.394455555
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.1022251170
Short name	T1095
Test name
Test status
Simulation time	1489832500 ps
CPU time	208.88 seconds
Started	Aug 10 07:35:58 PM PDT 24
Finished	Aug 10 07:39:27 PM PDT 24
Peak memory	296200 kb
Host	smart-382b3741-a14c-45a1-b040-de5e6cd77ede
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022251170 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.flash_ctrl_rw_serr.1022251170
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.631255139
Short name	T442
Test name
Test status
Simulation time	3658836300 ps
CPU time	76.68 seconds
Started	Aug 10 07:36:07 PM PDT 24
Finished	Aug 10 07:37:24 PM PDT 24
Peak memory	265492 kb
Host	smart-5cf5e51c-b8ad-4e1f-a717-ddd47f5e0753
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631255139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.631255139
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.608336449
Short name	T562
Test name
Test status
Simulation time	267837200 ps
CPU time	196.78 seconds
Started	Aug 10 07:35:48 PM PDT 24
Finished	Aug 10 07:39:05 PM PDT 24
Peak memory	278880 kb
Host	smart-84223445-e21b-49c6-8dc0-7a7854e8aacd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608336449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.608336449
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.473880993
Short name	T429
Test name
Test status
Simulation time	5102640200 ps
CPU time	178.96 seconds
Started	Aug 10 07:35:53 PM PDT 24
Finished	Aug 10 07:38:52 PM PDT 24
Peak memory	260060 kb
Host	smart-ca8dee0d-9ab3-4d30-9436-c780ea46b2ec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473880993 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_wo.473880993
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.2952903241
Short name	T422
Test name
Test status
Simulation time	39932200 ps
CPU time	15.52 seconds
Started	Aug 10 07:42:34 PM PDT 24
Finished	Aug 10 07:42:50 PM PDT 24
Peak memory	283656 kb
Host	smart-1c641e2b-b9de-45f2-a99f-9252e07b9c23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952903241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2952903241
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.462773325
Short name	T677
Test name
Test status
Simulation time	43179700 ps
CPU time	111.21 seconds
Started	Aug 10 07:42:32 PM PDT 24
Finished	Aug 10 07:44:24 PM PDT 24
Peak memory	261700 kb
Host	smart-4493f1ac-ac8a-41f1-9e1f-1b1f80ec2f9c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462773325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_ot p_reset.462773325
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.3711048327
Short name	T407
Test name
Test status
Simulation time	26504200 ps
CPU time	15.65 seconds
Started	Aug 10 07:42:36 PM PDT 24
Finished	Aug 10 07:42:52 PM PDT 24
Peak memory	283656 kb
Host	smart-7371eece-8639-44cf-bc31-eb3e9ebb4ae7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711048327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3711048327
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.1398200218
Short name	T406
Test name
Test status
Simulation time	74419000 ps
CPU time	112.67 seconds
Started	Aug 10 07:42:32 PM PDT 24
Finished	Aug 10 07:44:25 PM PDT 24
Peak memory	260620 kb
Host	smart-fc715e9d-31e9-4c87-beb2-d6bc56eb01e0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398200218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o tp_reset.1398200218
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.1859873929
Short name	T438
Test name
Test status
Simulation time	33688600 ps
CPU time	13.47 seconds
Started	Aug 10 07:42:38 PM PDT 24
Finished	Aug 10 07:42:51 PM PDT 24
Peak memory	284884 kb
Host	smart-e2921445-030e-4781-bcad-52288da26bd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859873929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1859873929
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.548430757
Short name	T518
Test name
Test status
Simulation time	41320100 ps
CPU time	131.65 seconds
Started	Aug 10 07:42:38 PM PDT 24
Finished	Aug 10 07:44:49 PM PDT 24
Peak memory	262784 kb
Host	smart-98af5202-ab97-41e5-b034-339e14d61ba6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548430757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_ot p_reset.548430757
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.4281647346
Short name	T130
Test name
Test status
Simulation time	16087200 ps
CPU time	16 seconds
Started	Aug 10 07:42:37 PM PDT 24
Finished	Aug 10 07:42:53 PM PDT 24
Peak memory	275492 kb
Host	smart-31ba9d47-7cd2-4959-a731-41f31621ee57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281647346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.4281647346
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.3489150153
Short name	T794
Test name
Test status
Simulation time	76565100 ps
CPU time	130.46 seconds
Started	Aug 10 07:42:37 PM PDT 24
Finished	Aug 10 07:44:48 PM PDT 24
Peak memory	265756 kb
Host	smart-1ef122f6-17bd-429f-a414-7066825d78e8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489150153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o tp_reset.3489150153
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.3883028297
Short name	T765
Test name
Test status
Simulation time	59255400 ps
CPU time	15.97 seconds
Started	Aug 10 07:42:39 PM PDT 24
Finished	Aug 10 07:42:55 PM PDT 24
Peak memory	283628 kb
Host	smart-2e751a37-d9bd-4c2e-ad68-bee94075ff89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883028297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3883028297
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.2385304592
Short name	T692
Test name
Test status
Simulation time	71758400 ps
CPU time	133.09 seconds
Started	Aug 10 07:42:38 PM PDT 24
Finished	Aug 10 07:44:52 PM PDT 24
Peak memory	261568 kb
Host	smart-89fcecf5-c26d-4a8a-9d21-dddb2950fdc1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385304592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o tp_reset.2385304592
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.132112546
Short name	T394
Test name
Test status
Simulation time	51680800 ps
CPU time	15.57 seconds
Started	Aug 10 07:42:36 PM PDT 24
Finished	Aug 10 07:42:52 PM PDT 24
Peak memory	284792 kb
Host	smart-a0bd3609-5051-49d5-bc23-d178b55ef040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132112546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.132112546
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.2882687996
Short name	T645
Test name
Test status
Simulation time	140384300 ps
CPU time	130.96 seconds
Started	Aug 10 07:42:37 PM PDT 24
Finished	Aug 10 07:44:48 PM PDT 24
Peak memory	260744 kb
Host	smart-65edfb48-7d96-4681-bfe1-7ce36657e03a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882687996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o tp_reset.2882687996
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.813698435
Short name	T795
Test name
Test status
Simulation time	52433300 ps
CPU time	15.8 seconds
Started	Aug 10 07:42:39 PM PDT 24
Finished	Aug 10 07:42:55 PM PDT 24
Peak memory	283536 kb
Host	smart-46f78448-7649-4388-b6d2-6af490622f16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813698435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.813698435
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.1468379660
Short name	T652
Test name
Test status
Simulation time	151571400 ps
CPU time	110.26 seconds
Started	Aug 10 07:42:38 PM PDT 24
Finished	Aug 10 07:44:28 PM PDT 24
Peak memory	261692 kb
Host	smart-93766dfe-8835-4441-bf94-601139bc158b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468379660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o tp_reset.1468379660
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.195375143
Short name	T784
Test name
Test status
Simulation time	23653800 ps
CPU time	15.9 seconds
Started	Aug 10 07:42:46 PM PDT 24
Finished	Aug 10 07:43:02 PM PDT 24
Peak memory	284892 kb
Host	smart-33a3b7a5-6ecb-48f6-8794-49e600fe3c74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195375143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.195375143
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.552057424
Short name	T899
Test name
Test status
Simulation time	41311200 ps
CPU time	111.32 seconds
Started	Aug 10 07:42:37 PM PDT 24
Finished	Aug 10 07:44:29 PM PDT 24
Peak memory	264700 kb
Host	smart-63740ebf-645c-485e-9d62-fd0c9aee9fd2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552057424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_ot p_reset.552057424
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.3747667715
Short name	T414
Test name
Test status
Simulation time	21032900 ps
CPU time	15.59 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:43:00 PM PDT 24
Peak memory	284916 kb
Host	smart-5a4bea33-d8de-49bd-8eca-bfe5f3c8b244
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747667715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3747667715
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.3914015052
Short name	T690
Test name
Test status
Simulation time	42033800 ps
CPU time	110.86 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:44:35 PM PDT 24
Peak memory	261400 kb
Host	smart-3926df3f-9d27-4718-8ece-bb87bcdb2ea2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914015052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.3914015052
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.2026876749
Short name	T629
Test name
Test status
Simulation time	48915000 ps
CPU time	15.61 seconds
Started	Aug 10 07:42:43 PM PDT 24
Finished	Aug 10 07:42:59 PM PDT 24
Peak memory	285036 kb
Host	smart-e1fcae4c-3d1c-46a6-8b05-af52e849cdcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026876749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2026876749
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.2484348473
Short name	T620
Test name
Test status
Simulation time	48451400 ps
CPU time	111 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:44:36 PM PDT 24
Peak memory	260808 kb
Host	smart-f7b4bf65-4f8c-4869-871e-daf07be48801
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484348473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.2484348473
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.2840901079
Short name	T481
Test name
Test status
Simulation time	46407400 ps
CPU time	13.99 seconds
Started	Aug 10 07:36:28 PM PDT 24
Finished	Aug 10 07:36:42 PM PDT 24
Peak memory	258732 kb
Host	smart-38205dae-bb88-4592-b26a-85f0443e0e86
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840901079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2 840901079
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.3550836049
Short name	T755
Test name
Test status
Simulation time	48105600 ps
CPU time	13.35 seconds
Started	Aug 10 07:36:21 PM PDT 24
Finished	Aug 10 07:36:34 PM PDT 24
Peak memory	283616 kb
Host	smart-5ae3d06d-7185-45ac-b230-933c7c40cce1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550836049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.3550836049
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.1586510884
Short name	T916
Test name
Test status
Simulation time	11161700 ps
CPU time	21.73 seconds
Started	Aug 10 07:36:22 PM PDT 24
Finished	Aug 10 07:36:44 PM PDT 24
Peak memory	267112 kb
Host	smart-4cc11c44-b3e6-4428-8be3-aaf2d72b6e3e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586510884 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.1586510884
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.673329849
Short name	T478
Test name
Test status
Simulation time	3336531600 ps
CPU time	2194.57 seconds
Started	Aug 10 07:36:10 PM PDT 24
Finished	Aug 10 08:12:44 PM PDT 24
Peak memory	263528 kb
Host	smart-53ac6d25-90f2-4e87-84bf-45160558d0a7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=673329849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.673329849
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.12441775
Short name	T780
Test name
Test status
Simulation time	535792700 ps
CPU time	705.2 seconds
Started	Aug 10 07:36:13 PM PDT 24
Finished	Aug 10 07:47:59 PM PDT 24
Peak memory	272936 kb
Host	smart-32b8c08a-e50a-44e2-82e5-f8e224a5facf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12441775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.12441775
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.3744116996
Short name	T584
Test name
Test status
Simulation time	349189700 ps
CPU time	23.08 seconds
Started	Aug 10 07:36:09 PM PDT 24
Finished	Aug 10 07:36:33 PM PDT 24
Peak memory	263020 kb
Host	smart-45d2bb2c-e4d8-4891-8a1f-44803d30691e
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744116996 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.3744116996
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.752204985
Short name	T1096
Test name
Test status
Simulation time	10019609000 ps
CPU time	80.08 seconds
Started	Aug 10 07:36:28 PM PDT 24
Finished	Aug 10 07:37:48 PM PDT 24
Peak memory	300612 kb
Host	smart-303ee180-20ca-4ec9-babb-447b0a037539
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752204985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.752204985
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3723374515
Short name	T953
Test name
Test status
Simulation time	25077900 ps
CPU time	13.41 seconds
Started	Aug 10 07:36:26 PM PDT 24
Finished	Aug 10 07:36:40 PM PDT 24
Peak memory	258928 kb
Host	smart-bca60f8d-c31a-42c0-b034-6db5e56568ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723374515 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3723374515
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.3958433940
Short name	T63
Test name
Test status
Simulation time	80143885100 ps
CPU time	935.42 seconds
Started	Aug 10 07:36:10 PM PDT 24
Finished	Aug 10 07:51:45 PM PDT 24
Peak memory	264736 kb
Host	smart-0d3dd1ab-d191-45ff-a6bb-efefecc31fbb
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958433940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.flash_ctrl_hw_rma_reset.3958433940
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.2391522937
Short name	T793
Test name
Test status
Simulation time	1106248200 ps
CPU time	54.83 seconds
Started	Aug 10 07:36:13 PM PDT 24
Finished	Aug 10 07:37:08 PM PDT 24
Peak memory	263220 kb
Host	smart-bae7bd65-733b-4e1c-8199-1d8b09edf29d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391522937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.2391522937
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.830991562
Short name	T1023
Test name
Test status
Simulation time	2225458200 ps
CPU time	135.56 seconds
Started	Aug 10 07:36:18 PM PDT 24
Finished	Aug 10 07:38:33 PM PDT 24
Peak memory	286392 kb
Host	smart-378676e5-8589-4a0f-93ce-30140fe0182a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830991562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash _ctrl_intr_rd.830991562
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.1125465426
Short name	T650
Test name
Test status
Simulation time	2907707900 ps
CPU time	74.63 seconds
Started	Aug 10 07:36:17 PM PDT 24
Finished	Aug 10 07:37:32 PM PDT 24
Peak memory	261196 kb
Host	smart-708e4893-7709-4cd5-9af3-a49d1d7473b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125465426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.1125465426
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3430048874
Short name	T883
Test name
Test status
Simulation time	22800726500 ps
CPU time	187.76 seconds
Started	Aug 10 07:36:17 PM PDT 24
Finished	Aug 10 07:39:25 PM PDT 24
Peak memory	260872 kb
Host	smart-0bef0fae-f93e-4421-b175-31cf3e7dadd5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343 0048874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3430048874
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.1686644580
Short name	T575
Test name
Test status
Simulation time	1696685700 ps
CPU time	69.04 seconds
Started	Aug 10 07:36:08 PM PDT 24
Finished	Aug 10 07:37:17 PM PDT 24
Peak memory	263696 kb
Host	smart-d48e5aca-6e46-43a7-ad88-1aacc4516215
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686644580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1686644580
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3746087662
Short name	T47
Test name
Test status
Simulation time	26332700 ps
CPU time	13.56 seconds
Started	Aug 10 07:36:22 PM PDT 24
Finished	Aug 10 07:36:36 PM PDT 24
Peak memory	260632 kb
Host	smart-245ba38d-9eb7-4c5b-8d0d-bc44847f8d6b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746087662 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3746087662
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.3656641971
Short name	T722
Test name
Test status
Simulation time	6982515900 ps
CPU time	162.85 seconds
Started	Aug 10 07:36:14 PM PDT 24
Finished	Aug 10 07:38:57 PM PDT 24
Peak memory	265788 kb
Host	smart-0ba3eb42-a47d-451a-af53-daf89809f389
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656641971 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.3656641971
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.2551035710
Short name	T978
Test name
Test status
Simulation time	134760700 ps
CPU time	111.71 seconds
Started	Aug 10 07:36:15 PM PDT 24
Finished	Aug 10 07:38:06 PM PDT 24
Peak memory	265208 kb
Host	smart-820a1476-3740-4182-8879-9e43f56da3fa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551035710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.2551035710
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.2752373545
Short name	T332
Test name
Test status
Simulation time	237096500 ps
CPU time	271.69 seconds
Started	Aug 10 07:36:09 PM PDT 24
Finished	Aug 10 07:40:41 PM PDT 24
Peak memory	263752 kb
Host	smart-091de9f5-ba3c-4344-80bf-41ec1567ac3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2752373545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2752373545
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.1409815551
Short name	T439
Test name
Test status
Simulation time	96282200 ps
CPU time	16.05 seconds
Started	Aug 10 07:36:21 PM PDT 24
Finished	Aug 10 07:36:37 PM PDT 24
Peak memory	260272 kb
Host	smart-20791dda-c8ae-4a04-89d3-9646d09afdba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409815551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_prog_reset.1409815551
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.1261818025
Short name	T734
Test name
Test status
Simulation time	102516800 ps
CPU time	788.56 seconds
Started	Aug 10 07:36:09 PM PDT 24
Finished	Aug 10 07:49:18 PM PDT 24
Peak memory	286500 kb
Host	smart-0e6a3405-f042-4cc8-8000-c0fd92eafb74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1261818025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1261818025
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.2352433598
Short name	T330
Test name
Test status
Simulation time	86091800 ps
CPU time	35.61 seconds
Started	Aug 10 07:36:21 PM PDT 24
Finished	Aug 10 07:36:57 PM PDT 24
Peak memory	274276 kb
Host	smart-49fd7953-938d-4f80-9489-35fb62974c65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352433598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_re_evict.2352433598
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.3667048217
Short name	T979
Test name
Test status
Simulation time	501122500 ps
CPU time	122.32 seconds
Started	Aug 10 07:36:10 PM PDT 24
Finished	Aug 10 07:38:13 PM PDT 24
Peak memory	290656 kb
Host	smart-25deaf6c-c0c7-4763-813e-b9bcc64dedc4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667048217 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.3667048217
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.1296049855
Short name	T166
Test name
Test status
Simulation time	1255999800 ps
CPU time	131.88 seconds
Started	Aug 10 07:36:15 PM PDT 24
Finished	Aug 10 07:38:27 PM PDT 24
Peak memory	282556 kb
Host	smart-dbb3cfcd-3dac-43bd-934f-55d36d41a2b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1296049855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1296049855
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.1701292041
Short name	T1005
Test name
Test status
Simulation time	552452300 ps
CPU time	156.63 seconds
Started	Aug 10 07:36:10 PM PDT 24
Finished	Aug 10 07:38:47 PM PDT 24
Peak memory	282576 kb
Host	smart-c75a1ae9-42f7-4c9e-8b0b-604ca35e35af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701292041 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.1701292041
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.592009558
Short name	T1070
Test name
Test status
Simulation time	4148066100 ps
CPU time	250.67 seconds
Started	Aug 10 07:36:15 PM PDT 24
Finished	Aug 10 07:40:26 PM PDT 24
Peak memory	293708 kb
Host	smart-2f865fca-384c-417a-85c3-6ff8f415df54
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592009558 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_derr.592009558
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.165173906
Short name	T514
Test name
Test status
Simulation time	29444000 ps
CPU time	31.68 seconds
Started	Aug 10 07:36:21 PM PDT 24
Finished	Aug 10 07:36:53 PM PDT 24
Peak memory	276364 kb
Host	smart-1e37f00d-0a6e-4746-aae8-1eb1e328080f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165173906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_rw_evict.165173906
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.856542509
Short name	T822
Test name
Test status
Simulation time	29943800 ps
CPU time	31.42 seconds
Started	Aug 10 07:36:23 PM PDT 24
Finished	Aug 10 07:36:55 PM PDT 24
Peak memory	276388 kb
Host	smart-c89a3980-8d1c-4cca-950f-e74ff3cc12e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856542509 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.856542509
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.2466706729
Short name	T473
Test name
Test status
Simulation time	7638086900 ps
CPU time	180.53 seconds
Started	Aug 10 07:36:13 PM PDT 24
Finished	Aug 10 07:39:13 PM PDT 24
Peak memory	290700 kb
Host	smart-c2ceb2c0-c888-4d0c-a748-f70abe0615fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466706729 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.flash_ctrl_rw_serr.2466706729
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.2660036242
Short name	T986
Test name
Test status
Simulation time	654717100 ps
CPU time	68.75 seconds
Started	Aug 10 07:36:23 PM PDT 24
Finished	Aug 10 07:37:32 PM PDT 24
Peak memory	265000 kb
Host	smart-ebff24b9-7c13-4fd1-81b0-ab9e34da35eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660036242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2660036242
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.2323553935
Short name	T42
Test name
Test status
Simulation time	57948300 ps
CPU time	172.91 seconds
Started	Aug 10 07:36:08 PM PDT 24
Finished	Aug 10 07:39:01 PM PDT 24
Peak memory	281232 kb
Host	smart-664af3ff-6c05-4764-bfd9-5b3c133706f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323553935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2323553935
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.3096495181
Short name	T720
Test name
Test status
Simulation time	4101042800 ps
CPU time	174.75 seconds
Started	Aug 10 07:36:09 PM PDT 24
Finished	Aug 10 07:39:04 PM PDT 24
Peak memory	265848 kb
Host	smart-bac3ccbf-c92a-4e88-ae8d-d7467e23d790
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096495181 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.3096495181
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.1957435498
Short name	T987
Test name
Test status
Simulation time	15678400 ps
CPU time	16.03 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:43:00 PM PDT 24
Peak memory	284880 kb
Host	smart-41429850-2a24-4a5c-8ce4-3810502b31ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957435498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1957435498
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.3955546252
Short name	T415
Test name
Test status
Simulation time	329044000 ps
CPU time	131.45 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:44:55 PM PDT 24
Peak memory	261480 kb
Host	smart-04b0a84d-aa8a-4d67-be46-18906e7ccc58
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955546252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o tp_reset.3955546252
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.951016549
Short name	T271
Test name
Test status
Simulation time	42822200 ps
CPU time	16.17 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:43:00 PM PDT 24
Peak memory	275560 kb
Host	smart-f6d06c20-7ccb-43c0-b8b2-2ccef01655f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951016549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.951016549
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.793508116
Short name	T894
Test name
Test status
Simulation time	68088000 ps
CPU time	131.88 seconds
Started	Aug 10 07:42:43 PM PDT 24
Finished	Aug 10 07:44:55 PM PDT 24
Peak memory	260560 kb
Host	smart-fbc5b841-fe25-46f4-a16a-d320e3129674
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793508116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot p_reset.793508116
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.2554188276
Short name	T550
Test name
Test status
Simulation time	16000100 ps
CPU time	16.14 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:43:00 PM PDT 24
Peak memory	275456 kb
Host	smart-ad001f39-33c4-48f0-a0e3-fda93b636727
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554188276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2554188276
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.48221157
Short name	T646
Test name
Test status
Simulation time	41842600 ps
CPU time	111.3 seconds
Started	Aug 10 07:42:43 PM PDT 24
Finished	Aug 10 07:44:35 PM PDT 24
Peak memory	261400 kb
Host	smart-3feb297b-bf2f-44e7-93f7-a1834dab339b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48221157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp _reset.48221157
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.1172648721
Short name	T723
Test name
Test status
Simulation time	22674900 ps
CPU time	15.87 seconds
Started	Aug 10 07:42:49 PM PDT 24
Finished	Aug 10 07:43:05 PM PDT 24
Peak memory	283604 kb
Host	smart-49d6e0e0-d8b9-4da7-9a35-dd44a87b1d2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172648721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1172648721
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.2155606980
Short name	T367
Test name
Test status
Simulation time	44227200 ps
CPU time	110.62 seconds
Started	Aug 10 07:42:44 PM PDT 24
Finished	Aug 10 07:44:34 PM PDT 24
Peak memory	261524 kb
Host	smart-e3244e15-a333-42e2-808f-1b857eea363c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155606980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.2155606980
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.2317374547
Short name	T437
Test name
Test status
Simulation time	25351300 ps
CPU time	16.41 seconds
Started	Aug 10 07:42:49 PM PDT 24
Finished	Aug 10 07:43:05 PM PDT 24
Peak memory	284860 kb
Host	smart-ad18e693-8daa-4eb5-8f69-e88a918d18eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317374547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2317374547
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.2522189350
Short name	T182
Test name
Test status
Simulation time	202927600 ps
CPU time	110.32 seconds
Started	Aug 10 07:42:50 PM PDT 24
Finished	Aug 10 07:44:41 PM PDT 24
Peak memory	264948 kb
Host	smart-77932a89-82a6-4119-8908-8ee7ea190c71
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522189350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o tp_reset.2522189350
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.1099025873
Short name	T990
Test name
Test status
Simulation time	49405400 ps
CPU time	15.81 seconds
Started	Aug 10 07:42:48 PM PDT 24
Finished	Aug 10 07:43:04 PM PDT 24
Peak memory	283536 kb
Host	smart-42288924-4f12-4e15-ba61-b42bc417728b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099025873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1099025873
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.3509563180
Short name	T914
Test name
Test status
Simulation time	74818400 ps
CPU time	132.36 seconds
Started	Aug 10 07:42:49 PM PDT 24
Finished	Aug 10 07:45:01 PM PDT 24
Peak memory	264360 kb
Host	smart-29fc08c9-7569-49f4-90c1-9bc6db262efa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509563180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o tp_reset.3509563180
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.2709030067
Short name	T574
Test name
Test status
Simulation time	53744500 ps
CPU time	16.15 seconds
Started	Aug 10 07:42:50 PM PDT 24
Finished	Aug 10 07:43:06 PM PDT 24
Peak memory	275568 kb
Host	smart-b84aa521-2eda-4452-aa00-c1bb75bff267
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709030067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.2709030067
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.2765778767
Short name	T807
Test name
Test status
Simulation time	72696100 ps
CPU time	133.29 seconds
Started	Aug 10 07:42:50 PM PDT 24
Finished	Aug 10 07:45:03 PM PDT 24
Peak memory	265688 kb
Host	smart-5ea0da35-ba38-4c12-b327-bcb8de17be13
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765778767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o tp_reset.2765778767
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.2416738757
Short name	T732
Test name
Test status
Simulation time	52630000 ps
CPU time	15.88 seconds
Started	Aug 10 07:42:51 PM PDT 24
Finished	Aug 10 07:43:07 PM PDT 24
Peak memory	283480 kb
Host	smart-92ecaec5-e9c6-4404-aeeb-c2e1997c9e7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416738757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2416738757
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.1481184957
Short name	T998
Test name
Test status
Simulation time	133970700 ps
CPU time	133.59 seconds
Started	Aug 10 07:42:51 PM PDT 24
Finished	Aug 10 07:45:04 PM PDT 24
Peak memory	265620 kb
Host	smart-6a634c0c-c509-4b48-9bf2-e54a0145395b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481184957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.1481184957
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.3752387595
Short name	T493
Test name
Test status
Simulation time	54581600 ps
CPU time	15.69 seconds
Started	Aug 10 07:42:49 PM PDT 24
Finished	Aug 10 07:43:04 PM PDT 24
Peak memory	283564 kb
Host	smart-f7c16cdb-1046-4001-8f7c-1637678dd0b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752387595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3752387595
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.3930890909
Short name	T1059
Test name
Test status
Simulation time	73800800 ps
CPU time	134.78 seconds
Started	Aug 10 07:42:49 PM PDT 24
Finished	Aug 10 07:45:04 PM PDT 24
Peak memory	264592 kb
Host	smart-94c3775c-4ce0-4fe6-9843-f8463d4a85c4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930890909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o tp_reset.3930890909
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.2088169937
Short name	T842
Test name
Test status
Simulation time	14660600 ps
CPU time	15.89 seconds
Started	Aug 10 07:42:52 PM PDT 24
Finished	Aug 10 07:43:08 PM PDT 24
Peak memory	284808 kb
Host	smart-084d0b56-9fc4-4abe-9751-b99099444282
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088169937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2088169937
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.1301033065
Short name	T633
Test name
Test status
Simulation time	41963800 ps
CPU time	130.2 seconds
Started	Aug 10 07:42:47 PM PDT 24
Finished	Aug 10 07:44:57 PM PDT 24
Peak memory	260892 kb
Host	smart-4ad68385-11b3-4b31-ac08-fcd820253059
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301033065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.1301033065
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.3472328624
Short name	T444
Test name
Test status
Simulation time	54805100 ps
CPU time	13.41 seconds
Started	Aug 10 07:36:49 PM PDT 24
Finished	Aug 10 07:37:02 PM PDT 24
Peak memory	258812 kb
Host	smart-37060ec5-4734-4fcd-8115-0b39419ca4dd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472328624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3 472328624
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.2535686612
Short name	T668
Test name
Test status
Simulation time	27009700 ps
CPU time	13.43 seconds
Started	Aug 10 07:36:51 PM PDT 24
Finished	Aug 10 07:37:05 PM PDT 24
Peak memory	284872 kb
Host	smart-e84877b0-0a2c-4c76-ac58-e8d4bbe7e2f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535686612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2535686612
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.2661407518
Short name	T922
Test name
Test status
Simulation time	27127400 ps
CPU time	22.51 seconds
Started	Aug 10 07:36:50 PM PDT 24
Finished	Aug 10 07:37:13 PM PDT 24
Peak memory	267124 kb
Host	smart-50f5280c-24ce-4124-93df-cce6aaf7fa73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661407518 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.2661407518
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.2014676622
Short name	T25
Test name
Test status
Simulation time	6074928100 ps
CPU time	2386.3 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 08:16:20 PM PDT 24
Peak memory	265448 kb
Host	smart-3749595a-913a-4d8e-97fa-1e7525afb62a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2014676622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2014676622
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.3368818735
Short name	T273
Test name
Test status
Simulation time	755922700 ps
CPU time	874.68 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 07:51:08 PM PDT 24
Peak memory	271072 kb
Host	smart-10637906-fab3-4d49-9ee5-c926d9d5c815
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368818735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3368818735
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.447266043
Short name	T67
Test name
Test status
Simulation time	1951670600 ps
CPU time	30.1 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 07:37:03 PM PDT 24
Peak memory	263252 kb
Host	smart-abf22e20-628e-4708-8310-a9555de53e79
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447266043 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.447266043
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1787950897
Short name	T676
Test name
Test status
Simulation time	10071967700 ps
CPU time	48.67 seconds
Started	Aug 10 07:36:51 PM PDT 24
Finished	Aug 10 07:37:40 PM PDT 24
Peak memory	270644 kb
Host	smart-8d2b4352-5e5f-4294-b259-a5f55eb2a176
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787950897 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1787950897
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.588868690
Short name	T86
Test name
Test status
Simulation time	52028500 ps
CPU time	13.65 seconds
Started	Aug 10 07:36:49 PM PDT 24
Finished	Aug 10 07:37:03 PM PDT 24
Peak memory	258844 kb
Host	smart-4c2b2467-74d0-4312-b910-8217f0889eee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588868690 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.588868690
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2206688309
Short name	T187
Test name
Test status
Simulation time	160168910000 ps
CPU time	927.38 seconds
Started	Aug 10 07:36:32 PM PDT 24
Finished	Aug 10 07:52:00 PM PDT 24
Peak memory	265376 kb
Host	smart-870b1bf6-7769-48a0-852f-db33b68ea97e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206688309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.2206688309
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.337406715
Short name	T293
Test name
Test status
Simulation time	32986592800 ps
CPU time	148.34 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 07:39:01 PM PDT 24
Peak memory	263056 kb
Host	smart-daa59c39-3a7c-49aa-9538-e097508cd3f6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337406715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw _sec_otp.337406715
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.3107514668
Short name	T1075
Test name
Test status
Simulation time	13306684100 ps
CPU time	222.7 seconds
Started	Aug 10 07:36:39 PM PDT 24
Finished	Aug 10 07:40:22 PM PDT 24
Peak memory	285836 kb
Host	smart-678022be-b1b0-4337-aacb-f5872a0c6aa0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107514668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_intr_rd.3107514668
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3971279112
Short name	T1043
Test name
Test status
Simulation time	6110845400 ps
CPU time	153.18 seconds
Started	Aug 10 07:36:40 PM PDT 24
Finished	Aug 10 07:39:14 PM PDT 24
Peak memory	293536 kb
Host	smart-7d453ece-3cef-4f9b-8bd5-7cf90fdb8600
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971279112 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3971279112
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3940231499
Short name	T531
Test name
Test status
Simulation time	59643554500 ps
CPU time	143.84 seconds
Started	Aug 10 07:36:44 PM PDT 24
Finished	Aug 10 07:39:08 PM PDT 24
Peak memory	261128 kb
Host	smart-a40cab92-9ce8-491d-bfdf-fc18b77ee72f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394 0231499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3940231499
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.3523934794
Short name	T788
Test name
Test status
Simulation time	1752106900 ps
CPU time	73.35 seconds
Started	Aug 10 07:36:40 PM PDT 24
Finished	Aug 10 07:37:53 PM PDT 24
Peak memory	264220 kb
Host	smart-431080a1-cf9e-4a8f-baf6-04799ae5a342
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523934794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3523934794
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.1323851820
Short name	T713
Test name
Test status
Simulation time	72549400 ps
CPU time	130.31 seconds
Started	Aug 10 07:36:32 PM PDT 24
Finished	Aug 10 07:38:43 PM PDT 24
Peak memory	260788 kb
Host	smart-73c4e120-2046-43b5-acaf-875e25f76b84
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323851820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.1323851820
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.2686868991
Short name	T545
Test name
Test status
Simulation time	59477000 ps
CPU time	111.94 seconds
Started	Aug 10 07:36:31 PM PDT 24
Finished	Aug 10 07:38:23 PM PDT 24
Peak memory	263684 kb
Host	smart-de3670a3-41de-49b3-8e20-b0e7b2a0eb52
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2686868991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2686868991
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.244536651
Short name	T800
Test name
Test status
Simulation time	5733992300 ps
CPU time	244.97 seconds
Started	Aug 10 07:36:44 PM PDT 24
Finished	Aug 10 07:40:49 PM PDT 24
Peak memory	260892 kb
Host	smart-8903236c-be92-40a8-9c7e-250d7cb76d85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244536651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.flash_ctrl_prog_reset.244536651
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.2629077085
Short name	T154
Test name
Test status
Simulation time	873277300 ps
CPU time	1019.21 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 07:53:32 PM PDT 24
Peak memory	285996 kb
Host	smart-f0a0e819-f5e0-40ee-92cf-e8f2d166769c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629077085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2629077085
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.2231730752
Short name	T536
Test name
Test status
Simulation time	232635600 ps
CPU time	35.36 seconds
Started	Aug 10 07:36:45 PM PDT 24
Finished	Aug 10 07:37:21 PM PDT 24
Peak memory	274364 kb
Host	smart-7eec96cf-5c80-4192-9482-09dfc75fc201
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231730752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.2231730752
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.1939505266
Short name	T206
Test name
Test status
Simulation time	992589100 ps
CPU time	112.82 seconds
Started	Aug 10 07:36:40 PM PDT 24
Finished	Aug 10 07:38:33 PM PDT 24
Peak memory	291992 kb
Host	smart-25a0081d-ab95-4912-9b49-4f54050ddfc2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939505266 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.1939505266
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.2908077295
Short name	T733
Test name
Test status
Simulation time	2743084400 ps
CPU time	130.01 seconds
Started	Aug 10 07:36:39 PM PDT 24
Finished	Aug 10 07:38:49 PM PDT 24
Peak memory	282592 kb
Host	smart-638299fd-601d-4f88-9a58-760c4a5e6e78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2908077295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2908077295
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.3252265957
Short name	T982
Test name
Test status
Simulation time	1831406400 ps
CPU time	119.47 seconds
Started	Aug 10 07:36:39 PM PDT 24
Finished	Aug 10 07:38:39 PM PDT 24
Peak memory	282548 kb
Host	smart-ba525cd5-8c22-41ff-971f-2c2afeb1ea36
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252265957 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.3252265957
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.1059119947
Short name	T1053
Test name
Test status
Simulation time	6841281200 ps
CPU time	566.98 seconds
Started	Aug 10 07:36:42 PM PDT 24
Finished	Aug 10 07:46:09 PM PDT 24
Peak memory	315364 kb
Host	smart-b4baceb5-42b9-4a4a-a606-f8f4a474c76b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059119947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.flash_ctrl_rw.1059119947
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.2661204781
Short name	T52
Test name
Test status
Simulation time	6515739900 ps
CPU time	201.55 seconds
Started	Aug 10 07:36:44 PM PDT 24
Finished	Aug 10 07:40:06 PM PDT 24
Peak memory	290344 kb
Host	smart-867383b0-8f76-45aa-95a7-de4cf4556b4a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661204781 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_derr.2661204781
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.110421986
Short name	T889
Test name
Test status
Simulation time	176387100 ps
CPU time	30.51 seconds
Started	Aug 10 07:36:44 PM PDT 24
Finished	Aug 10 07:37:15 PM PDT 24
Peak memory	274332 kb
Host	smart-bf982571-4bc0-4668-89f4-602c475490a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110421986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_rw_evict.110421986
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3704808528
Short name	T153
Test name
Test status
Simulation time	162529400 ps
CPU time	28.91 seconds
Started	Aug 10 07:36:43 PM PDT 24
Finished	Aug 10 07:37:12 PM PDT 24
Peak memory	274300 kb
Host	smart-ada82897-de37-4a3a-b821-b3f3d9e86336
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704808528 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3704808528
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.596460995
Short name	T611
Test name
Test status
Simulation time	1999840600 ps
CPU time	177.35 seconds
Started	Aug 10 07:36:39 PM PDT 24
Finished	Aug 10 07:39:36 PM PDT 24
Peak memory	295980 kb
Host	smart-90e10001-4036-4765-8418-1a72f5d496c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596460995 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_rw_serr.596460995
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.74681274
Short name	T383
Test name
Test status
Simulation time	539771200 ps
CPU time	64.07 seconds
Started	Aug 10 07:36:48 PM PDT 24
Finished	Aug 10 07:37:52 PM PDT 24
Peak memory	264504 kb
Host	smart-0add9185-472f-4543-b009-e08aef3d9722
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=74681274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.74681274
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.917595110
Short name	T999
Test name
Test status
Simulation time	29468400 ps
CPU time	73.92 seconds
Started	Aug 10 07:36:33 PM PDT 24
Finished	Aug 10 07:37:47 PM PDT 24
Peak memory	275556 kb
Host	smart-1b120316-8844-4af5-bd34-cf6b5a856713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917595110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.917595110
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.2567675885
Short name	T261
Test name
Test status
Simulation time	1924258400 ps
CPU time	167.85 seconds
Started	Aug 10 07:36:44 PM PDT 24
Finished	Aug 10 07:39:32 PM PDT 24
Peak memory	265928 kb
Host	smart-88ede046-053e-4711-9f54-6f0c2e7b9293
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567675885 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_wo.2567675885
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.1928541993
Short name	T901
Test name
Test status
Simulation time	19961400 ps
CPU time	13.48 seconds
Started	Aug 10 07:37:08 PM PDT 24
Finished	Aug 10 07:37:21 PM PDT 24
Peak memory	258896 kb
Host	smart-8d1d5414-439a-4c4e-95f8-6c0840870d90
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928541993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1 928541993
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.2320529657
Short name	T991
Test name
Test status
Simulation time	27217600 ps
CPU time	13.34 seconds
Started	Aug 10 07:37:10 PM PDT 24
Finished	Aug 10 07:37:23 PM PDT 24
Peak memory	285020 kb
Host	smart-9d0d10ce-416d-4877-86a1-2935fa536999
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320529657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2320529657
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.1606951053
Short name	T950
Test name
Test status
Simulation time	90621900 ps
CPU time	22.25 seconds
Started	Aug 10 07:37:09 PM PDT 24
Finished	Aug 10 07:37:31 PM PDT 24
Peak memory	274276 kb
Host	smart-1fa9a382-85b4-4979-a5ee-2ffdd167253d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606951053 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.1606951053
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.2030699173
Short name	T1029
Test name
Test status
Simulation time	12208817300 ps
CPU time	2196.28 seconds
Started	Aug 10 07:36:56 PM PDT 24
Finished	Aug 10 08:13:32 PM PDT 24
Peak memory	263372 kb
Host	smart-1f6d2574-c9e5-41b0-bd7a-a7db61d651a6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2030699173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.2030699173
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.1985685748
Short name	T869
Test name
Test status
Simulation time	1254218900 ps
CPU time	902.89 seconds
Started	Aug 10 07:36:53 PM PDT 24
Finished	Aug 10 07:51:56 PM PDT 24
Peak memory	273400 kb
Host	smart-8452b415-5b19-4a30-8947-d141a9842791
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985685748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1985685748
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2124324198
Short name	T510
Test name
Test status
Simulation time	10053676700 ps
CPU time	42.88 seconds
Started	Aug 10 07:37:08 PM PDT 24
Finished	Aug 10 07:37:51 PM PDT 24
Peak memory	271780 kb
Host	smart-fe02cc09-2c94-42c2-9c07-226c26ab1f32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124324198 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2124324198
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.59977985
Short name	T885
Test name
Test status
Simulation time	46831900 ps
CPU time	13.67 seconds
Started	Aug 10 07:37:08 PM PDT 24
Finished	Aug 10 07:37:22 PM PDT 24
Peak memory	259044 kb
Host	smart-cc4c764c-a262-46c3-9b2d-a8ebb5fa442b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59977985 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.59977985
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3106449808
Short name	T737
Test name
Test status
Simulation time	180200210400 ps
CPU time	915.71 seconds
Started	Aug 10 07:36:54 PM PDT 24
Finished	Aug 10 07:52:10 PM PDT 24
Peak memory	264700 kb
Host	smart-e4eb3269-9496-44dd-b102-29fb2d311d9a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106449808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.3106449808
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.372713896
Short name	T605
Test name
Test status
Simulation time	41957397800 ps
CPU time	162.01 seconds
Started	Aug 10 07:36:56 PM PDT 24
Finished	Aug 10 07:39:38 PM PDT 24
Peak memory	263340 kb
Host	smart-b909da46-8e33-4dc5-8dbc-6c2eed63c327
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372713896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw _sec_otp.372713896
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.2450231413
Short name	T789
Test name
Test status
Simulation time	17672172700 ps
CPU time	217.45 seconds
Started	Aug 10 07:37:04 PM PDT 24
Finished	Aug 10 07:40:42 PM PDT 24
Peak memory	285588 kb
Host	smart-adaca5d4-9931-418a-92bc-f41f09a3f3bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450231413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_intr_rd.2450231413
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.192820224
Short name	T1105
Test name
Test status
Simulation time	5974068100 ps
CPU time	150.35 seconds
Started	Aug 10 07:37:03 PM PDT 24
Finished	Aug 10 07:39:34 PM PDT 24
Peak memory	291784 kb
Host	smart-d2a9fb60-970b-45ff-b260-2711175c555e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192820224 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.192820224
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.383797830
Short name	T569
Test name
Test status
Simulation time	9054568200 ps
CPU time	79.25 seconds
Started	Aug 10 07:37:02 PM PDT 24
Finished	Aug 10 07:38:22 PM PDT 24
Peak memory	260568 kb
Host	smart-ba472a27-8561-42c2-a586-5cfd3a9a343f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383797830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 9.flash_ctrl_intr_wr.383797830
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2417715404
Short name	T571
Test name
Test status
Simulation time	20337384700 ps
CPU time	182.98 seconds
Started	Aug 10 07:37:03 PM PDT 24
Finished	Aug 10 07:40:06 PM PDT 24
Peak memory	260840 kb
Host	smart-852d257a-b613-4ebf-860f-7d36e7eca363
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241 7715404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2417715404
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.4042807455
Short name	T89
Test name
Test status
Simulation time	3327482900 ps
CPU time	63.52 seconds
Started	Aug 10 07:36:55 PM PDT 24
Finished	Aug 10 07:37:59 PM PDT 24
Peak memory	261156 kb
Host	smart-c2c8f4fa-b2d1-4d80-90fc-3245f8b7f26a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042807455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.4042807455
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.4284687668
Short name	T451
Test name
Test status
Simulation time	15771000 ps
CPU time	13.71 seconds
Started	Aug 10 07:37:07 PM PDT 24
Finished	Aug 10 07:37:21 PM PDT 24
Peak memory	265352 kb
Host	smart-9dbd675e-b109-4c71-bf79-c8949098b4b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284687668 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.4284687668
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.3042323799
Short name	T1032
Test name
Test status
Simulation time	9237289400 ps
CPU time	162.55 seconds
Started	Aug 10 07:36:55 PM PDT 24
Finished	Aug 10 07:39:38 PM PDT 24
Peak memory	265820 kb
Host	smart-a2d36028-2524-425c-aa52-b497a15d3630
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042323799 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.3042323799
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.2118576868
Short name	T97
Test name
Test status
Simulation time	71209300 ps
CPU time	130.69 seconds
Started	Aug 10 07:36:55 PM PDT 24
Finished	Aug 10 07:39:06 PM PDT 24
Peak memory	260636 kb
Host	smart-399d0317-1a3c-457b-89a9-26315c4aa095
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118576868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot p_reset.2118576868
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.1364679467
Short name	T1069
Test name
Test status
Simulation time	49483500 ps
CPU time	66.74 seconds
Started	Aug 10 07:36:54 PM PDT 24
Finished	Aug 10 07:38:01 PM PDT 24
Peak memory	263620 kb
Host	smart-c66bd27c-9c97-4a2d-bbc7-5f809e43a64f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1364679467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1364679467
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.1295095695
Short name	T392
Test name
Test status
Simulation time	59976700 ps
CPU time	13.55 seconds
Started	Aug 10 07:37:03 PM PDT 24
Finished	Aug 10 07:37:17 PM PDT 24
Peak memory	265660 kb
Host	smart-eff41643-aefa-40ad-bbcc-f0bd81e165a1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295095695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.flash_ctrl_prog_reset.1295095695
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.2623672007
Short name	T660
Test name
Test status
Simulation time	516785200 ps
CPU time	953.74 seconds
Started	Aug 10 07:36:55 PM PDT 24
Finished	Aug 10 07:52:49 PM PDT 24
Peak memory	286972 kb
Host	smart-d706fe1c-7cc9-4cea-8443-0361460ac493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623672007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2623672007
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.4265404967
Short name	T320
Test name
Test status
Simulation time	84083200 ps
CPU time	32.61 seconds
Started	Aug 10 07:37:05 PM PDT 24
Finished	Aug 10 07:37:38 PM PDT 24
Peak memory	274260 kb
Host	smart-a321a9d1-8942-4504-ae22-ab377a368c73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265404967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.4265404967
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.2645643976
Short name	T427
Test name
Test status
Simulation time	555131100 ps
CPU time	113.34 seconds
Started	Aug 10 07:37:06 PM PDT 24
Finished	Aug 10 07:38:59 PM PDT 24
Peak memory	282508 kb
Host	smart-3819a473-6331-43f8-a696-6f041935ee8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645643976 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.2645643976
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.1331663781
Short name	T1109
Test name
Test status
Simulation time	9471155400 ps
CPU time	153.91 seconds
Started	Aug 10 07:37:03 PM PDT 24
Finished	Aug 10 07:39:38 PM PDT 24
Peak memory	282552 kb
Host	smart-3b6b187b-d1ac-4f57-8f80-ad3f8d23181c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1331663781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1331663781
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.3432426585
Short name	T939
Test name
Test status
Simulation time	5130756800 ps
CPU time	117.36 seconds
Started	Aug 10 07:37:06 PM PDT 24
Finished	Aug 10 07:39:03 PM PDT 24
Peak memory	282588 kb
Host	smart-1b3bb424-de07-49fb-acca-54642ea843fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432426585 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3432426585
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.2524165359
Short name	T1097
Test name
Test status
Simulation time	7040526100 ps
CPU time	528.45 seconds
Started	Aug 10 07:37:03 PM PDT 24
Finished	Aug 10 07:45:52 PM PDT 24
Peak memory	319700 kb
Host	smart-afa30d50-254f-4b8f-addc-5f295bea591d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524165359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.2524165359
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.2902948849
Short name	T757
Test name
Test status
Simulation time	1664083700 ps
CPU time	242 seconds
Started	Aug 10 07:37:02 PM PDT 24
Finished	Aug 10 07:41:04 PM PDT 24
Peak memory	283960 kb
Host	smart-b3942b10-c98a-48f0-ae3b-11971bbbc58e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902948849 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_derr.2902948849
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.709466230
Short name	T40
Test name
Test status
Simulation time	67968500 ps
CPU time	29.11 seconds
Started	Aug 10 07:37:03 PM PDT 24
Finished	Aug 10 07:37:32 PM PDT 24
Peak memory	276320 kb
Host	smart-890c291f-a450-4fb2-87ef-d871ca8718aa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709466230 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.709466230
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.2480347972
Short name	T744
Test name
Test status
Simulation time	7549161000 ps
CPU time	253.88 seconds
Started	Aug 10 07:37:02 PM PDT 24
Finished	Aug 10 07:41:16 PM PDT 24
Peak memory	295828 kb
Host	smart-7b5bedaf-08cd-494d-a043-3ab3c1faefb4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480347972 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.flash_ctrl_rw_serr.2480347972
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.1092224705
Short name	T679
Test name
Test status
Simulation time	2774577800 ps
CPU time	74.54 seconds
Started	Aug 10 07:37:10 PM PDT 24
Finished	Aug 10 07:38:24 PM PDT 24
Peak memory	264392 kb
Host	smart-8dbeb3fb-984b-4e08-a91b-b6e953c72358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092224705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1092224705
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.1833144974
Short name	T364
Test name
Test status
Simulation time	112500900 ps
CPU time	100.94 seconds
Started	Aug 10 07:36:56 PM PDT 24
Finished	Aug 10 07:38:37 PM PDT 24
Peak memory	276888 kb
Host	smart-4213dafe-2b9f-4758-939b-65d06fd9863f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833144974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1833144974
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.1831551373
Short name	T636
Test name
Test status
Simulation time	2052881100 ps
CPU time	176.96 seconds
Started	Aug 10 07:36:55 PM PDT 24
Finished	Aug 10 07:39:52 PM PDT 24
Peak memory	265828 kb
Host	smart-419220a2-c3ea-42e9-883b-35c3c9af0c46
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831551373 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.1831551373
Directory	/workspace/9.flash_ctrl_wo/latest

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