Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25416780	1		T1	970		T2	11653		T3	72
full_word	7606591	1		T1	296		T2	8603		T3	50

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33023031	1		T1	1266		T2	20256		T3	122
auto[TlIntgErrCmd]	113	1		T101	6		T216	3		T218	11
auto[TlIntgErrData]	121	1		T101	3		T216	5		T218	8
auto[TlIntgErrBoth]	106	1		T101	1		T216	2		T218	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28625363	1		T1	1006		T2	17351		T3	72
auto[1]	4398008	1		T1	260		T2	2905		T3	50

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24735321	1		T1	942		T2	10923		T3	68
auto[TlIntgErrNone]	partial	auto[1]	681150	1		T1	28		T2	730		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	3889884	1		T1	64		T2	6428		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	3716676	1		T1	232		T2	2175		T3	46
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T101	3		T218	3		T238	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T101	3		T216	3		T218	6
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T218	2		T277	1		T351	2
auto[TlIntgErrData]	partial	auto[0]	62	1		T101	1		T216	2		T218	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T101	2		T216	2		T218	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T216	1		T350	1		T348	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T218	2		T238	1		T274	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T101	1		T216	1		T238	6
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T216	1		T218	1		T238	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T350	1		T354	3		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T238	1		T281	1		T277	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19210	1		T63	332		T100	1000		T101	9
full_word	3780585	1		T1	116		T2	16914		T3	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3799474	1		T1	116		T2	16914		T3	7
auto[TlIntgErrCmd]	88	1		T101	4		T216	3		T218	5
auto[TlIntgErrData]	119	1		T101	2		T216	2		T218	7
auto[TlIntgErrBoth]	114	1		T101	3		T216	4		T218	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3775604	1		T1	116		T2	16914		T3	7
auto[1]	24191	1		T63	407		T100	1492		T101	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1289	1		T63	4		T100	73		T102	11
auto[TlIntgErrNone]	partial	auto[1]	17630	1		T63	328		T100	927		T102	411
auto[TlIntgErrNone]	full_word	auto[0]	3774186	1		T1	116		T2	16914		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	6369	1		T63	79		T100	565		T102	185
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T101	1		T238	3		T274	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T101	3		T216	1		T218	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T216	2		T238	2		T281	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T350	1		T308	1		T351	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T101	1		T216	1		T218	3
auto[TlIntgErrData]	partial	auto[1]	61	1		T101	1		T216	1		T218	4
auto[TlIntgErrData]	full_word	auto[0]	1	1		T353	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T277	1		T308	1		T353	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T101	1		T218	3		T238	5
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T101	2		T216	4		T218	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T242	1		T281	1		T277	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T238	1		T242	1		T350	1