Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1544415924	1541303700	0	0
CheckNGreaterZero_A	4188	4188	0	0
GntImpliesReady_A	1544415924	408543733	0	0
GntImpliesValid_A	1544415924	408543733	0	0
GrantKnown_A	1544415924	1541303700	0	0
IdxKnown_A	1544415924	1541303700	0	0
IndexIsCorrect_A	1544415924	408543733	0	0
NoReadyValidNoGrant_A	1544415924	174857170	0	0
Priority_A	1544415924	432369973	0	0
ReadyAndValidImplyGrant_A	1544415924	408543733	0	0
ReqAndReadyImplyGrant_A	1544415924	408543733	0	0
ReqImpliesValid_A	1544415924	432369973	0	0
ValidKnown_A	1544415924	1541303700	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	1541303700	0	0
T1	15096	14872	0	0
T2	207680	207384	0	0
T3	3980	3768	0	0
T4	242372	241996	0	0
T15	2325360	2324828	0	0
T16	477084	477020	0	0
T17	6452	5712	0	0
T18	618168	617868	0	0
T19	42820	42564	0	0
T20	5464	4864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4188	4188	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	408543733	0	0
T1	15096	3814	0	0
T2	207680	45538	0	0
T3	3980	86	0	0
T4	242372	48818	0	0
T15	2325360	34084	0	0
T16	477084	85178	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	236	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	408543733	0	0
T1	15096	3814	0	0
T2	207680	45538	0	0
T3	3980	86	0	0
T4	242372	48818	0	0
T15	2325360	34084	0	0
T16	477084	85178	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	236	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	1541303700	0	0
T1	15096	14872	0	0
T2	207680	207384	0	0
T3	3980	3768	0	0
T4	242372	241996	0	0
T15	2325360	2324828	0	0
T16	477084	477020	0	0
T17	6452	5712	0	0
T18	618168	617868	0	0
T19	42820	42564	0	0
T20	5464	4864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	1541303700	0	0
T1	15096	14872	0	0
T2	207680	207384	0	0
T3	3980	3768	0	0
T4	242372	241996	0	0
T15	2325360	2324828	0	0
T16	477084	477020	0	0
T17	6452	5712	0	0
T18	618168	617868	0	0
T19	42820	42564	0	0
T20	5464	4864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	408543733	0	0
T1	15096	3814	0	0
T2	207680	45538	0	0
T3	3980	86	0	0
T4	242372	48818	0	0
T15	2325360	34084	0	0
T16	477084	85178	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	236	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	174857170	0	0
T1	15096	564	0	0
T2	207680	57928	0	0
T3	3980	320	0	0
T4	242372	61956	0	0
T15	2325360	1176028	0	0
T16	477084	2636912	0	0
T17	6452	730	0	0
T18	618168	256	0	0
T19	42820	256	0	0
T20	5464	804	0	0
T25	0	40	0	0
T53	0	284	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	432369973	0	0
T1	15096	3820	0	0
T2	207680	74842	0	0
T3	3980	86	0	0
T4	242372	78908	0	0
T15	2325360	579784	0	0
T16	477084	541936	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	334	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	408543733	0	0
T1	15096	3814	0	0
T2	207680	45538	0	0
T3	3980	86	0	0
T4	242372	48818	0	0
T15	2325360	34084	0	0
T16	477084	85178	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	236	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	408543733	0	0
T1	15096	3814	0	0
T2	207680	45538	0	0
T3	3980	86	0	0
T4	242372	48818	0	0
T15	2325360	34084	0	0
T16	477084	85178	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	236	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	432369973	0	0
T1	15096	3820	0	0
T2	207680	74842	0	0
T3	3980	86	0	0
T4	242372	78908	0	0
T15	2325360	579784	0	0
T16	477084	541936	0	0
T17	6452	340	0	0
T18	618168	268802	0	0
T19	42820	64	0	0
T20	5464	366	0	0
T53	0	334	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544415924	1541303700	0	0
T1	15096	14872	0	0
T2	207680	207384	0	0
T3	3980	3768	0	0
T4	242372	241996	0	0
T15	2325360	2324828	0	0
T16	477084	477020	0	0
T17	6452	5712	0	0
T18	618168	617868	0	0
T19	42820	42564	0	0
T20	5464	4864	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386103981	385325925	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	386103981	103131994	0	0
GntImpliesValid_A	386103981	103131994	0	0
GrantKnown_A	386103981	385325925	0	0
IdxKnown_A	386103981	385325925	0	0
IndexIsCorrect_A	386103981	103131994	0	0
NoReadyValidNoGrant_A	386103981	45118387	0	0
Priority_A	386103981	109242233	0	0
ReadyAndValidImplyGrant_A	386103981	103131994	0	0
ReqAndReadyImplyGrant_A	386103981	103131994	0	0
ReqImpliesValid_A	386103981	109242233	0	0
ValidKnown_A	386103981	385325925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131994	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131994	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131994	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	45118387	0	0
T1	3774	193	0	0
T2	51920	16459	0	0
T3	995	141	0	0
T4	60593	16983	0	0
T15	581340	294921	0	0
T16	119271	684702	0	0
T17	1613	325	0	0
T18	154542	128	0	0
T19	10705	128	0	0
T20	1366	359	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	109242233	0	0
T1	3774	819	0	0
T2	51920	19724	0	0
T3	995	36	0	0
T4	60593	20664	0	0
T15	581340	132545	0	0
T16	119271	142246	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131994	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131994	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	109242233	0	0
T1	3774	819	0	0
T2	51920	19724	0	0
T3	995	36	0	0
T4	60593	20664	0	0
T15	581340	132545	0	0
T16	119271	142246	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386103981	385325925	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	386103981	103131903	0	0
GntImpliesValid_A	386103981	103131903	0	0
GrantKnown_A	386103981	385325925	0	0
IdxKnown_A	386103981	385325925	0	0
IndexIsCorrect_A	386103981	103131903	0	0
NoReadyValidNoGrant_A	386103981	45118293	0	0
Priority_A	386103981	109242236	0	0
ReadyAndValidImplyGrant_A	386103981	103131903	0	0
ReqAndReadyImplyGrant_A	386103981	103131903	0	0
ReqImpliesValid_A	386103981	109242236	0	0
ValidKnown_A	386103981	385325925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131903	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131903	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131903	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	45118293	0	0
T1	3774	193	0	0
T2	51920	16459	0	0
T3	995	141	0	0
T4	60593	16983	0	0
T15	581340	294921	0	0
T16	119271	684702	0	0
T17	1613	325	0	0
T18	154542	128	0	0
T19	10705	128	0	0
T20	1366	359	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	109242236	0	0
T1	3774	819	0	0
T2	51920	19724	0	0
T3	995	36	0	0
T4	60593	20664	0	0
T15	581340	132545	0	0
T16	119271	142246	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131903	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	103131903	0	0
T1	3774	817	0	0
T2	51920	12653	0	0
T3	995	36	0	0
T4	60593	13170	0	0
T15	581340	8295	0	0
T16	119271	22280	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	109242236	0	0
T1	3774	819	0	0
T2	51920	19724	0	0
T3	995	36	0	0
T4	60593	20664	0	0
T15	581340	132545	0	0
T16	119271	142246	0	0
T17	1613	91	0	0
T18	154542	86971	0	0
T19	10705	32	0	0
T20	1366	167	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386103981	385325925	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	386103981	101139918	0	0
GntImpliesValid_A	386103981	101139918	0	0
GrantKnown_A	386103981	385325925	0	0
IdxKnown_A	386103981	385325925	0	0
IndexIsCorrect_A	386103981	101139918	0	0
NoReadyValidNoGrant_A	386103981	42310245	0	0
Priority_A	386103981	106942752	0	0
ReadyAndValidImplyGrant_A	386103981	101139918	0	0
ReqAndReadyImplyGrant_A	386103981	101139918	0	0
ReqImpliesValid_A	386103981	106942752	0	0
ValidKnown_A	386103981	385325925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	42310245	0	0
T1	3774	89	0	0
T2	51920	12505	0	0
T3	995	19	0	0
T4	60593	13995	0	0
T15	581340	293093	0	0
T16	119271	633754	0	0
T17	1613	40	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	43	0	0
T25	0	20	0	0
T53	0	142	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	106942752	0	0
T1	3774	1091	0	0
T2	51920	17697	0	0
T3	995	7	0	0
T4	60593	18790	0	0
T15	581340	157347	0	0
T16	119271	128722	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	106942752	0	0
T1	3774	1091	0	0
T2	51920	17697	0	0
T3	995	7	0	0
T4	60593	18790	0	0
T15	581340	157347	0	0
T16	119271	128722	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	167	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386103981	385325925	0	0
CheckNGreaterZero_A	1047	1047	0	0
GntImpliesReady_A	386103981	101139918	0	0
GntImpliesValid_A	386103981	101139918	0	0
GrantKnown_A	386103981	385325925	0	0
IdxKnown_A	386103981	385325925	0	0
IndexIsCorrect_A	386103981	101139918	0	0
NoReadyValidNoGrant_A	386103981	42310245	0	0
Priority_A	386103981	106942752	0	0
ReadyAndValidImplyGrant_A	386103981	101139918	0	0
ReqAndReadyImplyGrant_A	386103981	101139918	0	0
ReqImpliesValid_A	386103981	106942752	0	0
ValidKnown_A	386103981	385325925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1047	1047	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	42310245	0	0
T1	3774	89	0	0
T2	51920	12505	0	0
T3	995	19	0	0
T4	60593	13995	0	0
T15	581340	293093	0	0
T16	119271	633754	0	0
T17	1613	40	0	0
T18	154542	0	0	0
T19	10705	0	0	0
T20	1366	43	0	0
T25	0	20	0	0
T53	0	142	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	106942752	0	0
T1	3774	1091	0	0
T2	51920	17697	0	0
T3	995	7	0	0
T4	60593	18790	0	0
T15	581340	157347	0	0
T16	119271	128722	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	167	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	101139918	0	0
T1	3774	1090	0	0
T2	51920	10116	0	0
T3	995	7	0	0
T4	60593	11239	0	0
T15	581340	8747	0	0
T16	119271	20309	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	106942752	0	0
T1	3774	1091	0	0
T2	51920	17697	0	0
T3	995	7	0	0
T4	60593	18790	0	0
T15	581340	157347	0	0
T16	119271	128722	0	0
T17	1613	79	0	0
T18	154542	47430	0	0
T19	10705	0	0	0
T20	1366	16	0	0
T53	0	167	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386103981	385325925	0	0
T1	3774	3718	0	0
T2	51920	51846	0	0
T3	995	942	0	0
T4	60593	60499	0	0
T15	581340	581207	0	0
T16	119271	119255	0	0
T17	1613	1428	0	0
T18	154542	154467	0	0
T19	10705	10641	0	0
T20	1366	1216	0	0